CN115079759A

CN115079759A - Semiconductor integrated circuit having a plurality of transistors

Info

Publication number: CN115079759A
Application number: CN202210238728.2A
Authority: CN
Inventors: 濑川智贵
Original assignee: Mitsumi Electric Co Ltd
Current assignee: Mitsumi Electric Co Ltd
Priority date: 2021-03-11
Filing date: 2022-03-11
Publication date: 2022-09-20
Also published as: JP2022138853A

Abstract

The invention provides a semiconductor integrated circuit. When the external terminal receives the waveform-delayed voltage, the delay of the voltage waveform is improved. The semiconductor integrated circuit includes: a voltage detection unit that detects a change in a decrease or an increase in the voltage received by the external terminal; a pulse generating unit that generates a pulse signal in response to the voltage detecting unit detecting the change in the voltage; and a voltage change acceleration unit that accelerates a change in the voltage received via the external terminal in response to the pulse signal.

Description

Semiconductor integrated circuit having a plurality of transistors

Technical Field

The present invention relates to a semiconductor integrated circuit.

Background

In an automatic fire alarm notification system having a fire detector and a fire signal receiver connected to each other via a detector line, a method of detecting deterioration of an electric wire or the like by determining a degree of waveform dullness of a communication signal has been proposed (for example, see patent document 1).

In addition, the following methods are proposed: in a sub-device of an automatic fire alarm system, power consumption is reduced by switching a receiving unit to a receiving operation state or a receiving stop state depending on whether or not operating power is supplied to the receiving unit that receives a signal from a main device (for example, see patent document 2).

Patent document

Patent document 1: japanese patent laid-open publication No. 2017-130048

Patent document 2: japanese patent laid-open publication No. 2017-37433

Disclosure of Invention

Problems to be solved by the invention

For example, in a system that transmits information in accordance with a change in voltage applied to a transmission line, a falling waveform or a rising waveform of the voltage may be delayed by a parasitic capacitance or the like of a receiving unit that receives the voltage. When the voltage waveform is delayed, the time until the change of the voltage waveform is transmitted to the circuit of the subsequent stage becomes long, and the response of the circuit of the subsequent stage to the voltage change is delayed.

The disclosed technology aims to improve the delay of a voltage waveform when the waveform-delayed voltage is received through an external terminal.

Means for solving the problems

In order to solve the above-described problems, a semiconductor integrated circuit according to one embodiment of the present invention includes: a voltage detection unit that detects a change in a decrease or an increase in the voltage received by the external terminal; a pulse generating unit that generates a pulse signal in response to the voltage detecting unit detecting the change in the voltage; and a voltage change acceleration unit that accelerates a change in the voltage received via the external terminal in response to the pulse signal.

When the waveform-delayed voltage is received through the external terminal, the delay of the voltage waveform can be improved.

Drawings

Fig. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention.

Fig. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit of fig. 1.

Fig. 3 is a circuit diagram showing an example of another semiconductor integrated circuit.

Fig. 4 is a circuit diagram showing another example of another semiconductor integrated circuit.

Fig. 5 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit of the present invention.

Fig. 6 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit of fig. 5.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, the same reference numerals as the voltage names are used for the voltage lines, terminals, and nodes for transmitting voltages, and the same reference numerals as the signal names are used for the signal lines, terminals, and nodes for transmitting signals. In each drawing, the same components are denoted by the same reference numerals, and redundant description thereof may be omitted.

(first embodiment)

Fig. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit 100 shown in fig. 1 has a function of improving delay of a falling waveform of a voltage Rx when the voltage Rx received via the external terminal Rx is transferred to a circuit of a subsequent stage. The semiconductor integrated circuit 100 includes a voltage detection unit 10 that detects a change in the drop of the voltage Rx, a pulse generation unit 20, and a voltage change acceleration unit 30. For example, the semiconductor integrated circuit 100 is mounted on a receiver of a communication system, and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

The voltage detection unit 10 includes resistance elements R11, R12, R13, R14, a capacitance element C11, and a comparator CMP 11. The resistor elements R11 and R12 are connected IN series between the external terminal Rx and the ground terminal GND via a connection node to the input terminal IN-to the negative side of the comparator CMP 11. Hereinafter, the voltage line connected to the external terminal Rx is also referred to as a voltage line Rx. The resistance elements R13 and R14 are connected IN series between the voltage line Rx and the ground line GND via a connection node to the input terminal IN + on the positive side of the comparator CMP 11. The capacitive element C11 is connected between the input terminal IN-and the ground line GND.

The resistor elements R11 and R12 are an example of a first voltage-dividing circuit that generates a first divided voltage at a connection node between the resistor elements R11 and R12 and supplies the generated first divided voltage to the input terminal IN-. The resistor elements R13 and R14 are examples of a second voltage dividing circuit that generates a second divided voltage at a connection node between the resistor elements R13 and R14 and supplies the generated second divided voltage to the input terminal IN +. The resistance values of the resistance elements R11, R12, R13, and R14 are set so that the voltage at the input terminal IN + (the second divided voltage) is higher than the voltage at the input terminal IN (-the first divided voltage) when the voltage Rx is maintained constant.

IN the voltage detection unit 10 of fig. 1, since the load (the capacitive element C11) is connected to the input terminal IN-, when the voltage Rx decreases, the voltage IN-can be decreased at a rate slower than the rate at which the voltage IN +. As a result, when the voltage Rx drops, the voltage IN + can be temporarily made lower than the voltage IN — and as will be described later, a low-level pulse signal (COUT) can be output from the comparator CMP 11.

IN the drop of the voltage Rx, the rate of decrease of the voltage Rx from the high level value when the voltage IN + becomes lower than the voltage IN-is substantially the same regardless of the high level value. Therefore, for example, regardless of the specification of the high level value of the voltage R, when the voltage Rx is decreased to a certain ratio (for example, 70%) of the high level value, the decrease of the voltage Rx can be accelerated. Here, the fixed ratio is a ratio of the voltage Rx when a difference between a high level value and a low level value of the voltage Rx is 100%. Therefore, even when the electrical specification of the high level value of the voltage Rx is different for each system on which the semiconductor integrated circuit 100 is mounted, when the voltage Rx is reduced to a certain ratio, the n-channel transistor NM of the voltage change accelerating unit 30, which will be described later, can be turned on. Although not particularly limited, the high level value of the voltage Rx is 34V, 24V, or 10V, and the low level value of the voltage Rx is 8V, 6V, or 2V, for example.

The comparator CMP11 outputs the output signal COUT at a high level when the voltage received by the input terminal IN + is greater than the voltage received by the input terminal IN-. The comparator CMP11 outputs the output signal COUT at a low level when the voltage received at the input terminal IN + is smaller than the voltage received at the input terminal IN-. Although not particularly limited, the comparator CMP11 is a hysteresis comparator. The output signal COUT is an example of the comparison result signal.

The pulse generating section 20 includes inverters IV11 and IV12, a resistance element R15, a capacitance element C12, and an OR gate OR. The inverter IV11 and the resistance element R15 are connected in series between the output node COUT of the comparator CMP11 and one input of the OR gate OR. One end of the capacitive element C12 is connected between the resistive element R15 and one input of the OR gate OR, and the other end of the capacitive element C12 is connected to the ground line GND. The resistance element R15 and the capacitance element C12 function as a time constant circuit (delay circuit) that delays the output signal from the inverter IV11 by a predetermined time. The predetermined time delayed by the time constant circuit is determined according to a required pulse width amount of the pulse signal PLS described later.

The OR gate OR receives the output signal COUT and a signal in which the signal obtained by inverting the output signal COUT by the inverter IV11 is delayed by a predetermined time. Then, the OR gate OR outputs the pulse signal PLS0 of a low level in synchronization with the falling edge of the output signal COUT. The inverter IV12 inverts the logic of the low-level pulse signal PLS0 and outputs the high-level pulse signal PLS. Therefore, the semiconductor integrated circuit 100 outputs the pulse signal PLS at the high level as a fall detection signal in response to detection of the fall of the voltage Rx.

The voltage change acceleration section 30 includes an n-channel transistor NM having a gate (control terminal) receiving the pulse signal PLS, a drain connected to the voltage line Rx, and a source connected to the ground line GND. For example, the n-channel Transistor NM is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited to a MOSFET and may be a switching element having a control terminal such as an NPN bipolar Transistor. The n-channel transistor NM turns on the drain-source in response to the pulse signal PLS shifting to the high level, and draws charge from the voltage line Rx during the high level period. In this way, the n-channel transistor NM functions as a discharge element. This makes it possible to increase the falling speed when the voltage Rx falls, and to improve the delay of the falling waveform of the voltage Rx supplied via the external terminal Rx.

As described later, when the voltage Rx falls, the comparator CMP11 outputs a pulse signal of a low level. Therefore, when the accuracy of the pulse width of the pulse signal PLS is not required, the pulse generating unit 20 is not provided, and the output of the comparator CMP11 may be connected to the gate of the n-channel transistor NM only via the inverter IV 12.

Fig. 2 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit 100 of fig. 1. For example, when the voltage Rx received by the external terminal Rx is maintained at a high level value or a low level value, the voltage IN + supplied to the input terminal IN + becomes higher than the input voltage IN-supplied to the input terminal IN-. The comparator CMP11 outputs the output signal COUT at a high level. The low level value of the voltage Rx is a predetermined voltage determined by the electrical specification of the semiconductor integrated circuit 100, and is higher than the ground voltage GND.

In the example shown in fig. 2, when the voltage Rx changes to a low level value, the falling waveform is delayed by a parasitic capacitance of a circuit connected to the external terminal Rx. For example, a diode bridge is connected to the external terminal Rx, and a voltage Rx is supplied from the diode bridge to the external terminal Rx, or a surge absorber is connected to the external terminal Rx. In this case, the waveform when the voltage Rx varies is delayed due to the parasitic capacitance of the diode bridge or the surge absorber.

IN FIG. 2, as the voltage Rx decreases, the voltages IN +, IN-decrease. At this time, the voltage IN-of the input terminal IN-to which the capacitive element C11 is connected drops at a slower rate than the voltage IN +. That is, the voltage IN-falls slower than the voltage IN + due to the influence of the capacitive element C11.

Therefore, the voltage IN + becomes lower than the voltage IN-, the comparator CMP11 changes the output signal COUT from high level to low level. Then, the pulse generating unit 20 outputs the high-level pulse signal PLS in response to the falling edge of the output signal COUT. The n-channel transistor NM is turned on while the pulse signal PLS is at the high level, and draws charges from the voltage line Rx to accelerate the falling speed of the voltage Rx.

The high-level period of the pulse signal PLS is set by a time constant circuit including the resistor element R15 and the capacitor element C12. Therefore, the voltage Rx can be quickly set to a predetermined low level value by an appropriate time constant circuit, and the voltage Rx is suppressed from decreasing below the low level value. The dotted line shown by the waveform of the voltage Rx is a waveform when the semiconductor integrated circuit 100 does not include the voltage detection unit 10, the pulse generation unit 20, and the voltage change acceleration unit 30.

As described above, in the first embodiment, the speed of the drop of the voltage Rx received by the external terminal Rx can be increased, and the delay of the drop waveform of the voltage Rx can be improved. This enables the processing of the subsequent circuit that operates in response to the drop in the voltage Rx to be started early, and thus the performance of the semiconductor integrated circuit 100 or the performance of a system including the semiconductor integrated circuit 100 can be improved. Alternatively, malfunction of a subsequent circuit can be prevented, and the reliability of the semiconductor integrated circuit 100 or the reliability of a system including the semiconductor integrated circuit 100 can be improved.

By supplying the 2 divided voltages generated by the resistance division to the input terminals IN +, IN-of the comparator CMP11, respectively, the voltage IN + can be made higher than the voltage IN-when the voltage Rx is maintained constant. Since the load (the capacitor element C11) is connected to the input terminal IN-, when the voltage Rx decreases, the voltage IN-can be decreased at a slower rate than the voltage IN +. Thus, when the voltage Rx drops, the voltage IN + can be temporarily made lower than the voltage IN — and the comparator CMP11 can output a low-level pulse signal (COUT).

Further, by providing the pulse generating unit 20, the on period of the n-channel transistor NM can be set to an arbitrary period by the time constant circuit. In addition, by extracting charges from the voltage line Rx by the n-channel transistor NM, the delay of the falling waveform of the voltage Rx can be improved by a simple discharge element.

IN the drop of the voltage Rx, the rate of decrease of the voltage Rx from the high level value when the voltage IN + becomes lower than the voltage IN-is substantially the same regardless of the high level value. Therefore, even when the electrical specification of the high level value of the voltage Rx is different for each system in which the semiconductor integrated circuit 100 is mounted, the n-channel transistor NM can be turned on when the voltage Rx is reduced to a certain ratio.

In the first embodiment, the following example is explained: when the voltage Rx is kept constant, the voltage at the input terminal IN + is set to be higher than the voltage at the input terminal IN-by resistance division, and the capacitive element C11 is connected to the input terminal IN-. However, the voltage at the input terminal IN-may be set to be higher than the voltage at the input terminal IN + when the voltage Rx is maintained constant by resistance division, and the capacitive element C11 may be connected to the input terminal IN +.

In this case, when the decrease of the voltage Rx is detected, the comparator CMP11 temporarily outputs the high-level output signal COUT. The pulse generating section 20 includes, for example, an and gate instead of the OR gate OR and the inverter IV12 of fig. 1, in order to output the high-level pulse signal PLS in response to a rising edge of the output signal COUT.

Fig. 3 is a circuit diagram showing an example (comparative example) of another semiconductor integrated circuit. The same elements as those in fig. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit 102 shown in fig. 3 includes a voltage detection unit 12, a pulse generation unit 22, and a voltage change acceleration unit 30. For example, the semiconductor integrated circuit 102 is mounted on a receiver of a communication system, and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

The voltage detector 12 includes a voltage divider circuit including resistance elements R21 and R22, a reference voltage generation circuit 18, and a comparator CMP 11. For example, the divided voltage generated by the voltage dividing circuit is supplied to the input terminal IN-of the comparator CMP 11. The reference voltage generation circuit 18 generates a reference voltage VREF, and supplies the generated reference voltage VREF to the input terminal IN + of the comparator CMP 11.

In the case where the divided voltage is lower than the reference voltage VREF, the comparator CMP11 outputs the output signal COUT of a high level. In the case where the divided voltage is higher than the reference voltage VREF, the comparator CMP11 outputs the output signal COUT of a low level.

The pulse generating section 22 includes an inverter IV11, a resistance element R15, a capacitance element C12, AND an AND gate AND. The pulse generating unit 22 has the same configuration as the pulse generating unit 20 of fig. 1 except that an AND gate AND is provided instead of the OR gate OR AND the inverter IV 12. The pulse generator 22 outputs a high-level pulse signal PLS in synchronization with a rising edge of the output signal COUT from the comparator CMP 11. Then, the drop of the voltage Rx is accelerated by the n-channel transistor NM turned on according to the pulse signal PLS of the high level.

In the voltage detection section 12 shown in fig. 3, the comparator CMP11 compares the voltage value with a fixed reference voltage VREF. Therefore, when the voltage Rx falls, the pulse signal PLS is generated when the voltage Rx becomes lower than the reference voltage VREF. In other words, the amount of decrease in the voltage Rx until the n-channel transistor NM is turned on is different when the electrical specification of the high value of the voltage Rx is high than when the electrical specification of the voltage Rx is low. Therefore, depending on the electrical specifications of various systems in which the semiconductor integrated circuit 102 is mounted, the semiconductor integrated circuit 102 cannot be used when, for example, it is necessary to accelerate the decrease in the voltage Rx when the voltage Rx is decreased to 70% of the high level value of the voltage Rx.

Fig. 4 is a circuit diagram showing another example (comparative example) of another semiconductor integrated circuit. The same elements as those in fig. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit 104 shown in fig. 4 includes the voltage detection unit 14 and the voltage change acceleration unit 30. For example, the semiconductor integrated circuit 104 is mounted on a receiver of a communication system, and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

The voltage detection unit 14 includes resistance elements R41, R42, R43, and R44, a capacitance element C41, an n-channel transistor NM41, and a buffer circuit BUF. The resistance element R41 is connected between the external terminal Rx and one end of the capacitance element C41. The resistance elements R42 and R43 are connected in series between the power supply line VDD and the ground line GND via the other end of the capacitor element C41.

The resistance element R44 and the n-channel transistor NM are connected in series between the power supply line VDD and the ground line GND. The gate of the n-channel transistor NM41 is connected to the other end of the capacitive element C41. The drain of the n-channel transistor NM41 is connected to the resistance element R44 and the input terminal of the buffer circuit BUF.

The buffer circuit BUF operates by the power supply voltage VDD. The buffer circuit BUF outputs a high level when the drain voltage of the n-channel transistor NM is higher than a logic threshold voltage, and outputs a low level when the drain voltage of the n-channel transistor NM is lower than the logic threshold voltage. The n-channel transistor NM is turned on while the buffer circuit BUF outputs a high level, and charges are extracted from the voltage line Rx.

In the semiconductor integrated circuit 100 shown in fig. 4, in the case where the voltage Rx has decreased, the gate voltage of the n-channel transistor NM41 temporarily decreases by AC coupling of the capacitive element C41. Thereby, the resistance between the drain and the source of the n-channel transistor NM41 decreases, the input voltage of the buffer circuit BUF becomes equal to or higher than the logic threshold voltage, and the buffer circuit BUF outputs a high level at this time. And, the n-channel transistor NM is turned on.

However, in fig. 4, since the decrease in the voltage Rx is detected by the AC coupling of the capacitor C41, a relatively large capacitor C41 is required, and the circuit size of the semiconductor integrated circuit 104 increases. When the voltage Rx decreases in a frequency band that is shifted from the frequency band determined by the capacitive element C41 and the resistive elements R42 and R43, the charge cannot be extracted from the voltage line Rx. In contrast, in the semiconductor integrated circuit 100 shown in fig. 1, the charges can be extracted from the voltage lines Rx without being limited to the frequency band when the voltage Rx is lowered.

(second embodiment)

Fig. 5 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit of the present invention. The same elements as those in fig. 1 are denoted by the same reference numerals, and detailed description thereof is omitted. The semiconductor integrated circuit 106 shown in fig. 5 has a function of improving delay of a rising waveform of a voltage in a case where the voltage Rx received via the external terminal Rx is transmitted to a subsequent stage circuit. The semiconductor integrated circuit 106 includes a voltage detection unit 16 that detects a change in the rise of the voltage Rx, a pulse generation unit 26, and a voltage change acceleration unit 36. For example, the semiconductor integrated circuit 106 is mounted on a receiver of a communication system, and has a function of receiving a voltage signal transmitted from a transmitter of the communication system.

Voltage detection unit 16 has the same configuration as voltage detection unit 10 of fig. 1, except that capacitive element C11 is connected to input terminal IN + of comparator CMP 11. As IN the voltage detection unit 10 of fig. 1, the voltage detection unit 16 is set such that the voltage at the input terminal IN + is higher than the voltage at the input terminal IN-when the voltage Rx is maintained constant. When the voltage Rx rises, the voltage IN + is temporarily lower than the voltage IN-. Thus, the comparator CMP11 outputs a low-level pulse signal (COUT) while the voltage IN + is temporarily lower than the voltage IN-.

The pulse generating unit 26 has the same configuration as the pulse generating unit 20 of fig. 1 except that the inverter IV12 is eliminated. That is, the pulse generating unit 26 outputs the pulse signal PLS from the OR gate OR. Upon receiving the low-level pulse signal (COUT) from the comparator CMP11, the pulse generator 26 outputs the low-level pulse signal PLS as a rise detection signal.

The voltage change acceleration unit 36 includes a p-channel transistor PM having a gate (control terminal) receiving the pulse signal PLS, a drain connected to the external terminal Rx, and a source connected to the power supply line VDD. For example, the p-channel transistor PM is a MOSFET, but is not limited to a MOSFET, and may be a switching element having a control terminal such as a PNP bipolar transistor. The p-channel transistor PM turns on (turns on) the drain-source line while the pulse signal PLS is at the low level, and supplies charges from the power supply line VDD to the voltage line Rx. In this way, the p-channel transistor PM functions as a charging element. This makes it possible to increase the rising speed when the voltage Rx rises, and to improve the delay of the rising waveform of the voltage Rx.

As described later, when the voltage Rx rises, the comparator CMP11 outputs a pulse signal of low level. Therefore, when the accuracy of the pulse width is not required, the output of the comparator CMP11 may be directly connected to the gate of the p-channel transistor PM without providing the pulse generating unit 26. The voltage change acceleration unit 36 may include an n-channel transistor, in addition to the p-channel transistor PM, having a gate receiving the pulse signal PLS, a source connected to the voltage line Rx, and a drain connected to the power supply line VDD. That is, the voltage change accelerating unit 36 may have a CMOS (Complementary Metal Oxide Semiconductor) transfer gate.

IN the voltage detection unit 16, as IN the voltage detection unit 10 of fig. 1, the voltage IN + can be made higher than the voltage IN-when the voltage Rx is maintained constant. Thus, when the voltage Rx rises, the voltage IN + can be temporarily made lower than the voltage IN — and a low-level pulse signal can be output from the comparator CMP 11.

IN addition, IN the rise of the voltage Rx, the rate of rise of the voltage Rx from the low level value when the voltage IN + becomes lower than the voltage IN-is substantially the same regardless of the low level value. Therefore, for example, when the voltage Rx rises to a certain ratio (for example, 30%) with respect to the low level value, the rise of the voltage Rx can be accelerated. Here, the fixed ratio is a ratio of the voltage Rx when a difference between a high level value and a low level value of the voltage Rx is 100%. Therefore, even when the electrical specification of the low level value of the voltage Rx is different for each system in which the semiconductor integrated circuit 106 is mounted, the p-channel transistor PM can be turned on when the voltage Rx rises to a certain ratio.

Fig. 6 is a waveform diagram showing an example of the operation of the semiconductor integrated circuit 106 in fig. 5. The same operation as that in fig. 2 will not be described in detail. The low level value of the voltage Rx is a predetermined voltage determined by the electrical specification of the semiconductor integrated circuit 106, and is higher than the ground voltage GND.

In the example shown in fig. 6, when the voltage Rx changes to a high level, the rising waveform is delayed by a parasitic capacitance such as a diode bridge or a surge absorber connected to the external terminal Rx. IN FIG. 6, as the voltage Rx rises, the voltages IN +, IN-rise. The voltage IN + rises slower than the voltage IN-due to the influence of the capacitive element C11.

During the period when the voltage IN + is temporarily lower than the voltage IN-, the comparator CMP11 changes the output signal COUT from the high level to the low level. The pulse generating unit 26 outputs a low-level pulse signal PLS in synchronization with the falling edge of the output signal COUT. The p-channel transistor PM is turned on while the pulse signal PLS is at the low level, and supplies charges to the voltage line Rx to accelerate the rising speed of the voltage Rx. The dotted line shown by the waveform of the voltage Rx is a waveform when the semiconductor integrated circuit 106 does not include the voltage detection unit 16, the pulse generation unit 26, and the voltage change acceleration unit 36.

As described above, in the second embodiment, the rising speed of the voltage Rx received by the external terminal Rx can be increased, and the delay of the rising waveform of the voltage Rx can be improved. This enables the processing of the subsequent circuit that operates in response to the rise of the voltage Rx to be started early, and thus the performance of the semiconductor integrated circuit 106 or the performance of a system including the semiconductor integrated circuit 106 can be improved. Alternatively, malfunction of a subsequent circuit can be prevented, and the reliability of the semiconductor integrated circuit 106 or the reliability of a system including the semiconductor integrated circuit 106 can be improved.

By supplying the 2 divided voltages generated by the resistance division to the input terminals IN + and IN-of the comparator CMP11, respectively, the voltage IN + can be made higher than the voltage IN-while the voltage Rx is kept constant. Further, since the load (the capacitor element C11) is connected to the input terminal IN +, when the voltage Rx decreases, the voltage IN + can be decreased at a slower rate than the voltage IN-. Thus, when the voltage Rx rises, the voltage IN + can be temporarily made lower than the voltage IN — and the comparator CMP11 can output a low-level pulse signal (COUT).

The voltage detection unit 16 outputs a low-level pulse signal (COUT) when the voltage Rx decreases. Therefore, for example, even if the pulse generating unit 26 is not provided and the output signal COUT is directly output to the gate of the p-channel transistor PM, the rising speed at the time of rising of the voltage Rx can be increased, and the delay of the rising waveform of the voltage Rx can be improved. By providing the pulse generator 26, the on period of the p-channel transistor PM can be set to an arbitrary period by the time constant circuit. In addition, by supplying charges to the voltage line Rx using the p-channel transistor PM, it is possible to improve the delay of the rising waveform of the voltage Rx using a simple charging element.

IN the rise of the voltage Rx, the rate of rise of the voltage Rx from the low level value when the voltage IN + becomes lower than the voltage IN-is substantially the same regardless of the low level value. Therefore, even when the electrical specification of the low level value of the voltage Rx is different for each system in which the semiconductor integrated circuit 106 is mounted, the p-channel transistor PM can be turned on when the voltage Rx rises to a certain ratio.

In the second embodiment, the following example is explained: when the voltage Rx is kept constant, the voltage at the input terminal IN + is set to be higher than the voltage at the input terminal IN-and the capacitive element C11 is connected to the input terminal IN +. However, the voltage at the input terminal IN-may be set to be higher than the voltage at the input terminal IN + when the voltage Rx is maintained constant by resistance division, and the capacitive element C11 may be connected to the input terminal IN-.

In this case, when detecting the rise of the voltage Rx, the comparator CMP11 outputs the output signal COUT at the high level temporarily. Therefore, the pulse generating unit 20 includes, for example, a nand gate (and gate + inverter) instead of the OR gate OR in fig. 5, in order to output the low-level pulse signal PLS in response to the rising edge of the output signal COUT.

The present invention has been described above based on the embodiments, but the present invention is not limited to the requirements shown in the above embodiments. These components can be changed without departing from the spirit of the present invention, and can be determined as appropriate according to the application mode thereof.

Description of reference numerals

10. 12, 14, 16 voltage detecting part

18 reference voltage generating circuit

20. 22, 26 pulse generating part

30. 36 voltage change accelerating part

100. 102, 104, 106 semiconductor integrated circuit

BUF buffer circuit

C11, C12, C41 capacitance element

CMP11 comparator

COUT output signal

GND grounding wire

IN +, IN-input terminal

IV11, IV12 inverter

NM and NM41 n channel transistor

PLS0, PLS pulse signal

PM p-channel transistor

R11, R12, R13, R14 and R15 resistance elements

R21, R22 resistance element

R41, R42, R43 and R44 resistance elements

Rx external terminal

VDD Power line

The VREF reference voltage.

Claims

1. A semiconductor integrated circuit is provided with:

a voltage detection unit that detects a change in a decrease or an increase in the voltage received by the external terminal;

a pulse generating unit that generates a pulse signal in response to the voltage detecting unit detecting the change in the voltage; and

and a voltage change acceleration unit that accelerates a change in the voltage received via the external terminal in response to the pulse signal.

2. The semiconductor integrated circuit according to claim 1,

the voltage detection unit includes:

a first voltage dividing circuit that divides the voltage received by the external terminal to generate a first divided voltage;

a second voltage dividing circuit that divides the voltage received by the external terminal to generate a second divided voltage higher than the first divided voltage;

a comparator having a first input terminal receiving the first divided voltage and a second input terminal receiving the second divided voltage, and comparing the first divided voltage with the second divided voltage; and

a load connected to any one of the first input terminal and the second input terminal,

the pulse generating unit generates a pulse signal in response to a comparison result signal output from the comparator in accordance with a change in the voltage drop.

3. The semiconductor integrated circuit according to claim 2,

when the voltage has decreased, a decrease in the input voltage of one of the first input terminal and the second input terminal connected to the load is delayed with respect to a decrease in the input voltage of the other of the first input terminal and the second input terminal.

4. The semiconductor integrated circuit according to claim 2 or 3,

the first divided voltage and the second divided voltage are different from each other while the voltage is maintained to be constant,

the load is connected to an input terminal that receives a low divided voltage of the first input terminal and the second input terminal when the voltage is maintained constant.

5. The semiconductor integrated circuit according to any one of claims 1 to 3,

the pulse generating section generates a fall detection signal in response to the voltage detecting section detecting the fall of the voltage.

6. The semiconductor integrated circuit according to claim 5,

the voltage change acceleration unit includes a switch that receives the drop detection signal via a control terminal, one terminal of the switch is connected to the external terminal, and the other terminal of the switch is connected to a ground line.

7. The semiconductor integrated circuit according to claim 6,

the pulse generating unit includes a delay circuit including a resistance element and a capacitance element, and changes a waveform of the pulse signal output to the control terminal according to a time constant of the delay circuit.

8. The semiconductor integrated circuit according to claim 1,

the voltage detection unit includes:

the pulse generating unit generates a pulse signal in response to a comparison result signal output from the comparator in accordance with a change in the rise of the voltage.

9. The semiconductor integrated circuit according to claim 8,

the load is connected to an input terminal that receives a high divided voltage of the first input terminal and the second input terminal when the voltage is maintained constant.

10. The semiconductor integrated circuit according to any one of claims 1, 8, and 9,

the pulse generating unit generates a rise detection signal in response to the voltage detecting unit detecting the rise of the voltage.

11. The semiconductor integrated circuit according to claim 10,

the voltage change acceleration unit includes a switch that receives the rise detection signal via a control terminal, one terminal of which is connected to the external terminal, and the other terminal of which is connected to a power supply line.