CN1150753C - Method and device for preventing OSD display area jumping on screen - Google Patents
Method and device for preventing OSD display area jumping on screen Download PDFInfo
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- CN1150753C CN1150753C CNB991036352A CN99103635A CN1150753C CN 1150753 C CN1150753 C CN 1150753C CN B991036352 A CNB991036352 A CN B991036352A CN 99103635 A CN99103635 A CN 99103635A CN 1150753 C CN1150753 C CN 1150753C
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Abstract
The present invention relates to a device used for preventing an OSD show region from jumping on a screen and a method of the device. The device comprises a timing part, a comparison circuit, a pulse generator generating a first reference signal and a second reference signal, and a multiplexer. The method comprises the steps of generating the first reference signal according to the pulse leading edge of a vertical synchronizing signal, and delaying a period of established time by the second reference signal relatively to the first reference signal. Firstly, the comparison circuit calculates the time difference between corresponding pulse leading edges of vertical/horizontal synchronizing signals. The time difference is compared with a time constant. If time difference is higher than the time constant, an enough buffer distance exists between the pulse leading edges of the horizontal synchronizing signal and the vertical synchronizing signal, and thus, the OSD show region can not jump on the screen.
Description
Invention field:
The present invention relates to the display of a kind of OSD of having (on-screen display) function, the method and the device of on indicator screen, beating particularly relevant for a kind of OSD of preventing viewing area, and this jumping phenomena is normally owing to user institute when adjusting H-phase parameters such as (horiaontal phase, horizontal phases) causes.
Background technology:
Display unit (comprise TV, computer with display or the like) mostly has some adjustable parameter values, allow the user when practical operation, adjust, for example be used for adjusting the H-size and the V-size parameter of viewing area horizontal size and vertical size, and in order to the H-phase that adjusts viewing area horizontal level and upright position and V-phase parameter or the like.These display parameters mostly are to utilize pulse-width modulation (display parameters that the user is set are delivered on the corresponding deflection circuit for pulse width modulation, mode PWM), adjust the state of its video picture.Therefore, on display, all have certain mechanism usually, can allow the user that these display parameters are adjusted.
In present display unit, known have dual mode can provide the user that display parameters are adjusted.First kind of mode is to utilize the light-emitting diode that is installed on the display pannel (Light-emitteddiode LED) and button, adjusts display parameters.When the user utilized options button (select key) to choose a certain specific display parameters, the LED of corresponding these display parameters promptly can light on the panel, and prompting is the selected display parameters that arrive at present.At this moment, the operator just can press adjustment key (adjust key) and adjust display parameter value.The second way is to utilize OSD to show and button is adjusted display parameters, and the difference of itself and first kind of mode mainly is the mode difference of show message.When the user presses options button on the lower panel, i.e. representative triggers the OSD Presentation Function.At this moment, the OSD viewing area just appears on the ad-hoc location on the screen, demonstrates each corresponding display parameters respectively.The user just can utilize options button to select the display parameters that will adjust this moment, and utilizes and adjust key adjustment parameter value.Basically, above-mentioned dual mode does not have too big difference in operation, and the main difference point is the mode difference that message shows.With present use, because first kind of mode needs a large amount of LED, on display effect, can not show a candle to the second way simultaneously, therefore utilize OSD to come the practice of show message more and more general.
Fig. 1 is illustrated in the display with OSD Presentation Function, the block diagram of vision circuit part.With reference to figure 1,, make a simple explanation to the enforcement of OSD.As shown in Figure 1, R (red), G (green), B (blue) represent the three primary colors signal red, green, blue that transmitted by video signal card (video card) respectively, and this is the image signal that institute's desire shows under the normal condition.Under general show state, R, G, B signal see through mixer 8 (its function describes in detail after a while) and amplifier 10, send into CRT (cathoderay tube, cathode ray tube) picture tube 2 and carry out video picture.And in 2 video pictures of CRT picture tube, deflection circuit 4 can be controlled the video picture position of view data, the signal that wherein is used for controlling the video picture position comprises horizontal-drive signal (horizontal synchronizing signal, Hs) and vertical synchronizing signal (vertical synchronizing signal, Vs).Horizontal-drive signal and vertical synchronizing signal all are a kind of pulse signal (comprising a plurality of pulses).Wherein, the adjacent pulse in the horizontal-drive signal is shorter at interval, is used for defining each bar horizontal scanning line (scanning line); Adjacent pulse in the vertical synchronizing signal is longer at interval, then is to be used for defining the frame (frame) that comprises a plurality of horizontal scanning lines.Therefore, the view data on R, G, the B can see through the control of deflection circuit 4, the position of the correspondence on screen of video picture correctly.
When the user triggers the OSD Presentation Function, microcontroller in the display (not shown) promptly reads character data to display from EEPROM (not shown), deliver in the osd circuit 6, produce three look signal Rosd (red), Gosd (green), the Bosd (indigo plant) of corresponding this OSD viewing area.As shown in the figure, osd circuit 6 is sent into Rosd, Gosd, Bosd signal and a blanking signal Blank in the mixer 8 in the lump.The effect of blanking signal Blank is to be used for defining the scope of OSD viewing area on screen, that is, when blanking signal Blank=1 represents that the zone that is showing at present is normal viewing area, mixer 8 promptly can cut out the character data input of Rosd, Gosd, Bosd, and by R, G, B output image data to amplifier 10; When blanking signal Blank=0 represented that the zone that is showing at present is the OSD viewing area, mixer 8 promptly can cut out the input of R, G, B view data, and by Rosd, Gosd, Bosd output character data to amplifier 10.Blanking signal Blank decides according to the relative timing of horizontal-drive signal Hs and vertical synchronizing signal Vs relation, that is to say, by the decision scanning line range, defines corresponding OSD viewing area.For instance, if the 240th scan line is defined as starting position, OSD viewing area, and high 120 scan lines in OSD viewing area; Then osd circuit promptly can calculate from vertical synchronizing signal time of occurrence beginning, begin to export blanking signal Blank=0 when calculating the 240th scan line position, to output blanking signal Blank=1 during the 360th scan line position.
According to the above as can be known, the OSD viewing area is decided by horizontal-drive signal Hs and vertical synchronizing signal Vs, so the association between horizontal-drive signal Hs and the vertical synchronizing signal Vs can have influence on the demonstration of OSD.Problem is in the present display, the adjustment of some display parameters action, as: the H-phase display parameters are adjusted, and can have influence on the relativeness between horizontal-drive signal Hs and the vertical synchronizing signal Hs immediately.Fig. 2 and Fig. 3 are illustrated in the display of known techniques, are illustrated in to adjust before and after the H-phase parameter, and the sequential chart between horizontal-drive signal Hs and the vertical synchronizing signal Vs is in order to the situation of explanation relativeness change.
Sequential as shown in Figure 2, (time T is the pulse leading edge (time T b) of leading (lead) horizontal-drive signal Hs a) to the pulse leading edge of vertical synchronizing signal Vs, that is Tb＞Ta before adjusting; And both pulse leading edges are considerably close.
And when the user adjusts the H-phase parameter, promptly might change the sequencing of horizontal-drive signal Hs with respect to vertical synchronizing signal Vs.Suppose under a certain H-phase adjustment amount, sequential relationship between horizontal-drive signal Hs and the vertical synchronizing signal Vs changes over situation as shown in Figure 3, and the pulse leading edge (time T a ') that this moment occurred horizontal-drive signal Hs takes the lead the phenomenon of the pulse leading edge (time T b ') of vertical synchronizing signal Vs on the contrary.
As mentioned above, osd circuit is to decide when send blanking signal Blank's according to the relativeness between horizontal-drive signal Hs and the vertical synchronizing signal Vs.If therefore the user is when adjusting H-phase, Fig. 2 and shown in Figure 3 when being converted to the phenomenon of " Hs pulse leading edge is leading " by " Vs pulse leading edge is leading " appears, osd circuit just mistake can occur on the calculating scan line position, and make the OSD viewing area differ a scan line, and then can produce the problem of OSD viewing area bob; This is the shortcoming in the known OSD demonstration.
Existing display is that the mode that sees through signal delay is reached at the solution that the problems referred to above proposed.That is to say, if during the problem that beating the OSD viewing area can appear in the combination of having known some signal sequence, just earlier the Hs synchronizing signal is postponed, the relative timing precedence relationship of horizontal synchronization and vertical synchronization is changed.Yet this processing method is merely able to solve at some known particular cases, can not guarantee that all situations can be suitable for.The problem that this also solves for institute of the present invention desire.
Summary of the invention:
In view of this, main purpose of the present invention is to provide a kind of OSD of preventing apparatus and method of beating in the viewing area on screen, can at the situation of synchronizing signal sequence change might take place, solve the problem of beating in the OSD viewing area.
According to above-mentioned purpose, the invention provides the device of beating in a kind of OSD of preventing viewing area on screen, this device comprises the timing piece in order to the generation time constant, time constant and horizontal-drive signal and vertical synchronizing signal pulse leading edge time difference are compared and produce the alternative route of selecting signal, produce the pulse generator of first and second reference signals respectively, and select the multiplexer of a reference signal as clear signal according to above-mentioned selection signal.Wherein, second reference signal postpones a given time with respect to first reference signal.The effect of this device is the clear signal that produces counter in the osd circuit, and this counter is the current scanline line position that is used for calculating in each frame scan process.Its action can be described below.At first, the time difference of respective pulses leading edge compares with time constant in a pulse leading edge of alternative route calculating vertical synchronizing signal and the horizontal-drive signal.If the time difference is higher than time constant, have enough buffer distances between expression level and vertical synchronizing signal pulse leading edge, so multiplexer selects first reference signal as clear signal according to the indication of selecting signal.If the time difference when being lower than time constant, is then represented the respective pulses buffer distance deficiency of level and vertical synchronizing signal, just so multiplexer according to the indication of selecting signal, select second reference signal as clear signal.By this, this device can determine corresponding processing according to the sequential relationship between level and vertical synchronizing signal, makes the OSD viewing area can not influence to some extent because of the adjustment of other parameters.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Brief Description Of Drawings:
Fig. 1 is illustrated in the display with OSD Presentation Function, the block diagram of vision circuit part;
Fig. 2 and Fig. 3 are illustrated in the display of known techniques, and horizontal-drive signal Hs and vertical synchronizing signal Vs are before adjusting the H-phase parameter and adjusted sequential chart;
Fig. 4 represents to prevent in the embodiment of the invention circuit block diagram of beating the OSD viewing area;
The operational flowchart of Fig. 5 presentation graphs 4 shown devices;
Fig. 6 represents the signal sequential chart of first example in the embodiment of the invention;
Fig. 7 represents the signal sequential chart of second example in the embodiment of the invention;
Fig. 8 represents the signal sequential chart of the 3rd example in the embodiment of the invention.
Embodiment:
Proposed by the invention prevent method and the device of beating in the OSD viewing area on screen, mainly be that the mode of utilizing signal to select reaches purpose of the present invention, soluble situation also is not limited to some specific, known sequential relationship simultaneously, thoroughly solves the problem of beating in the OSD viewing area by this.The phenomenon of beating in the viewing area can take place in general osd circuit, mainly be because between horizontal-drive signal and the vertical synchronizing signal on sequential very near due to.That is the respective pulses of horizontal-drive signal and vertical synchronizing signal is too close, and when the user when adjusting parameter such as H-phase, just may make corresponding sequential precedence relationship between the two occur changing, cause the osd circuit erroneous judgement.The method applied in the present invention is the sequential relationship between first determined level synchronizing signal and the vertical synchronizing signal, selects to be applicable to the clear signal of present circumstances again.Following conjunction with figs. describes content of the present invention in detail with an embodiment.
Fig. 4 represents to prevent in the embodiment of the invention circuit block diagram of beating the OSD viewing area.As shown in the figure, this circuit comprises comparison circuit 20, timer 22, pulse generator 24 and multiplexer 26.In circuit shown in Figure 4, mainly be the clear signal Clear that will produce a counter, this clear signal is delivered in the counter (not shown) that calculates scan line in the osd circuit.As previously mentioned, osd circuit is the relative timing relation according to horizontal-drive signal Hs and vertical synchronizing signal Vs, decides the scan line zone that will hide from view.And the practice of side circuit is to utilize a counter, and the number of calculated level synchronizing signal Hs is judged the scan line position that scans at present.In known techniques, this counter is fixed on the pulse leading edge of each vertical synchronizing signal Vs, and can be eliminated (clear) is 0, uses the starting position of a picture frame of expression.And during the pulse at every turn detecting horizontal-drive signal Hs (beginning of a scan line of expression), just the contents value with counter increases by 1, when the contents value of counter reaches the scan line of the default viewing area of OSD, just send corresponding blanking signal Blank.Embodiments of the invention are the adjustment that see through counter initialization signal Clear, control the scan line position of OSD viewing area actual displayed, use the jumping phenomena that prevents the OSD viewing area.
The processing mode of Fig. 4 circuit is to judge between the pulse leading edge relative position of present horizontal-drive signal Hs and vertical synchronizing signal Vs earlier, whether has enough buffer distances and can avoid occurring beating of OSD viewing area.If the result who is detected shows in the time of can not beating, just directly select the first reference signal CLR1 as straight positive counter initialization signal Clear; In the time of if possible can beating, just select through the second reference signal CLR2 after the delay processing.As shown in Figure 4, comparison circuit 20 receives horizontal/vertical synchronization signals Hs/Vs, and therefore the direct pulse leading edge of basis vertical synchronizing signal Vs wherein produces the first reference signal CLR1.On the other hand, pulse generator 24 also is that the pulse leading edge according to vertical synchronizing signal Vs decides the second reference signal CLR2, but still need and to consider T3 time of delay that timer 22 is provided, allow have T3 time of delay between the pulse of the second reference signal CLR2 and the first reference signal CLR1.Time of delay T3 effect, will OSD viewing area beat (can select CLR2 as clear signal Clear this moment) under the situation may take place exactly, pulse on the clear signal Clear can be interpulse with immediate two horizontal-drive signal Hs, all keep certain buffer distance, to guarantee when adjusting other display parameters, can not to change the scan line position that begins to count.
Another purpose of comparison circuit 20 is to be used for the relativeness of comparison level synchronizing signal Hs and vertical synchronizing signal Vs respective pulses leading edge, uses decision and will select that reference signal as real counter initialization signal.In the present embodiment, the time difference T1 of the pulse leading edge that comparison circuit 20 can be obtained vertical synchronizing signal Vs corresponding pulse leading edge in the horizontal-drive signal Hs, again time difference T1 is compared with the time constant T2 that timer 22 is sent here again, use to produce and select signal SEL.Time constant T2 can be considered a critical range in the present embodiment, be used for before and after the pulse leading edge of vertical synchronizing signal Vs, defining a time window (time window), as long as there is the pulse leading edge of any horizontal-drive signal Hs to drop in this time window, just OSD viewing area beat (because not having enough buffer time between the two) might take place in expression.In detail, if the time window scope that time difference T1 overtime constant T2 sets, expression level and vertical synchronizing signal interpulse has enough buffer time distances, therefore can not be subjected to the H-phase parameter adjustment and changes its relative position relation.On the other hand, if time difference T1 drops in the time window scope that time constant T2 sets, the reformed situation of Vs/Hs relative timing precedence relationship might take place apart from deficiency in the interpulse buffer time of then representing level and vertical synchronizing signal.Therefore, set to select the mode of signal SEL as described below in the present embodiment: as time difference T1 during greater than time constant T2, to select signal SEL to be made as the state of logical zero,, will select signal SEL to be made as the state of logical one as time difference T1 during less than time constant T2.And select signal SEL to be sent to the selection input of multiplexer 26, use according to its state and select corresponding clear signal.
Needing in addition what circuit 20 relatively was described further to be, is that a pulse leading edge with vertical synchronizing signal Vs is the center in the present embodiment, utilizes time constant T2, defines a time window scope in the front and back of this pulse leading edge.As long as certain pulse leading edge of horizontal-drive signal Hs dropped in the front and back T2 time of vertical sync pulse leading edge, must produce in the mode that postpones with regard to representing clear signal Clear.But, above-mentioned processing mode is not in order to limit the present invention.For instance, can in comparison circuit 20, add one and judge whether Vs pulse leading edge falls within the judgment standard in Hs pulse=1.Under Vs pulse leading edge fell within situation in the Hs pulse, if time constant T2 during less than the Hs pulse duration, then the time window scope after Vs pulse leading edge remained time constant T2, and the time window scope before it then becomes the pulse duration of Hs.That is to say,, define different critical ranges respectively in the front and back of Vs pulse leading edge.According to the above, promptly judge the mode of critical range among the present invention, situation that can be when implementing and being adjusted, but the spirit that does not still break away from the present invention.
Timer 22 is according to clock pulse signal CLK, produces two time constants that are predetermined in circuit, and one is exactly the above-mentioned time constant T2 that is sent to comparison circuit 20.Another then is T3 time of delay that is sent to pulse generator 24.In the present embodiment, time constant T2 approximates 1/4th of the horizontal-drive signal Hs cycle, time of delay, T3 approximated half of horizontal-drive signal Hs cycle, and clock pulse signal CLK can be 8MHz, 12MHz or other frequencies get final product far above the signal of horizontal-drive signal Hs, produce the fundamental frequency of above-mentioned time constant as timer 22.Time constant T2 or time of delay T3 then be sequential by horizontal/vertical synchronization signals Hs/Vs, and the maximum timing off-set amount that may cause when adjusting other parameters (as H-phase) determines.On decision time constant T2, what consider is to measure now at maximum timing off-set, in the time interval of Hs and Vs pulse leading edge much at least (this is T2), the phenomenon of two pulse leading edge back to front can not take place.On decision T3 time of delay, what consider is in Hs pulse leading edge drops on T2 time window scope the time, at least how long Vs pulse leading edge to be postponed (this is T3), can make between Vs pulse leading edge and adjacent Hs pulse leading edge maintenance certain buffer time.
As mentioned above, in the present embodiment, comparison circuit 20 and pulse generator 24 are applicable to the first reference signal CLR1 and the second reference signal CLR2 of different sequential situations respectively in order to generation.Comparison circuit produces the first reference signal CLR1 according to the pulse leading edge of vertical synchronizing signal Vs, is applicable to the situation that enough buffer time is arranged between vertical and horizontal synchronization pulse leading edge.Pulse generator 24 also produces the second reference signal CLR2 according to vertical synchronizing signal Vs, and the second reference signal CLR2 postpones a given time with respect to the first reference signal CLR1, is applicable to the situation of vertical and horizontal synchronization pulse leading edge buffer time deficiency.The first reference signal CLR1 and the second reference signal CLR2 deliver on two inputs of multiplexer 26.Though and produce the first reference signal CLR1 in the lump with comparison circuit 20 in the present embodiment, but be not in order to limiting the present invention, can also utilize during enforcement one independently pulse generator produce purpose also according to the invention.
According to above-mentioned description to selection signal SEL and reference signal CLR1, CLR2, multiplexer 26 actions among Fig. 4 can be described below: when selecting signal SEL to be logical zero, still keep enough buffer time between expression level and vertical sync pulse, therefore multiplexer 26 is selected first reference signal CLR1 output, as clear signal Clear; When selecting signal SEL to be logical one, very approaching between expression level and lock-out pulse, so multiplexer 26 selections second reference signal CLR2 output, as clear signal Clear.Therefore, no matter the sequential relationship between horizontal-drive signal Hs and the vertical synchronizing signal Vs why, can produce impregnable counter initialization signal Clear.
The operating process of Fig. 4 circuit then as shown in Figure 5.At first, the pulse leading edge of comparison circuit 20 meeting comparison level synchronizing signal Hs and vertical synchronizing signal Vs obtains time difference T1 (S1) between the two.Then, the time constant T2 that time difference T1 and timer 22 are produced compares size (S2).If T1＞T2 is when promptly the blanking time between respective pulses is greater than the time window scope, just multiplexer 26 according to " 0 " state of selecting signal SEL, selects the first reference signal CLR1 that comparison circuit 20 produced as clear signal Clear (S3).If T1＜T2, when promptly the blanking time between respective pulses is less than the time window scope, just multiplexer 26 according to the one state of selecting signal SEL, the second reference signal CLR2 that strobe pulse generator 24 is produced is as clear signal Clear (S4).
, below illustrate for the circuit part of present embodiment and the description of processing section according to Fig. 4 and Fig. 5 with three kinds of different sequential situations.Fig. 6 represents the signal sequential chart of first example in the present embodiment, wherein T1 represents among horizontal-drive signal Hs and the vertical synchronizing signal Vs edge time difference before the respective pulses, T2 then represents the signal that produced by timer, and its pulse duration is promptly represented above-mentioned time constant T2.Under situation shown in Figure 6, time difference T1＞time constant T2 promptly represents horizontal-drive signal Hs and the present sequential relationship of vertical synchronizing signal Vs, and the unlikely H-phase of being adjusted parameter influences.Therefore select first reference signal CLR1 output as clear signal Clear.Fig. 7 represents the signal sequential chart of second example in the present embodiment.Under situation shown in Figure 7, very approaching between horizontal-drive signal Hs and vertical synchronizing signal Vs respective pulses, that is T1 '＜T2, the pulse leading edge of vertical synchronizing signal Vs is the pulse leading edge of top standard's synchronizing signal Hs simultaneously.According to T1 '＜T2 relation, the comparison circuit 20 in Fig. 4 can produce logical one State Selection signal SEL, selects the second reference signal CLR2 as clear signal Clear by multiplexer 26 again.Because the clear signal Clear of this moment is away from the close zone of pulse leading edge of horizontal-drive signal Hs and vertical synchronizing signal Vs, even therefore the user has changed both corresponding relations when adjusting the H-phase parameter, but then can not be affected the situation of just having avoided the OSD viewing area to beat by article one scan line that counter begins to calculate.In situation shown in Figure 8, time difference T1 " also be less than time constant T2, but it different with Fig. 7 is the leading on the contrary vertical synchronizing signal Vs of horizontal-drive signal Hs wherein.For the situation among Fig. 8, the processing mode of present embodiment is identical with the mode of handling Fig. 7 situation, that is " condition of＜T2 is selected the second reference signal CLR2 as clear signal by multiplexer again to check out T1 by comparison circuit.Explanation is in addition, and in situation shown in Figure 8, the leading edge that the comparator in the present embodiment also can remove to detect vertical synchronizing signal Vs falls within the state in the pulse of horizontal-drive signal Hs, determines the processing method of selecting the second reference signal CLR2 by this.See through explanation that Fig. 6 to Fig. 8 did as can be known, present embodiment can solve the problem of beating in the OSD viewing area for the sequential situation of various Hs and Vs relation, therefore can reach purpose of the present invention.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining of the present invention.
Claims (10)
1. device that prevents that the OSD viewing area from beating on screen, be applicable in the display, it utilizes horizontal-drive signal and vertical synchronizing signal, in order to produce in the osd circuit clear signal in order to the counter that calculates scan line, this osd circuit determines this position, OSD viewing area according to this counter output numerical value, it is characterized in that this device comprises:
Comparison circuit, receive this horizontal-drive signal and this vertical synchronizing signal, in order to produce one first reference signal, and calculate the time difference of the pulse leading edge of this horizontal-drive signal with respect to respective pulses leading edge in this vertical synchronizing signal, produce one and select signal, when this time difference surpassed a given time window scope, this selection signal was made as first state, when this time difference fell into this given time window scope, this selection signal was made as second state;
Pulse generator produces one second reference signal, and this second reference signal is with respect to this first delayed reference signal, one given time; And
Multiplexer, select signal according to this, select one of this first reference signal and this second reference signal to be output as this clear signal, when this selection signal is first state, this first reference signal output is as this clear signal, when this selection signal was second state, this second reference signal output was as this clear signal.
2. device as claimed in claim 1 is characterized in that, this comparison circuit system produces this first reference signal corresponding to the pulse leading edge of this vertical synchronizing signal.
3. device as claimed in claim 1 is characterized in that, still comprises a timer, in order to produce a time constant, to use this given time window scope that defines.
4. device as claimed in claim 1 is characterized in that, in this comparison circuit, when the leading edge of this pulse of this vertical synchronizing signal is positioned at the respective pulses width range of this horizontal-drive signal, should select signal to be made as second state.
5. method that prevents that the OSD viewing area from beating on screen, be applicable to that in the display, it utilizes horizontal-drive signal and vertical synchronizing signal, in order to produce in the osd circuit clear signal in order to the counter that calculates scan line, it is characterized in that this method comprises the following steps:
Calculate the time difference of the pulse leading edge of this horizontal-drive signal with respect to respective pulses leading edge in this vertical synchronizing signal;
Produce one first reference signal and one second reference signal, wherein this first reference signal is with respect to the pulse leading edge of this vertical synchronizing signal, and then relative this first reference signal of this second reference signal postpones a given time; And
According to this time difference, by selecting one in this first reference signal and this second reference signal, be output as this clear signal, when this time difference surpasses a given time window scope, select this first reference signal output as this clear signal, when this time difference is dropped on this given time window scope, select this second reference signal output as this clear signal.
6. method as claimed in claim 5 is characterized in that, still comprises a step:
Utilize a timer to produce a time constant, use this given time window scope of back definition before the pulse leading edge of this vertical synchronizing signal.
7. method as claimed in claim 5 is characterized in that, comprises the following steps: in this selection step
Produce one and select signal, when this time difference surpassed this given time window scope, this selection signal was made as first state, and when this time difference fell within this given time window scope, this selection signal was made as second state; And
This first reference signal and this second reference signal are imported in the multiplexer, and should select signal to import the control selecting side of this multiplexer, when this selection signal is first state, this multiplexer is exported this first reference signal, when this selection signal was second state, this multiplexer was exported this second reference signal.
8. method as claimed in claim 5 is characterized in that, still comprises a step:
When the leading edge of this pulse of this vertical synchronizing signal was positioned at the respective pulses width range of this horizontal-drive signal, setting this selection signal was second state.
9. method as claimed in claim 8 is characterized in that, comprises the following steps: in this selection step
Produce one and select signal, when this time difference surpassed this given time window scope, this selection signal was made as first state, and when this time difference fell within this given time window scope, this selection signal was made as second state; And
This first reference signal and this second reference signal are imported in the multiplexer, and will select signal to import the control selecting side of this multiplexer, when this selection signal is first state, this multiplexer is exported this first reference signal, when this selection signal was second state, this multiplexer was exported this second reference signal.
10. device that utilizes the counter that calculates scan line to decide the OSD viewing area is characterized in that this device comprises:
One comparison circuit, calculate the pulse leading edge of a horizontal-drive signal and select signal to produce one with respect to the time difference of respective pulses leading edge in the vertical synchronizing signal, when this time difference surpasses a set T2 time value, this selection signal is made as first state, when this time difference during less than this set T2 time value, this selection signal is made as second state;
One signal generator, produce one first reference signal and one second reference signal, this first reference signal system is instant the generation according to this vertical synchronizing signal, and this second reference signal postpones the set T3 time with respect to this vertical synchronizing signal system, and this set T3 time is greater than this set T2 time; And
One multiplexer when this selection signal is first state, is selected the clear signal of this first reference signal as this counter, when this selection signal is second state, selects the clear signal of this second reference signal as this counter.
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| CNB991036352A CN1150753C (en) | 1999-03-08 | 1999-03-08 | Method and device for preventing OSD display area jumping on screen |
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| CN100448265C (en) * | 2002-08-16 | 2008-12-31 | 瑞轩科技股份有限公司 | Method and device for regulating horizontal synchronous signal and vertical synchronous signal |
| JP4769974B2 (en) | 2006-01-30 | 2011-09-07 | オンセミコンダクター・トレーディング・リミテッド | Horizontal / vertical sync signal generation circuit |
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| CN1266331A (en) | 2000-09-13 |
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