CN115073163B - Chip piezoresistor and preparation method and application thereof - Google Patents

Chip piezoresistor and preparation method and application thereof Download PDF

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Publication number
CN115073163B
CN115073163B CN202210767580.1A CN202210767580A CN115073163B CN 115073163 B CN115073163 B CN 115073163B CN 202210767580 A CN202210767580 A CN 202210767580A CN 115073163 B CN115073163 B CN 115073163B
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additive
chip
solvent
crystal phase
mixing
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CN115073163A (en
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苏财能
刘季超
肖倩
林亚梅
陈樱琳
李耀坤
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Shenzhen Zhenhua Ferrite and Ceramic Electronics Co Ltd
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Shenzhen Zhenhua Ferrite and Ceramic Electronics Co Ltd
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Priority to PCT/CN2022/105754 priority patent/WO2024000670A1/en
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Abstract

The application belongs to the technical field of resistors, and particularly relates to a chip varistor as well as a preparation method and application thereof. The method comprises the following steps: the molar ratio of Bi (1.0-2.0): (0.4-0.8): (1.0-2.0): (0.8-1.6): (0.2-0.8): (0.01-0.05): (0.02-0.08) 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 An additive for O; mixing with main crystal phase material, solvent and assistant to obtain the chip varistor. The sintering temperature is reduced, the proportion of the additive and the main crystal phase material is adjusted, and low-medium-high different potential gradient resistors can be prepared respectively, so that the method is simple and efficient.

Description

Chip piezoresistor and preparation method and application thereof
Technical Field
The application belongs to the technical field of resistors, and particularly relates to a chip varistor as well as a preparation method and application thereof.
Background
The trend of miniaturization, thinness and multifunction of modern electronic complete equipment is that the integration level of the internal circuit and the mounting density of electronic components are greatly improved, and the electronic components are used as the most basic parts in the electronic equipment, so that the miniaturization requirement is stronger. The plug-in ZnO varistor of the conventional form has a large size (minimum in the market) The application of the device is greatly limited due to the defects of small through flow and the like. With the improvement of materials and process technologies, chip piezoresistors are increasingly favored in the market due to miniaturization and excellent surge overvoltage protection capability, and the chip piezoresistors are gradually replaced by traditional plug-in pressure sensitivity in part of application fields, particularly in the fields of security protection, communication power supply, network access, LED illumination and the like, and are widely applied. The magnitude of the peak current parameter of the chip piezoresistor determines the strength of the anti-surge capability of the product, and the larger the parameter is, the stronger the anti-surge capability of the product is, and the better the protection effect is. The parameters are mainly related to ceramic materials, product sizes (structural design) and production processes, and along with the demand of miniaturization trend, the through-flow density of the ceramic materials is further improved, so that the surge protection performance of the product can be further improved, and the market demand is met.
The traditional chip piezoresistor can be roughly divided into direct current application (low voltage 5-30V, medium voltage 30-85V) and alternating current application (high voltage 110-320V) according to the difference of application fields, different types of formulas are needed to be adopted for manufacturing according to different voltage ranges in manufacturing technology, and because various types of formulas are operated on a production line, each time of milling and pulping, a jig and equipment are strictly cleaned, or a plurality of sets of equipment are needed to be prepared for classification and special use, so that cross contamination among various types of equipment is prevented, and the problems of low production efficiency, complex process, complex field management and the like are caused by the operation rules. The existing chip piezoresistor is mainly made of ZnO-Bi ceramic materials matched with Pd10/Ag90 or Pd20/Ag80 internal electrode slurry, the sintering temperature is 900 ℃ and above, the sintering temperature is too high for pure silver internal slurry, and the chip piezoresistor cannot be completely and effectively matched, for example, the internal electrode needs to be printed to reach 10 mu m or above, the problems of burning out of a leading-out end and the internal electrode, narrow sintering temperature adjustment space and the like are solved, so that the sintering temperature of a ceramic material system needs to be further reduced to below 900 ℃ if the chip piezoresistor is completely matched with pure silver internal electrode slurry.
Disclosure of Invention
The application aims to provide a chip varistor, a preparation method thereof and electronic equipment, and aims to solve the problems that the chip varistor in different voltage ranges needs to be manufactured by adopting different types of formulas, the production efficiency is low and the sintering temperature is high to a certain extent.
In order to achieve the purposes of the application, the technical scheme adopted by the application is as follows:
in a first aspect, the present application provides a method for manufacturing a chip varistor, comprising the steps of:
preparing an additive, wherein the additive comprises Bi with the molar ratio of (1.0-2.0): 0.4-0.8): 1.0-2.0): 0.8-1.6): 0.2-0.8): 0.01-0.05): 0.02-0.08 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O；
Mixing and grinding the additive, the main crystal phase material, the solvent and the auxiliary agent to obtain a ceramic material;
and manufacturing the ceramic body material into the chip piezoresistor.
In a second aspect, the present application provides a chip varistor,the ceramic material of the chip piezoresistor comprises a main crystal phase material and an additive, wherein the additive comprises Bi with the molar ratio of (1.0-2.0): 0.4-0.8): 1.0-2.0): 0.8-1.6): 0.2-0.8): 0.01-0.05): 0.02-0.08 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O。
In a third aspect, the present application provides an electronic device, where the electronic device includes a chip varistor prepared by the above method, or the chip varistor described above.
The preparation method of the chip piezoresistor provided by the first aspect of the application has the advantages of simple process, low energy consumption and low cost, and is suitable for industrial mass production and application. The ceramic material for the prepared chip piezoresistor contains an additive with a unique formula, wherein Bi 2 O 3 The high-resistance grain boundary skeleton structure is a main component of a high-resistance grain boundary skeleton structure of the varistor, and is a nonlinear foundation for the varistor. Sb (Sb) 2 O 3 The method is a main additive component for producing antimony-zinc spinel phases, and the spinel is positioned at the grain intersection of main crystal phase materials such as ZnO and the like, thereby being beneficial to promoting the growth and uniform development of the main crystal phases, improving the breakdown voltage and the tolerance square wave of the device and improving the running stability of the device under the action of large current impact and long-term electric field. If Sb is 2 O 3 Too much addition will increase leakage current and reduce the through-current capacity and surge overvoltage absorbing capacity of the product. Cr (Cr) 2 O 3 With Sb 2 O 3 Also participate in spinel formation, can produce a reaction with Sb 2 O 3 Similar channels are helpful for improving the stability of the device, and if doped, the potential gradient of the point is increased, the leakage current is increased, and the voltage ratio is deteriorated. MnO (MnO) 2 、Co 2 O 3 The components play a very important role in improving the nonlinearity of the chip piezoresistor and reducing the leakage current, and are the same asIt is also advantageous to increase the resistance and stability to square wave, lightning current and large current surge, but if excessively doped, the voltage ratio of the resistor sheet will increase. H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 The melting point of the components such as O is lower, and the eutectic compound formed by the components has remarkable melting-assisting effect, can promote the growth of crystal grains and reduce the sintering temperature. At the same time, the formed glass oxide is easy to be combined with Bi during the firing process 2 O 3 、Sb 2 O 3 And interstitial Zn ions to produce compact glass phase, so that the concentration of crystal boundary defects is reduced, and the long-term stability of the resistor sheet in an electric field environment is improved. Nb (Nb) 2 O 5 Can segregate at the grain boundary to form Zn with the main crystal phase material 3 Nb 2 O 8 The spinel phase can play a role in preventing grain growth, and meanwhile, the spinel phase also increases the surface state density of the grain boundary, so that the height of a grain boundary barrier can be increased, and the nonlinearity of a product is improved. However, when the amount of the additive is too large, grain boundary defects increase due to the inhibition of grain growth, and further leakage current increases and the nonlinear coefficient decreases. AgNO 3 Monovalent silver ions can reduce and clamp the fermi level, belong to grain boundary stabilizers, can inhibit migration of interstitial ions, inhibit diffusion of oxygen atoms, slow down deterioration of piezoresistors, and prolong the service life of devices. However, if the amount of the additive is too large, the leakage current will increase, the voltage-sensitive voltage will decrease, and the comprehensive performance will be deteriorated. Al (NO) 3 ) 3 ·9H 2 O is due to Al 3+ The (53.5 pm) ion radius is small, and the crystal particles easily enter the crystal lattice, so that the concentration of the carrier of the crystal particles of the main crystal phase is improved, the resistance of the crystal particles is reduced, the V-I characteristic curve of the piezoresistor is deviated to a large current area, the voltage limiting ratio is reduced, and the tolerance of lightning current and large current impact is improved. However, excessive doping will cause an increase in leakage current and an increase in voltage-sensitive voltage.
The chip varistor provided by the second aspect of the application plays roles in forming excellent nonlinear structure of the varistor, improving the capability of resisting impact current, improving long-term operation stability and the like through the synergistic effect of the main crystal phase material and the additive with a special formulaDecisive function. In addition, bi in the additive 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 The low-melting-point components such as O and the like can form a low-melting-point co-melt substance, thereby playing a role in assisting melting, being beneficial to reducing the sintering temperature to be lower than 900 ℃, and ensuring that the piezoresistor still has good electrical property and long-term use stability at the lower sintering temperature. Under the condition of reducing sintering temperature, the application requirements of low-voltage, medium-voltage and high-voltage potential gradient piezoresistors can be met by adjusting the doping amount of each component of the additive in the ceramic material or the proportion of the additive to the main crystal phase material, and the application is flexible and the adaptability is wide.
The electronic equipment provided by the third aspect of the application comprises the chip piezoresistor, and the chip piezoresistor has the characteristics of nonlinearity, high through-flow, adjustable voltage gradient, low-temperature sintering and the like through the synergistic effect of the main crystal phase material and the additive with a special formula, so that the stability of the electronic equipment is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of a method for manufacturing a chip varistor according to an embodiment of the present application;
FIG. 2 is an SEM image of a chip varistor according to embodiment 1 of the present application;
FIG. 3 is an SEM image of a chip varistor according to example 2 of the present application;
fig. 4 is an SEM image of a chip varistor according to embodiment 3 of the present application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
In the present application, the term "and/or" describes an association relationship of an association object, which means that three relationships may exist, for example, a and/or B may mean: a alone, a and B together, and B alone. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, "at least one (individual) of a, b, or c," or "at least one (individual) of a, b, and c" may each represent: a, b, c, a-b (i.e., a and b), a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple, respectively.
It should be understood that, in various embodiments of the present application, the sequence number of each process described above does not mean that the execution sequence of some or all of the steps may be executed in parallel or executed sequentially, and the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The weights of the relevant components mentioned in the description of the embodiments of the present application may refer not only to the specific contents of the components, but also to the proportional relationship between the weights of the components, so long as the contents of the relevant components in the description of the embodiments of the present application are scaled up or down within the scope of the disclosure of the embodiments of the present application. Specifically, the mass in the specification of the embodiment of the application can be a mass unit which is known in the chemical industry field such as mu g, mg, g, kg.
The terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated for distinguishing between objects such as substances from each other. For example, a first XX may also be referred to as a second XX, and similarly, a second XX may also be referred to as a first XX, without departing from the scope of embodiments of the application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.
The first aspect of the embodiment of the application provides a method for preparing a chip varistor, which comprises the following steps:
s10, preparing an additive, wherein the additive comprises Bi with the molar ratio of (1.0-2.0): 0.4-0.8): 1.0-2.0): 0.8-1.6): 0.2-0.8): 0.01-0.05): 0.02-0.08 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O；
S20, mixing and grinding the additive, the main crystal phase material, the solvent and the auxiliary agent to obtain a ceramic material;
s30, manufacturing the ceramic body material into the chip piezoresistor.
The preparation method of the chip piezoresistor provided by the first aspect of the embodiment of the application comprises the following steps of (1.0-2.0): 0.4-0.8): 1.0-2.0): 0.8-1.6): 0.2-0.8): 0.01-0.05): 0.02-0.08 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 And after the additive of O, mixing and grinding the additive, a main crystal phase material, a solvent and an auxiliary agent to prepare a ceramic material, and then preparing the ceramic material into the chip piezoresistor. The preparation method of the chip piezoresistor is simple in preparation process, low in energy consumption and low in cost, and is suitable for industrial mass production and application. The ceramic material for the prepared chip piezoresistor contains an additive with a unique formula, wherein Bi 2 O 3 The high-resistance grain boundary skeleton structure is a main component of a high-resistance grain boundary skeleton structure of the varistor, and is a nonlinear foundation for the varistor. Sb (Sb) 2 O 3 The method is a main additive component for producing antimony-zinc spinel phases, and the spinel is positioned at the grain intersection of main crystal phase materials such as ZnO and the like, thereby being beneficial to promoting the growth and uniform development of the main crystal phases, improving the breakdown voltage and the tolerance square wave of the device and improving the running stability of the device under the action of large current impact and long-term electric field. If Sb is 2 O 3 Too much addition will increase leakage current and reduce the through-current capacity and surge overvoltage absorbing capacity of the product. Cr (Cr) 2 O 3 With Sb 2 O 3 Also participate in spinel formation, can produce a reaction with Sb 2 O 3 Similar channels are beneficial to improving the stability of the device, and if too much doping is performed, the potential gradient is increased, the leakage current is increased, and the voltage ratio is deteriorated. MnO (MnO) 2 、Co 2 O 3 The components play a very important role in improving the nonlinearity of the chip piezoresistor and reducing leakage current, and are also beneficial to improving the tolerance and stability of the chip piezoresistor to the square wave, lightning current and large current impact, but if the chip piezoresistor is excessively doped, the voltage ratio of the chip piezoresistor is increased. H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 The melting point of the components such as O is lower, and the eutectic compound formed by the components has remarkable melting-assisting effect, can promote the growth of crystal grains and reduce the sintering temperature. At the same time, the formed glass oxide is easy to be combined with Bi during the firing process 2 O 3 、Sb 2 O 3 And interstitial Zn ions to produce compact glass phase, so as to reduce the concentration of crystal boundary defects and improve the long-term stability of the resistor sheet in an electric field environmentSex. Nb (Nb) 2 O 5 Can segregate at the grain boundary to form Zn with the main crystal phase material 3 Nb 2 O 8 The spinel phase can play a role in preventing grain growth, and meanwhile, the spinel phase also increases the surface state density of the grain boundary, so that the height of a grain boundary barrier can be increased, and the nonlinearity of a product is improved. However, when the amount of the additive is too large, grain boundary defects increase due to the inhibition of grain growth, and further leakage current increases and the nonlinear coefficient decreases. AgNO 3 Monovalent silver ions can reduce and clamp the fermi level, belong to grain boundary stabilizers, can inhibit migration of interstitial ions, inhibit diffusion of oxygen atoms, slow down deterioration of piezoresistors, and prolong the service life of devices. However, if the amount of the additive is too large, the leakage current will increase, the voltage-sensitive voltage will decrease, and the comprehensive performance will be deteriorated. Al (NO) 3 ) 3 ·9H 2 O is due to Al 3+ The (53.5 pm) ion radius is small, and the crystal particles easily enter the crystal lattice, so that the concentration of the carrier of the crystal particles of the main crystal phase is improved, the resistance of the crystal particles is reduced, the V-I characteristic curve of the piezoresistor is deviated to a large current area, the voltage limiting ratio is reduced, and the tolerance of lightning current and large current impact is improved. However, excessive doping will cause an increase in leakage current and an increase in voltage-sensitive voltage. The chip varistor prepared by the embodiment of the application plays a decisive role in forming an excellent nonlinear structure of the varistor, improving the capability of resisting impact current, improving long-term operation stability and the like through the synergistic effect of the main crystal phase material in the ceramic material and the additive with a special formula. On the other hand, the low-melting-point component in the additive can form a low eutectic substance, plays a role in assisting melting, is favorable for reducing the sintering temperature to be lower than 900 ℃, and ensures that the piezoresistor still has good electrical performance and long-term use stability at the lower sintering temperature. On the other hand, under the condition of reducing sintering temperature, the low-voltage, medium-voltage and high-voltage potential gradient application requirements can be respectively met by adjusting the doping amount of each component of the additive in the ceramic body material or the proportion of the additive to the main crystal phase material, and meanwhile, the manufacture of ceramic body materials and chip piezoresistors of different low-voltage, medium-voltage and high-voltage potential gradients is realized, thereby solving the conventional requirement of devices aiming at different potential gradientsThe problem of preparing ceramic materials with different formulas respectively greatly simplifies the production process and improves the production efficiency.
In some embodiments, in step S10, the step of preparing the additive includes: weighing Bi with the molar ratio of (1.0-2.0): (0.4-0.8): (1.0-2.0): (0.8-1.6): (0.2-0.8): (0.01-0.05): (0.02-0.08) 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 And (3) after O, placing the additive powder and water, preferably deionized water, accounting for 80-120% of the total mass of the powder on a planetary ball mill for mixing and grinding, discharging to a special tray after the particle size reaches the preset requirement, and drying to obtain the additive.
In some embodiments, the additive has a particle size D50 of no greater than 0.8 μm and a particle size D95 of no greater than 2 μm; the additive with the granularity is beneficial to the manufacturing process of the chip piezoresistor and ensures the nonlinear structure, low temperature, low voltage and other characteristics of the prepared chip piezoresistor. If the particle size is too small, although the subsequent sintering treatment process is facilitated, the too small particle size can make the potential gradient of the manufactured piezoresistor be too high, which is unfavorable for manufacturing the low-temperature low-voltage series chip piezoresistor. If the particle size is too large, sintering is not facilitated, and the method is not suitable for the existing casting process, and the preparation efficiency of the chip piezoresistor is affected. In some embodiments, the additive has a particle size D50 of no greater than 0.7 μm and a particle size D95 of no greater than 1.5 μm.
In some embodiments, in the step S20, the main crystal phase material is selected from zinc oxide, so as to manufacture the ZnO varistor. The main crystal phase material is composed of divalent element (Zn) and hexavalent element oxygen (O), and the zinc oxide piezoresistor is a 'II-VI oxide semiconductor' from the material perspective. Through the synergistic effect of the main crystal phase material and the additive with a specific formula, the prepared chip varistor has the characteristics of large current capacity, low limiting voltage, high response speed, no follow current, symmetrical volt-ampere characteristics (namely, the product is nonpolar), low voltage temperature coefficient and the like.
In some embodiments, the primary crystalline phase material has a particle size D50 of no greater than 0.8 μm and a particle size D95 of no greater than 2 μm. If the particle size is too small, although the subsequent sintering treatment process is facilitated, the too small particle size can make the potential gradient of the manufactured piezoresistor be too high, which is unfavorable for manufacturing the low-temperature low-voltage series chip piezoresistor. If the particle size is too large, sintering is not facilitated, and the method is not suitable for the existing casting process, and the preparation efficiency of the chip piezoresistor is affected.
According to the application, through the embodiment research, the lower the content of the main crystal phase material is, the higher the content of the additive is, and the higher the potential gradient of the ceramic body material is.
In some embodiments, the step of the hybrid milling process includes: the mass ratio is (90-94): mixing and grinding the additive and the main crystal phase material in the steps of (6-10), and then mixing and grinding the mixture with a solvent and an auxiliary agent to obtain a ceramic material with the potential of 300-500V/mm, thus obtaining the ceramic material with low potential gradient.
In other embodiments, the step of the hybrid milling process includes: the mass ratio is (86-90): mixing and grinding the additive and the main crystal phase material in the (10-14), and then mixing and grinding the mixture with a solvent and an auxiliary agent to obtain a porcelain body material with the potential of 500-1000V/mm, thus obtaining the porcelain body material with the medium potential gradient.
In other embodiments, the step of the hybrid milling process includes: the mass ratio is (81-86): mixing and grinding the additive and the main crystal phase material in the steps of (14-19), and then mixing and grinding the mixture with a solvent and an auxiliary agent to obtain a ceramic material with the potential of 1000V/mm-2000V/mm, thus obtaining the ceramic material with high potential gradient.
According to the embodiment of the application, the mixture ratio of the additive and the main crystal phase material in the ceramic body material is regulated, so that the ceramic body material with low potential gradient, the ceramic body material with medium potential gradient and the ceramic body material with high potential gradient can be prepared respectively, the application requirements of low-voltage, medium-voltage and high-voltage potential gradients are met respectively, meanwhile, the manufacture of different ceramic body materials with low-voltage, medium-voltage and high-voltage and chip piezoresistors is realized, the problem that ceramic body materials with different formulas are required to be prepared respectively for different potential gradient devices in the conventional way is solved, the production process is greatly simplified, and the generation efficiency is improved.
In some embodiments, the auxiliary agent includes a dispersant, an adhesive, and a thickener, and the auxiliary agent adjusts the material property of the porcelain body material to improve the stability of the manufactured chip varistor.
In some embodiments, the dispersing agent is selected from acrylic esters, and the dispersing agent has a plurality of active groups, is combined with components in main crystal phase materials such as zinc oxide and the like and additives, so that the components are uniformly and stably dispersed in the solution, and the dispersion stability and uniformity of the porcelain body materials are improved. In some embodiments, the acrylic dispersants include disperbyk-182, disperbyk-184, DOPA-22 from Kyowa chemical company.
In some embodiments, the binder is selected from polymethyl methacrylate, PMMA, systems; the system has higher material viscosity, and is favorable for the combination stability of all raw material components in the high porcelain body material. In some embodiments, the binder of the polymethyl methacrylate system includes Rogowski A-21, B-44.
In some embodiments, the thickener is selected from at least one of dioctyl phthalate DOP, dibutyl phthalate DBP, dioctyl adipate DOA; the thickener can improve the viscosity of the system, so that the system can maintain a uniform and stable suspension state or an emulsion state, or form gel, thereby being beneficial to the subsequent preparation of ceramic materials into green bodies and improving the preparation efficiency of the chip piezoresistor.
In some embodiments, the solvent comprises toluene or a mixture of propyl acetate and an alcoholic solvent. Through the compound use of toluene or propyl acetate and alcohol solvents, the dissolution and dispersion stability of additives, main crystal phase materials and auxiliary agents in the solvents are improved, and the stability of ceramic materials is improved. In some embodiments, the solvent is selected from a mixed solvent of toluene and absolute ethanol or a mixed solvent of propyl acetate and isobutanol.
In some embodiments, the ceramic material comprises 1-2% by mass of dispersant, 7-12% by mass of binder, 2-5% by mass of thickener, and 50-80% by mass of solvent. In the porcelain body material of the embodiment of the application, the addition amount of the solvent component is 50-80% of the weight of the powder, and the viscosity of the prepared slurry is ensured to be in a proper range for normal casting, so that the addition amount is influenced by the type and molecular weight of the selected adhesive. The consumption of the dispersant component is 1-2% of the weight of the powder; aims to improve the dispersion effect of the powder. The consumption of the adhesive component is 7-10% of the powder type, and the adhesive component is matched with the consumption of the solvent according to the molecular weight and the type of the adhesive, so that the proper viscosity of the slurry is ensured for normal casting. The plasticizer is used in an amount of 2-5%, so that the acting force among the molecules of the adhesive is reduced, the plasticity is increased, and the subsequent process is facilitated. The addition amount of the auxiliary agents and the solvent in the porcelain body material is more in order to ensure the machinability of the product manufactured in the previous working procedure, and if the addition amount is not proper, such as the viscosity is not proper, the casting effect is poor, and the post-manufacturing of the product is affected; if the dispersing agent is selected and added improperly, the dispersing effect of the powder is affected, and the consistency of the performance of the later-stage product is affected. If the adhesive and the plasticizer are used in an improper amount, the product cut in the later stage can generate poor appearance such as sticky sheets, burrs and the like.
In some embodiments, the step of subjecting the additive to a mixed milling process with the primary crystalline phase material, the solvent, and the adjunct comprises: mixing the additive with the main crystal phase material, adding a solvent and a dispersing agent, performing planetary ball milling for 6-12 hours under the condition of the ball milling frequency of 25-30 HZ, adding an adhesive and a thickening agent, and performing planetary ball milling for 6-12 hours under the condition of the ball milling frequency of 25-30 HZ to obtain the ceramic material. Fully ensures that each component in the porcelain body material is uniformly ground and stably dispersed, and is favorable for the subsequent manufacture of the chip piezoresistor.
In some embodiments, in the step S30, the step of manufacturing the ceramic body material into the chip piezoresistor includes: after the ceramic body material is made into a green film according to a preset structure, an inner electrode is printed, and a lamination process, a warm water pressing process, a cutting process, a glue discharging process, a sintering process, an end electrode process and an electroplating process are sequentially carried out, so that the chip piezoresistor is manufactured.
In some embodiments, the temperature of the sintering process is no less than 850 ℃ and no greater than 900 ℃. Bi in the additive of the porcelain body material of the embodiment of the application 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 The low-melting-point components such as O and the like can form a low-melting-point blend, thereby playing a role in assisting melting, being beneficial to reducing the sintering temperature of ceramic materials, leading the sintering temperature to be lower than 900 ℃, and ensuring that the piezoresistor still has good electrical property and long-term use stability at a lower sintering temperature.
In some embodiments, the silver paste used in the terminal electrode process has a silver content of 60-70% and a silver firing temperature of 600-800 ℃. In some embodiments, the inner plasma is pure silver paste, preferably the pure silver paste has a silver content of 85% -92% and a printing thickness of 5-10 μm; the sintering temperature is between 850 and 900 ℃.
A second aspect of the embodiment of the application provides a chip varistor, the ceramic material of the chip varistor comprising a primary crystalline phase material and an additive comprising Bi in a molar ratio of (1.0-2.0): (0.4-0.8): (1.0-2.0): (0.8-1.6): (0.2-0.8): (0.01-0.05): (0.02-0.08) 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O。
The chip piezoresistor provided by the second aspect of the embodiment of the application comprises a main crystal phase material and an additive, wherein the additive comprises Bi with the molar ratio of (1.0-2.0): (0.4-0.8): (1.0-2.0): (0.8-1.6): (0.2-0.8): (0.01-0.05): (0.02-0.08) 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O. The synergistic effect of the main crystal phase material and the additive with a special formula plays a decisive role in the formation of excellent nonlinear structures of piezoresistors, the improvement of the capability of resisting impact current, the improvement of long-term operation stability and the like. In addition, bi in the additive 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 The low-melting-point components such as O and the like can form a low-melting-point co-melt substance, thereby playing a role in assisting melting, being beneficial to reducing the sintering temperature to be lower than 900 ℃, and ensuring that the piezoresistor still has good electrical property and long-term use stability at the lower sintering temperature. Under the condition of reducing sintering temperature, the application requirements of low-voltage, medium-voltage and high-voltage potential gradient piezoresistors can be met by adjusting the doping amount of each component of the additive in the ceramic material or the proportion of the additive to the main crystal phase material, and the application is flexible and the adaptability is wide.
The chip piezoresistor of the embodiment of the application can be manufactured by the method of the embodiment.
In some embodiments, the primary crystalline phase material is selected from zinc oxide.
In some embodiments, the primary crystalline phase material has a particle size D50 of no greater than 0.8 μm and a particle size D95 of no greater than 2 μm.
In some embodiments, the particle size D50 of the additive is not greater than 0.8 μm and the particle size D95 is not greater than 2 μm.
In some embodiments, the mass ratio of the primary crystalline phase material to the additive is (81-94): (6-19).
In some embodiments, the mass ratio of the primary crystalline phase material to the additive is (90-94): (6-10) the voltage of the chip varistor is 300V/mm-500V/mm.
In some embodiments, the mass ratio of the primary crystalline phase material to the additive is (86-90): (10-14) the voltage of the chip varistor is 500V/mm-1000V/mm.
In some embodiments, the mass ratio of the primary crystalline phase material to the additive is (81-86): in the case of (14-19), the voltage potential of the chip varistor is 1000V/mm-2000V/mm.
The technical effects of the above embodiments of the present application are all discussed in the foregoing, and are not described herein.
In some embodiments, the primary crystalline phase material is zinc oxide, the mass ratio of zinc oxide to additives being 92:8, the through-flow density of the chip piezoresistor can reach 59A/mm 2 . Since the impulse current applied is short, when a large current is applied to the ZnO piezoresistor, the impulse capability is absorbed by the piezoresistors of different small units in a short time, the generated heat raises the temperature of the product, and the generated heat cannot be effectively and rapidly diffused to other places of the piezoresistor in such a short time, so that the piezoresistors of different small units can be rapidly raised in temperature in a short time, and the temperature gradient between the two different units can generate thermal stress on the grain boundary between the two different units. If the thermal stress between the different parts inside the resistor exceeds a critical value, burst damage occurs and failure occurs. And factors influencing the temperature diffusion degree and the temperature gradient difference degree between two adjacent small units are several, such as uniformity on microstructure, ceramic material heat conductivity coefficient, specific heat constant, specific gravity and the like. From the microstructure point of view, the microstructure of the piezoresistor is composed of zinc oxide crystal grains, a crystal boundary layer and spinel three phases. Since the electrical resistance of zinc oxide crystal grains is (1-10) Ω cm and the electrical resistivity of the grain boundary layer is (1012-1013) Ω cm, the voltage applied to the varistor is basically in the grain boundary layer, and the heat release characteristic of the grain boundary layer depends on the heat capacity, heat conductivity and other heat release characteristics of the zinc oxide crystal grains in contact with the crystal boundary layer, so that the current capacity of the high-energy varistor is approximately determined by the heat capacity of the zinc oxide crystal grains. It is apparent that the larger the ZnO grains in the chip varistor, i.e. the more ZnO content, the larger the current capacity of the high-energy varistor. By reducing the content of the additive, the thinner the grain boundary layer is, which contributes to the growth of zinc oxide crystal grains, and at the same time, the thermal conductivity and the thermal capacity of the zinc oxide crystal grains are higher than those of the grain boundary layer material, so that the reduction of the content of the additive in a certain range contributes to the improvement of the yieldThe flow capacity of the product.
A third aspect of the embodiment of the present application provides an electronic device, where the electronic device includes a chip varistor prepared by the above method, or the chip varistor described above.
The electronic equipment provided by the third aspect of the embodiment of the application comprises the chip piezoresistor, and the chip piezoresistor has the characteristics of nonlinearity, high through-flow, adjustable voltage gradient, low-temperature sintering and the like through the synergistic effect of the main crystal phase material and the additive with a special formula, so that the stability of the electronic equipment is improved.
In order that the details and operation of the present application may be clearly understood by those skilled in the art, and that the improved performance of the chip piezoresistors and methods of making the same according to the embodiments of the present application may be significantly realized, the above-described embodiments are exemplified by the following examples.
Example 1
A chip varistor, the preparation comprising the steps of:
1) The additive is prepared from the following chemical components in percentage by mole: bi (Bi) 2 O 3 ：Sb 2 O 3 ：MnO 2 ：Cr 2 O 3 ：Co 2 O 3 ：H 3 BO 3 ：Zn 3 (PO 4 ) 2 ·4H 2 O：Nb 2 O 5 ：AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O=1.2: 1.0:0.5:0.5:1.0:1.2:1.0:0.1:0.02:0.03, adding ionized water accounting for 90 percent of the total mass of the additive powder, putting the mixture on a planetary ball mill for mixing and grinding for 16 hours, discharging the mixture to a special tray when the particle size reaches the requirement that the preset D50 is less than or equal to 0.8 mu m and the D95 is less than or equal to 2 mu m, and drying the mixture in an oven at the temperature of 150+/-10 ℃ to obtain the additive for later-stage batching.
2) According to the material proportion of 92 weight percent ZnO+8 weight percent additive, weighing the additive with corresponding mass, crushing, mixing the crushed additive with zinc oxide powder with corresponding mass, adding solvent with corresponding mass (propyl acetate with 50 percent of total powder mass and isobutanol with 15 percent of total powder mass), adding acrylic dispersing agent (1.5 percent of total powder mass), and performing ball milling and mixing on a planetary ball mill according to the conditions of 30HZ and 8H.
3) After ball milling and mixing are completed, a polymethyl methacrylate system adhesive with the total powder mass of 12% and a dioctyl phthalate thickener with the total powder mass of 5% are continuously added into the slurry, and mixed and dispersed on a planetary ball mill again according to the conditions of 30HZ and 8H to obtain the porcelain body material.
4) And (3) casting the ceramic material on a PET film to form a green film with the thickness of 40 mu m after discharging, sequentially finishing lamination, wen Shuiya, cutting, glue discharging, sintering, terminal electrode and electroplating working procedures according to 4532 size, dielectric layer thickness of 0.14mm and structural design of 6 internal electrodes, and finally obtaining the chip varistor corresponding to the requirement. Wherein, the inner electrode is printed by pure silver paste with the silver content of 90 percent, and the printing thickness is 7-9 mu m. The sintering maximum temperature is 870 ℃, and the heat preservation is carried out for 2 hours; the silver paste of the terminal electrode is manufactured by adopting the terminal paste with the silver content of 65 percent, and the silver is burned at the highest temperature of 750 ℃ to finish the manufacturing of the conducting terminal, thus obtaining the chip piezoresistor.
Example 2
A chip varistor, the preparation comprising the steps of:
1) The additive was prepared and composed in the same manner as in example 1 and was taken directly.
2) According to the material proportion of 88% ZnO+12% additive, the additive with corresponding mass is weighed and crushed, the crushed additive and zinc oxide powder with corresponding mass are mixed, meanwhile, solvent with corresponding mass (propyl acetate with 50% of total powder mass and isobutanol with 15% of total powder mass) is added, acrylic dispersing agent (1.5% of total powder mass) is added, and ball milling and mixing are carried out on a planetary ball mill according to the conditions of 30HZ and 8H.
3) After ball milling and mixing are completed, a polymethyl methacrylate system adhesive with the total powder mass of 12% and a dioctyl phthalate thickener with the total powder mass of 5% are continuously added into the slurry, and mixed and dispersed on a planetary ball mill again according to the conditions of 30HZ and 8H to obtain the porcelain body material.
4) And (3) casting the ceramic material on a PET film to form a green film with the thickness of 40 mu m after discharging, sequentially finishing lamination, wen Shuiya, cutting, glue discharging, sintering, terminal electrode and electroplating working procedures according to 4532 size, dielectric layer thickness of 0.14mm and structural design of 6 internal electrodes, and finally obtaining the chip varistor corresponding to the requirement. Wherein, the inner electrode is printed by pure silver paste with the silver content of 90 percent, and the printing thickness is 7-9 mu m. The sintering maximum temperature is 870 ℃, and the heat preservation is carried out for 2 hours; the silver paste of the terminal electrode is manufactured by adopting the terminal paste with the silver content of 65 percent, and the silver is burned at the highest temperature of 750 ℃ to finish the manufacturing of the conducting terminal, thus obtaining the chip piezoresistor.
Example 3
A chip varistor, the preparation comprising the steps of:
1) The additive was prepared and composed in the same manner as in example 1 and was taken directly.
2) According to the material proportion of 84% ZnO+16% additive, weighing the additive with corresponding mass, crushing, mixing the crushed additive with zinc oxide powder with corresponding mass, adding solvent with corresponding mass (propyl acetate with 50% of total powder mass and isobutanol with 15% of total powder mass), adding acrylic dispersing agent (1.5% of total powder mass), and ball milling and mixing on a planetary ball mill according to 30HZ,8H conditions.
3) After ball milling and mixing are completed, a polymethyl methacrylate system adhesive with the total powder mass of 12% and a dioctyl phthalate thickener with the total powder mass of 5% are continuously added into the slurry, and mixed and dispersed on a planetary ball mill again according to the conditions of 30HZ and 8H to obtain the porcelain body material.
4) And (3) casting the ceramic material on a PET film to form a green film with the thickness of 40 mu m after discharging, sequentially finishing lamination, wen Shuiya, cutting, glue discharging, sintering, terminal electrode and electroplating working procedures according to 4532 size, dielectric layer thickness of 0.14mm and structural design of 6 internal electrodes, and finally obtaining the chip varistor corresponding to the requirement. Wherein, the inner electrode is printed by pure silver paste with the silver content of 90 percent, and the printing thickness is 7-9 mu m. The sintering maximum temperature is 870 ℃, and the heat preservation is carried out for 2 hours; the silver paste of the terminal electrode is manufactured by adopting the terminal paste with the silver content of 65 percent, and the silver is burned at the highest temperature of 750 ℃ to finish the manufacturing of the conducting terminal, thus obtaining the chip piezoresistor.
Example 4
A chip varistor differing from embodiment 1 in that: bi in step 1 2 O 3 ：Sb 2 O 3 ：MnO 2 ：Cr 2 O 3 ：Co 2 O 3 ：H 3 BO 3 ：Zn 3 (PO 4 ) 2 ·4H 2 O：Nb 2 O 5 ：AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O＝1.5：0.9：0.5：0.5：1.0：1.6：1.5：0.1：0.02：0.03。
Further, in order to verify the advancement of the embodiment of the present application, the electrochemical properties such as the voltage-sensitive voltage, the leakage current, the nonlinear coefficient, the peak current, the potential gradient, the circulation density, and the morphology of the chip piezoresistor prepared in the embodiment are respectively tested as follows:
1. the testing method of the voltage-sensitive voltage comprises the following steps: nominal value V of voltage-sensitive voltage 1mA The parameter is one parameter of the pre-breakdown region and the turning point of the breakdown region in the volt-ampere curve of the zinc oxide piezoresistor, and is generally the voltage value at two ends of the product when 1mA direct current passes through.
2. The test method of leakage current comprises the following steps: 75% voltage-sensitive voltage V 1mA Current value through the product.
3. The method for testing the nonlinear coefficient comprises the following steps: the nonlinear coefficient α is expressed as α=1/(logV) 1mA /V 0.1mA ) And (5) calculating to obtain the product.
4. The peak current testing method comprises the following steps: the product can bear 8/20 mu S pulse current peak value for a prescribed number of times;
5. the potential gradient voltage testing method comprises the following steps: calculated from the division of the voltage-dependent voltage value by the thickness of the dielectric layer
6. The method for testing the through-flow density comprises the following steps: reference to national standard GJB 1782A-2015
The results of the above test are shown in table 1 below:
TABLE 1
As shown by the test results, the chip piezoresistor prepared by the embodiment of the application has higher circulation density, low voltage-sensitive voltage, low leakage current and higher nonlinear coefficient, and the potential gradient can be flexibly regulated and controlled by the proportion of the zinc oxide main crystal phase material and the additive. The low-potential chip piezoresistor, the medium-potential chip piezoresistor and the high-potential chip piezoresistor can be prepared respectively by adjusting the proportion of the zinc oxide main crystal phase material and the additive. Leakage current is very small in low-voltage, medium-voltage and high-voltage ranges, so that the product has low power consumption, the application performance of the device is improved, the application flexibility of the chip piezoresistor is improved, and the preparation process is simplified. In addition, the nonlinear coefficient is higher, which indicates that the pressure-sensitive characteristic of the product is obvious; the peak current indicates that the surge protection capability of the product is strong.
7. The morphology of the chip piezoresistor prepared in the embodiment is observed through a scanning electron microscope, and the test results are shown in fig. 2-4, wherein fig. 2 is an SEM micro morphology diagram of the chip piezoresistor of embodiment 1, fig. 3 is an SEM micro morphology diagram of the chip piezoresistor of embodiment 2, and fig. 4 is an SEM micro morphology diagram of the chip piezoresistor of embodiment 3. As can be seen from the morphology graph, particles in the chip piezoresistor prepared by the embodiment of the application are uniformly distributed, the surface is smooth, and the stability of the chip piezoresistor is improved.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.

Claims (10)

1. The preparation method of the chip piezoresistor is characterized by comprising the following steps of:
the additive is prepared by the following components in mole ratio of (1.0-2.0): (0.4-0.8): (1.0-2.0): (0.8-1.6): (0.2-0.8): (0.01-0.05): (0.02-0.08) 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O is formed; the H is 3 BO 3 And the Zn 3 (PO 4 ) 2 ·4H 2 O forms a eutectic compound;
mixing and grinding the additive, the main crystal phase material, the solvent and the auxiliary agent to obtain a ceramic material; the main crystal phase material is selected from zinc oxide; the low-potential-gradient ceramic body material, the medium-potential-gradient ceramic body material and the high-potential-gradient ceramic body material can be prepared respectively by adjusting the proportion of the additive to the main crystal phase material in the ceramic body material;
manufacturing the ceramic body material into a chip piezoresistor; the sintering temperature of the chip piezoresistor is lower than 900 ℃.
2. The method of manufacturing a chip varistor according to claim 1, wherein the primary crystalline material has a particle size D50 of not more than 0.8 μm and a particle size D95 of not more than 2 μm;
and/or the particle diameter D50 of the additive is not higher than 0.8 mu m, and the particle diameter D95 is not higher than 2 mu m.
3. The method of manufacturing a chip varistor according to claim 1 or 2, wherein the step of mixing and grinding includes:
the mass ratio is (90-94): mixing and grinding the additive and the main crystal phase material, and then mixing and grinding the mixture with the solvent and the auxiliary agent to obtain a ceramic material with the potential of 300V/mm-500V/mm;
or alternatively, the process may be performed,
the mass ratio is (86-90): mixing and grinding the additive and the main crystal phase material of (10-14), and then mixing and grinding the mixture with the solvent and the auxiliary agent to obtain a porcelain body material with the potential of 500V/mm-1000V/mm;
or alternatively, the process may be performed,
the mass ratio is (81-86): mixing and grinding the additive and the main crystal phase material, and then mixing and grinding the mixture with the solvent and the auxiliary agent to obtain the ceramic material with the potential of 1000V/mm-2000V/mm.
4. A method of making a chip varistor as in claim 3, wherein said auxiliary agents include dispersants, binders and thickeners;
and/or the solvent comprises a mixed solvent of toluene and an alcohol solvent or a mixed solvent of propyl acetate and an alcohol solvent.
5. The method for manufacturing a chip varistor according to claim 4, wherein the ceramic material contains 1-2% by mass of the dispersant, 7-12% by mass of the binder, 2-5% by mass of the thickener, and 50-80% by mass of the solvent;
and/or the dispersant is selected from the group consisting of acrylate species;
and/or the binder is selected from polymethyl methacrylate systems;
and/or the thickener is at least one selected from dioctyl phthalate, dibutyl phthalate and dioctyl adipate;
and/or the solvent is selected from a mixed solvent of toluene and absolute ethyl alcohol or a mixed solvent of propyl acetate and isobutanol.
6. The method of manufacturing a chip varistor according to any one of claims 4 or 5, wherein the step of mixing and grinding includes:
and after mixing the additive with the main crystal phase material, adding the solvent and the dispersing agent, performing planetary ball milling for 6-12 hours under the condition of the ball milling frequency of 25-30 HZ, adding the adhesive and the thickening agent, and performing planetary ball milling for 6-12 hours under the condition of the ball milling frequency of 25-30 HZ to obtain the ceramic material.
7. The method of manufacturing a chip varistor as claimed in claim 6, wherein the step of forming the ceramic body material into a chip varistor comprises: and (3) preparing the ceramic body material into a green film according to a preset structure, printing an inner electrode, and sequentially performing a lamination process, a warm water pressing process, a cutting process, a glue discharging process, a sintering process, an end electrode process and an electroplating process to obtain the chip varistor.
8. The method of manufacturing a chip varistor according to claim 7, wherein the sintering process is performed at a temperature not lower than 850 ℃ and not higher than 900 ℃;
and/or the silver content in the silver paste adopted in the electrode terminal working procedure is 60-70%, and the silver firing temperature is 600-800 ℃.
9. A sheet type piezoresistor prepared by the method according to any one of claims 1 to 8, wherein the ceramic material of the sheet type piezoresistor comprises a main crystal phase material and an additive, and the additive comprises Bi with a molar ratio of (1.0 to 2.0): (0.4 to 0.8): (1.0 to 2.0): (0.8 to 1.6): (0.2 to 0.8): (0.01 to 0.05): (0.02 to 0.08) 2 O 3 、Sb 2 O 3 、MnO 2 、Cr 2 O 3 、Co 2 O 3 、H 3 BO 3 、Zn 3 (PO 4 ) 2 ·4H 2 O、Nb 2 O 5 、AgNO 3 And Al (NO) 3 ) 3 ·9H 2 O is formed; the main crystal phase materialThe material is selected from zinc oxide.
10. An electronic device, wherein the electronic device comprises a chip varistor prepared by the method of any one of claims 1 to 8 or a chip varistor according to claim 9.
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