CN115064527A - 3D fan-out packaging structure of multiple radio frequency chips and manufacturing method thereof - Google Patents

3D fan-out packaging structure of multiple radio frequency chips and manufacturing method thereof Download PDF

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Publication number
CN115064527A
CN115064527A CN202210748724.9A CN202210748724A CN115064527A CN 115064527 A CN115064527 A CN 115064527A CN 202210748724 A CN202210748724 A CN 202210748724A CN 115064527 A CN115064527 A CN 115064527A
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layer
chip
metal wiring
wiring layer
carrier
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王国军
王全龙
郑毛荣
曹立强
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Priority to CN202210748724.9A priority Critical patent/CN115064527A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/111—Manufacture and pre-treatment of the bump connector preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body

Abstract

The invention relates to a 3D packaging structure of a multi-radio frequency chip, which comprises: the front surface of the wafer is provided with an I/O interface; the dielectric layer is positioned on the front side of the wafer; the first metal wiring layer is positioned in the dielectric layer and is electrically connected with the wafer; the carrier is connected with the wafer, the front surface of the carrier is provided with a cut-off layer, the second metal wiring layer is positioned in the cut-off layer and is partially exposed, and the back surface of the carrier is provided with a groove; the conductive silicon through hole is positioned in the slide glass and is electrically connected with the second metal wiring layer; a chip disposed in the recess; the filling medium is filled in a gap between the side wall of the groove and the chip and covers the back surface of the slide glass; the metal column is positioned in the filling medium and is electrically connected with the chip or the conductive silicon through hole; an insulating layer on the filling medium; the third metal wiring layer is positioned in the insulating layer and is electrically connected with the metal column and the solder ball; and a solder ball disposed on the third metal wiring layer.

Description

3D fan-out packaging structure of multiple radio frequency chips and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a 3D fan-out packaging structure of multiple radio frequency chips and a manufacturing method thereof.
Background
The millimeter wave radio frequency technology is rapidly developed in the semiconductor industry, and is widely applied to the fields of high-speed data communication, automobile radars, airborne missile tracking systems, space spectrum detection, imaging and the like. These applications put new demands on the electrical performance, compact structure and system reliability of the product, and for wireless transmitting and receiving systems, they cannot be integrated on the same chip (SOC) at present, so that it is necessary to integrate different chips including rf units, filters, power amplifiers, etc. into a single system to realize transmitting and receiving signals.
The traditional packaging technology is characterized in that various functional chips and passive devices are mounted on a base plate, the occupied area is large, the reliability is poor, and the trend that a packaging system is more and more miniaturized cannot be met.
Disclosure of Invention
The invention aims to provide a 3D fan-out packaging structure of multiple radio frequency chips and a manufacturing method thereof, wherein the chips are embedded into a silicon-based carrier plate, wafer-level packaging of the chips with different substrates is realized, electromagnetic interference of the radio frequency chips is shielded by forming shielding layers in grooves, and meanwhile, 3D packaging of multiple chips is realized by utilizing a silicon through hole technology, so that the packaging thickness is reduced.
In a first aspect of the present invention, to solve the problems in the prior art, the present invention provides a 3D package structure of multiple radio frequency chips, including:
the front surface of the wafer is provided with an I/O interface;
the dielectric layer is positioned on the front side of the wafer;
the first metal wiring layer is positioned in the dielectric layer and is electrically connected with the wafer;
the carrier is connected with the wafer, wherein the front surface of the carrier is provided with a cut-off layer, the second metal wiring layer is positioned in the cut-off layer and is partially exposed, and the back surface of the carrier is provided with a groove;
a conductive through-silicon-via located in the carrier and electrically connected to the second metal wiring layer;
a chip disposed in the recess;
a filling medium filling a gap between the side wall of the groove and the chip and covering the back surface of the carrier;
the metal column is positioned in the filling medium and is electrically connected with the chip or the conductive through silicon via;
an insulating layer on the filling medium;
a third metal wiring layer located in the insulating layer and electrically connected to the metal pillar and the solder ball; and
a solder ball disposed at the third metal wiring layer.
In one embodiment of the invention, the device further comprises a shielding layer which is positioned on the side wall and the bottom of the groove.
In one embodiment of the invention, the grooves are one or more; and/or
A plurality of chips are arranged in the same or different grooves; and/or
The front surface of the chip is provided with pins, the metal posts are electrically connected with the pins, and the back surface of the chip is attached to the bottom of the groove.
In an embodiment of the invention, the wafer and the carrier are connected by hybrid bonding, wherein the second metal wiring layer is bonded to the first metal wiring layer, and the stop layer is bonded to the dielectric layer.
In one embodiment of the present invention, the bottom of the groove is the cut-off layer.
In a second aspect of the present invention, to solve the problems in the prior art, the present invention provides a method for manufacturing a 3D package structure of multiple radio frequency chips, including:
forming a dielectric layer and a first metal wiring layer on the front surface of the wafer;
the wafer and the carrier are connected through hybrid bonding, wherein the front surface of the carrier is provided with a cut-off layer, the second metal wiring layer is positioned in the cut-off layer, part of the second metal wiring layer is exposed, and the conductive silicon through hole is positioned in the carrier and is electrically connected with the second metal wiring layer;
thinning the back of the carrier to expose the conductive through silicon hole;
etching a groove on the back of the slide glass to expose the cut-off;
arranging a chip in the groove;
filling media are arranged in a gap between the side wall of the groove and the chip and on the back of the carrier, and the filling media above the pins on the front surface of the chip and above the conductive silicon through holes are removed to form blind holes;
filling metal in the blind holes to form metal columns;
arranging an insulating layer and a third metal wiring layer in the insulating layer on the filling medium; and
solder balls are arranged on the third metal wiring layer.
In one embodiment of the invention, a shielding layer is made on the side walls and bottom of the recess before said step of arranging the chip in the recess.
In one embodiment of the invention, one or more grooves are etched on the back surface of the slide; and/or
One or more of the chips are disposed in the same or different recesses.
In one embodiment of the invention, the back side of the chip is attached to the bottom of the groove, and the metal posts are electrically connected with the pins of the chip.
In an embodiment of the invention, the wafer and the carrier are connected by hybrid bonding, wherein the second metal wiring layer is bonded to the first metal wiring layer, and the stop layer is bonded to the dielectric layer.
The invention has at least the following beneficial effects: the invention discloses a 3D fan-out packaging structure of a multi-radio frequency chip and a manufacturing method thereof.A chip is embedded into a silicon-based carrier plate, so that wafer-level packaging of chips with different substrates is realized; shielding electromagnetic interference of the radio frequency chip by forming a shielding layer in the groove; meanwhile, 3D packaging of multiple chips is realized by using a through silicon via technology, so that the packaging thickness is reduced; it is advantageous to form the interconnects in a vertical direction using a wafer instead of a common carrier.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 illustrates a cross-sectional view of a 3D package structure of a multi-RF chip formed in accordance with an embodiment of the present invention;
FIG. 2 illustrates a cross-sectional view of a 3D package structure of a shielded multi-radio frequency chip formed according to an embodiment of the invention; and
fig. 3A to 3P are schematic cross-sectional views illustrating a process of fabricating a 3D package structure of a multi-rf chip according to an embodiment of the invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing the present invention and to simplify the description, but are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and does not limit the order of the steps.
A 3D package structure of a multi-rf chip according to an embodiment of the invention is described in detail below with reference to fig. 1. Fig. 1 illustrates a cross-sectional view of a 3D package structure of a multi-rf chip formed according to an embodiment of the invention.
As shown in fig. 1, the 3D package structure of the multi-rf chip includes a wafer 101, a dielectric layer 102, a first metal wiring layer 103, a carrier 104, a groove, a stop layer 105, a second metal wiring layer 106, a conductive through silicon via 107, a chip 108, a filling medium 109, a metal pillar 110, an insulating layer 111, a third metal wiring layer 112, and a solder ball 113.
Wafer 101 has an I/O interface (not shown) on its front side. In one embodiment of the present invention, the substrate material of wafer 101 may be Si, GaN, GaAs, InP, or the like. Wafer 101 is an IC chip wafer in which fabrication of devices and/or functional elements has been completed.
And a dielectric layer 102 on the front side of the wafer 101. In one embodiment of the present invention, the dielectric layer 102 may be an inorganic insulating material such as silicon oxide. In another embodiment of the present invention, the dielectric layer 102 may also be an organic insulating material such as resin, PI, underfill, cured sheet, etc.
And a first metal wiring layer 103 located in the dielectric layer 102 and electrically connected to the wafer 101.
The first metal wiring layers 103 are single-layer or multi-layer, and the multi-layer first metal wiring layers are electrically connected with each other.
First metal routing layer 103 fans out the I/O interface of wafer 101.
The carrier sheet 104 has a cut-off layer 105 on the front side and a recess on the back side. The bottom of the groove is a stop layer 105, and specifically, the back surface of the carrier sheet 104 is etched until the stop layer 105 is exposed, so that the groove is formed. The stop layer 105 may be SiO 2 And inorganic materials such as SiN. The second metal wiring layer 106 is located in the stopper layer 105, and has a portion exposed. The second metal wiring layers 106 are single-layer or multi-layer, and the multi-layer second metal wiring layers are electrically connected with each other. And a conductive through-silicon-via 107 located in the carrier sheet 104 and electrically connected to the second metal wiring layer 106. The front side of the carrier sheet 104 is connected to the front side of the wafer 101 by hybrid bonding. Specifically, the second metal wiring layer 106 is bonded to the first metal wiring layer 103, and the stopper layer 105 is bonded to the dielectric layer 102.
A chip 108 disposed in a recess in the back side of the chip 104. The back surface of the chip 107 is bonded to the stopper layer 105 at the bottom of the groove with an adhesive material. The front side of the chip 108 has pins (not shown). The quantity of chip is a plurality of, and when need not shielding electromagnetic interference, a plurality of chips are placed in same recess.
A filling medium 109 filling the gap between the sidewalls of the recess and the chip 105 and covering the back side of the chip 104. Fill medium 109 is a light sensitive material.
And a metal pillar 110 located in the filling medium 109 and electrically connected to the chip 108 or the conductive through silicon via 107.
And an insulating layer 111 on the fill dielectric 109.
And a third metal wiring layer 112 located in the insulating layer 111 and electrically connected to the metal pillar 110 and the solder ball 113. The third metal wiring layers 112 are single-layer or multi-layer, and the multi-layer third metal wiring layers are electrically connected with each other.
And a solder ball 113 disposed on the third metal wiring layer 112.
A 3D package structure of a multi-rf chip with shielding layer according to an embodiment of the invention is described in detail below with reference to fig. 2. Fig. 2 is a schematic cross-sectional view illustrating a 3D package structure of a shielded multi-rf chip according to an embodiment of the invention.
When a plurality of chips need to shield the interference among the chips, the chips are arranged in different grooves, and a metal shielding layer is arranged on the side wall and the bottom of each groove.
This take shielding layer's 3D packaging structure of many radio frequency chips includes: the chip comprises a wafer 201, a dielectric layer 202, a first metal wiring layer 203, a carrier 204, a groove, a stop layer 205, a second metal wiring layer 206, a conductive through silicon via 207, a chip 208, a filling medium 209, a metal column 210, an insulating layer 211, a third metal wiring layer 212, a solder ball 213 and a shielding layer 214.
The embodiment described in fig. 2 has only the following differences compared to the embodiment described in fig. 1: the number of the grooves is multiple, the shielding layer 214 is formed on the side wall and the bottom of each groove, one chip 208 is placed in each groove, and the shielding layer 214 can shield electromagnetic interference among multiple chips.
A method for fabricating a 3D package structure of a multi-rf chip according to an embodiment of the invention is described in detail below with reference to fig. 3A to 3P. Fig. 3A to 3P are schematic cross-sectional views illustrating a process of fabricating a 3D package structure of a multi-rf chip according to an embodiment of the invention.
In step 1, as shown in fig. 3A, a dielectric layer 302 and a first metal wiring layer 303 are formed on the front surface of a wafer 301. A first metal wiring layer 303 is formed on the front surface of the wafer 301 through a damascene process, so that the lead-out of the I/O interface of the wafer 301 is realized. Specifically, a dielectric layer is coated on the front surface of the wafer 301, then the dielectric layer 302 is etched to form a circuit pattern, and a metal is plated on the circuit pattern to form a first metal wiring layer 303. The first metal wiring layers 303 are single-layered or multi-layered, and the multi-layered first metal wiring layers are electrically connected to each other. In one embodiment of the present method, the substrate material of the wafer 301 may be Si, GaN, GaAs, InP, or the like. In one embodiment of the present invention, the dielectric layer 302 may be an inorganic insulating material such as silicon oxide. In another embodiment of the present invention, the dielectric layer 302 may also be an organic insulating material such as resin, PI, underfill, cured sheet, etc.
At step 2, as shown in fig. 3B, the wafer 301 and the carrier 304 are connected by hybrid bonding. The front surface of the carrier sheet 304 has a stop layer 305, and a second metal wiring layer 306 is located in the stop layer 305 and partially exposed. Conductive through-silicon-vias 307 are located in the chip 304 and are electrically connected to the second metal wiring layer 306. The second metal wiring layers 306 are single-layer or multi-layer, and the multi-layer second metal wiring layers are electrically connected with each other. Conductive through-silicon-vias 307 do not extend through the carrier 304. The stop layer 305 may be SiO 2 And inorganic materials such as SiN. The front side of the carrier 304 is connected to the front side of the wafer 301 by a hybrid bond. Specifically, the second metal wiring layer 306 is bonded to the first metal wiring layer 303, and the stop layer 305 is bonded to the dielectric layer 302.
In step 3, as shown in fig. 3C, the backside of the carrier 304 is thinned to expose the conductive through-silicon vias 307. The wafer and the slide glass are bonded firstly and then thinned, so that the process steps can be simplified, the step of temporary bonding is not needed, the bonding is not needed to be released, and the thinned thickness of the slide glass 304 is smaller.
At step 4, as shown in fig. 3D and 3E, a groove 320 is etched in the back surface of the carrier 304, exposing the stop layer 305. One or more grooves 320 are etched in the back side of the carrier sheet 304 by dry etching or wet etching. The arrangement of the stop layer 305 can better control the etching depth, the depth uniformity is better, and the control on the patch depth and size is more accurate.
Optionally, at step 5, as shown in fig. 3F, a shielding layer 314 is formed on the sidewalls and bottom of the recess 320. The shielding layer 314 is formed on the sidewalls and bottom by electroplating metal, depositing metal, sputtering metal, etc. When a plurality of chips are required to be arranged subsequently and electromagnetic interference is generated among the chips, shielding layers are required to be arranged on the side walls and the bottom of the groove 320, and the chips are required to be arranged in different grooves.
At step 6, as shown in fig. 3G and 3H, chip 308 is disposed in recess 320. When shielding is not required between the chips 308, the chips 308 may be disposed at the bottom of the same or different groove 320 by an adhesive material, and the back surfaces of the chips 308 are adhered to the bottom of the groove 320. When electromagnetic interference between the chips 308 needs to be shielded, the chips 308 are arranged in different grooves 320 with shielding layers 314, and the back surfaces of the chips 308 are connected with the shielding layers 314 at the bottoms of the grooves 320 through bonding materials. A gap is left between the chip 308 and the sidewall of the groove 320. The front side of chip 308 has pins (not shown).
At step 7, as shown in fig. 3I and 3J, a fill dielectric 309 is disposed in the gap between the sidewalls of the recess 320 and the chip 308 and the backside of the chip 304, and the fill dielectric 309 is removed over the pins of the chip and over the conductive through-silicon-vias 307 to form blind vias 315. The filling medium 309 is arranged by a lamination process. Fill medium 309 is a light sensitive material. The blind holes 315 are formed by means of photolithography.
In step 8, as shown in fig. 3K and 3L, the blind via 315 is filled with a metal to form a metal pillar 310. The blind via 315 is filled with metal by electroplating, deposition, or the like.
In step 9, as shown in fig. 3M and 3N, an insulating layer 311 and a third metal wiring layer 312 located in the insulating layer 311 are disposed on the filling medium 309. The third metal wiring layer 312 is electrically connected to the metal pillar 310. An insulating layer 311 is coated on the filling medium 309, then the insulating layer 311 is etched to form a line pattern, and a metal is plated on the line pattern to form a third metal wiring layer 312. The third metal wiring layers 312 are single-layered or multi-layered, and the multi-layered third metal wiring layers are electrically connected to each other.
In step 10, as shown in fig. 3O and 3P, solder balls 313 are arranged on the third metal wiring layer 312.
The invention has at least the following beneficial effects: the invention discloses a 3D fan-out packaging structure of a multi-radio frequency chip and a manufacturing method thereof.A chip is embedded into a silicon-based carrier plate, so that wafer-level packaging of chips with different substrates is realized; shielding electromagnetic interference of the radio frequency chip by forming a shielding layer in the groove; meanwhile, 3D packaging of multiple chips is realized by using a through silicon via technology, so that the packaging thickness is reduced; it is advantageous to form the interconnects in a vertical direction using a wafer instead of a common carrier.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims (10)

1. A3D packaging structure of a multi-radio frequency chip comprises:
the front surface of the wafer is provided with an I/O interface;
the dielectric layer is positioned on the front side of the wafer;
the first metal wiring layer is positioned in the dielectric layer and is electrically connected with the wafer;
the carrier is connected with the wafer, wherein the front surface of the carrier is provided with a cut-off layer, the second metal wiring layer is positioned in the cut-off layer and is partially exposed, and the back surface of the carrier is provided with a groove;
a conductive through-silicon-via located in the carrier and electrically connected to the second metal wiring layer;
a chip disposed in the recess;
a filling medium filling a gap between the side wall of the groove and the chip and covering the back surface of the carrier;
the metal column is positioned in the filling medium and is electrically connected with the chip or the conductive through silicon via;
an insulating layer on the filling medium;
a third metal wiring layer located in the insulating layer and electrically connected to the metal pillar and the solder ball; and
a solder ball disposed at the third metal wiring layer.
2. The 3D packaging structure of the multi-radio-frequency chip, according to claim 1, further comprising a shielding layer located on the side wall and the bottom of the groove.
3. The 3D packaging structure of the multi-radio-frequency chip according to claim 1, wherein the number of the grooves is one or more; and/or
A plurality of chips are arranged in the same or different grooves; and/or
The front surface of the chip is provided with pins, the metal posts are electrically connected with the pins, and the back surface of the chip is attached to the bottom of the groove.
4. The 3D packaging structure of the multi-radio-frequency chip, according to claim 1, wherein the wafer is connected with the carrier by hybrid bonding, wherein the second metal wiring layer is bonded with the first metal wiring layer, and the cut-off layer is bonded with the dielectric layer.
5. The 3D packaging structure of the multi-radio-frequency chip as claimed in claim 1, wherein the bottom of the groove is the cut-off layer.
6. A manufacturing method of a 3D packaging structure of a multi-radio-frequency chip comprises the following steps:
forming a dielectric layer and a first metal wiring layer on the front side of the wafer;
the wafer and the carrier are connected through hybrid bonding, wherein the front surface of the carrier is provided with a cut-off layer, the second metal wiring layer is positioned in the cut-off layer, part of the second metal wiring layer is exposed, and the conductive silicon through hole is positioned in the carrier and is electrically connected with the second metal wiring layer;
thinning the back of the carrier to expose the conductive through silicon hole;
etching a groove on the back of the slide glass to expose the cut-off;
arranging a chip in the groove;
filling media are arranged in a gap between the side wall of the groove and the chip and on the back of the carrier, and the filling media above the pins on the front surface of the chip and above the conductive silicon through holes are removed to form blind holes;
filling metal in the blind holes to form metal columns;
arranging an insulating layer and a third metal wiring layer in the insulating layer on the filling medium; and
solder balls are disposed on the third metal wiring layer.
7. The method for fabricating a 3D package structure of multiple radio frequency chips according to claim 6, wherein before the step of disposing the chip in the groove, shielding layers are fabricated on the side walls and the bottom of the groove.
8. The method for manufacturing the 3D packaging structure of the multi-radio-frequency chip according to claim 6, wherein one or more grooves are etched on the back surface of the carrier; and/or
One or more of the chips are disposed in the same or different recesses.
9. The method for manufacturing a 3D package structure of multiple radio frequency chips according to claim 6, wherein the back surface of the chip is attached to the bottom of the groove, and the metal posts are electrically connected with the pins of the chip.
10. The method for manufacturing the 3D packaging structure of the multi-radio-frequency chip, according to claim 6, wherein the wafer is connected with the slide glass through hybrid bonding, the second metal wiring layer is bonded with the first metal wiring layer, and the cut-off layer is bonded with the dielectric layer.
CN202210748724.9A 2022-06-29 2022-06-29 3D fan-out packaging structure of multiple radio frequency chips and manufacturing method thereof Pending CN115064527A (en)

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