CN115051703A - Time signal performance optimization method and device based on second-order digital phase-locked loop - Google Patents
Time signal performance optimization method and device based on second-order digital phase-locked loop Download PDFInfo
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Abstract
The invention discloses a time signal performance optimization method and a time signal performance optimization device based on a second-order digital phase-locked loop, wherein the method comprises the following steps of: acquiring a first single-sideband phase noise curve and a first frequency stability curve of an input frequency source and a second single-sideband phase noise curve and a second frequency stability curve of a local crystal oscillator, and determining a first loop gain of a second-order digital phase-locked loop based on the first single-sideband phase noise curve and the second single-sideband phase noise curve; determining a first time constant and a first proportional coefficient of a second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve and the second frequency stability curve; and adjusting the second-order digital phase-locked loop according to the first loop gain, the first time constant and the first proportional coefficient to complete the optimization of the time signal performance. According to the invention, the loop gain, the time constant and the proportionality coefficient of the second-order digital phase-locked loop are adjusted, so that the time signal can give consideration to the long-term stability characteristic and the short-term stability characteristic of the two frequency sources.
Description
Technical Field
The invention relates to the technical field of performance optimization of frequency source output signals, in particular to a time signal performance optimization method and device based on a second-order digital phase-locked loop.
Background
With the development of social economy and science and technology, national infrastructures such as electric power, communication, traffic and finance need high-precision time references to support wide-area and large-scale systems to realize accurate synchronization. Nowadays, satellite navigation positioning time service technology is widely applied to various industries of China-designed civilian life, and official time service precision of Beidou No. three satellite navigation time service technology reaches 10 ns. However, due to the requirement of high-precision time service, the time frequency signal which needs to be acquired has high accuracy and high stability. For the time service accuracy, the frequency source with higher time service precision is accessed to meet the corresponding requirements; for the time frequency signal output by the frequency source, the requirement of both long-term stability and short-term stability is required, and a single frequency source cannot meet the requirement. However, when a plurality of frequency sources are fused, the signals output by the respective frequency sources are liable to have errors in frequency and phase. In order to achieve the synchronization of the frequency and Phase of the signals output by the frequency sources, a Digital Phase Locked Loop (DPLL) is introduced to drive the local crystal oscillator. The tracking and locking performance (tracking and locking error, frequency stability) of the DPLL is closely related to the loop parameters, and therefore, the selection of the loop parameters of the DPLL is crucial in the process of optimizing the performance of the time-frequency signal output by the frequency source.
In the existing performance optimization method based on the frequency source output signal, the observation noise variance and the loop gain of the DPLL are usually adjusted and optimized to obtain the optimal loop parameter combination, thereby realizing the optimization of the performance of the output signal. However, although the above optimization method satisfies the requirement that the time frequency signal needs to have both long-term stability and short-term stability by using the characteristics of the DPLL and combining the stability characteristics of the input frequency source and the local crystal oscillator, the long-term stability and the short-term stability of the time frequency signal that is finally output are still greatly deteriorated compared to the original input frequency source and the local crystal oscillator.
Disclosure of Invention
The invention provides a time signal performance optimization method and a time signal performance optimization device based on a second-order digital phase-locked loop.
In order to solve the above technical problem, an embodiment of the present invention provides a time signal performance optimization method based on a second-order digital phase-locked loop, including:
acquiring a first single-sideband phase noise curve and a first frequency stability curve of an input frequency source and a second single-sideband phase noise curve and a second frequency stability curve of a local crystal oscillator, and determining a first loop gain of a second-order digital phase-locked loop based on the first single-sideband phase noise curve and the second single-sideband phase noise curve;
determining a first time constant of the second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve and the second frequency stability curve based on a preset parameter selection condition, and determining a first proportional coefficient of the second-order digital phase-locked loop by combining the first loop gain, the first time constant, the first frequency stability curve and the second frequency stability curve;
and adjusting final loop parameters of the second-order digital phase-locked loop according to the first loop gain, the first time constant and the first scale coefficient to optimize the performance of a time signal, wherein the time signal is output by the local crystal oscillator after being driven based on the input frequency source of the second-order digital phase-locked loop.
By implementing the embodiment of the application, before the time constant is adjusted, the loop bandwidth of the second-order digital phase-locked loop is determined according to the comparison of the single-sideband phase noise curves of the input frequency source and the local crystal oscillator, so that the optimization of the single-sideband phase noise of the finally output time signal is realized, the single-sideband phase noise is prevented from influencing the contrast effect of the frequency stability, and further the overall performance optimization is influenced. Then, the tracking locking performance of the second-order digital phase-locked loop is optimized by adopting a method of adjusting loop parameters of the second-order digital phase-locked loop for multiple times, so that after the local crystal oscillator is controlled by an input frequency source based on the second-order digital phase-locked loop, the output time signal can take the long-term stability characteristic of the input frequency source and the short-term stability characteristic of the local crystal oscillator into consideration, the synchronous optimization of the time signal on single-sideband phase noise and frequency stability is completed, and the optimization effect of the time signal performance is further improved.
As a preferred scheme, the adjusting a final loop parameter of the second-order digital phase-locked loop according to the first loop gain, the first time constant, and the first proportional coefficient to complete the optimization of the performance of the time signal specifically includes:
adjusting the first time constant and the first proportional coefficient for a plurality of times respectively, and obtaining a third frequency stability curve of the time signal after each adjustment;
based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the third frequency stability curves, selecting the first loop gain, the first time constant and the first scale coefficient corresponding to the third frequency stability curve meeting a first preset condition from all the third frequency stability curves as final loop parameters of the second-order digital phase-locked loop, and completing the optimization of the performance of the time signal.
According to the implementation of the preferred scheme of the embodiment of the application, on the basis of the preliminarily selected first time constant and first scale coefficient, a method of adjusting and approaching optimization for multiple times is adopted, the time constant and the scale coefficient of the second-order digital phase-locked loop are adjusted for multiple times, and then the first loop gain, the first time constant and the first scale coefficient corresponding to the optimal curve meeting the preset conditions are selected from the third frequency stability curve of the time signal after each adjustment to serve as final loop parameters of the second-order digital phase-locked loop, so that the long-term and short-term frequency stability of the time signal is further optimized.
As a preferred scheme, the determining a first time constant of the second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve and the second frequency stability curve based on a preset parameter selection condition specifically includes:
according to the first loop gain, combining a plurality of second time constants to obtain a plurality of fourth frequency stability curves of the time signals;
obtaining a relation between the second time constant and an intersection sampling period based on comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fourth frequency stability curves, and determining a first time constant of the second-order digital phase-locked loop according to the relation between the second time constant and the sampling period;
the second time constant and the fourth frequency stability curve are in one-to-one correspondence, and the intersection sampling period is a sampling period corresponding to an intersection of the first frequency stability curve and the second frequency stability curve.
According to the preferable scheme of the embodiment of the application, through the comparative analysis among the first frequency stability curve, the second frequency stability curve and the fourth frequency stability curve corresponding to different second time constants, the change relation of the time constant and the frequency stability and the relation of the time constant and the sampling period corresponding to the intersection point of the two frequency source curves are determined, the preliminary optimization result of the time constant of the second-order digital phase-locked loop is determined according to the determined relation, and parameter adjustment basis and reference are provided for the subsequent further optimization of the time constant.
As a preferred scheme, the determining, according to the first loop gain, a first scaling factor of the second-order digital phase-locked loop by combining the first loop gain, the first time constant, the first frequency stability curve, and the second frequency stability curve specifically includes:
according to the first loop gain and the first time constant, combining a plurality of second proportionality coefficients to obtain a plurality of fifth frequency stability curves of the time signals;
based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fifth frequency stability curves, selecting the second proportional coefficient corresponding to the fifth frequency stability curve meeting a third preset condition from all the fifth frequency stability curves as a first proportional coefficient of the second-order digital phase-locked loop;
and the second proportionality coefficient corresponds to the fifth frequency stability curve one by one.
According to the preferred scheme of the embodiment of the application, through the comparative analysis among the first frequency stability curve, the second frequency stability curve and the fifth frequency stability curve corresponding to different second proportionality coefficients, the change relation between the proportionality coefficients and the frequency stability is determined, the second proportionality coefficient corresponding to the fifth frequency stability curve meeting a second preset condition is selected from the change relation, the second proportionality coefficient is used as the preliminary optimization result of the proportionality coefficients of the second-order digital phase-locked loop, another loop parameter of the second-order digital phase-locked loop is further optimized on the basis of finishing the preliminary optimization of the time constant of the second-order digital phase-locked loop, and a parameter adjusting basis and a reference are provided for the further optimization of the subsequent proportionality coefficients.
In order to solve the same technical problem, the invention also provides a time signal performance optimization device based on a second-order digital phase-locked loop, which comprises:
the data acquisition module is used for acquiring a first single-sideband phase noise curve and a first frequency stability curve of an input frequency source and a second single-sideband phase noise curve and a second frequency stability curve of a local crystal oscillator, and determining a first loop gain of the second-order digital phase-locked loop based on the first single-sideband phase noise curve and the second single-sideband phase noise curve;
the parameter selection module is used for determining a first time constant of the second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve and the second frequency stability curve based on a preset parameter selection condition, and determining a first proportional coefficient of the second-order digital phase-locked loop by combining the first loop gain, the first time constant, the first frequency stability curve and the second frequency stability curve;
and the performance optimization module is used for adjusting final loop parameters of the second-order digital phase-locked loop according to the first loop gain, the first time constant and the first scale coefficient to complete optimization of the performance of a time signal, wherein the time signal is output after the local crystal oscillator is manipulated by the second-order digital phase-locked loop.
As a preferred scheme, the performance optimization module specifically includes:
the parameter adjusting unit is used for respectively adjusting the first time constant and the first proportional coefficient for a plurality of times and acquiring a third frequency stability curve of the time signal after each adjustment;
and the performance optimization unit is used for selecting the first loop gain, the first time constant and the first scale coefficient corresponding to the third frequency stability curve meeting a first preset condition from all the third frequency stability curves based on the contrastive analysis among the first frequency stability curve, the second frequency stability curve and all the third frequency stability curves, and using the first loop gain, the first time constant and the first scale coefficient as final loop parameters of the second-order digital phase-locked loop to complete the optimization of the performance of the time signal.
As a preferred scheme, the parameter selection module specifically includes:
the first parameter selection unit is used for acquiring a fourth frequency stability curve of the plurality of time signals by combining a plurality of second time constants according to the first loop gain; obtaining the relation between the second time constant and the intersection sampling period based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fourth frequency stability curves, and determining the first time constant of the second-order digital phase-locked loop according to the relation between the second time constant and the sampling period; the second time constant and the fourth frequency stability curve correspond to each other one by one, the intersection sampling period is a sampling period corresponding to an intersection of the first frequency stability curve and the second frequency stability curve, and the intersection sampling period is a sampling period corresponding to an intersection of the first frequency stability curve and the second frequency stability curve;
a second parameter selection unit, configured to obtain, according to the first loop gain and the first time constant, a fifth frequency stability curve of the plurality of time signals by combining a plurality of second scaling coefficients; based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fifth frequency stability curves, selecting the second proportional coefficient corresponding to the fifth frequency stability curve meeting a third preset condition from all the fifth frequency stability curves as a first proportional coefficient of the second-order digital phase-locked loop; and the second proportionality coefficient corresponds to the fifth frequency stability curve one by one.
In order to solve the same technical problem, the invention also provides a terminal, which comprises a processor, a memory and a computer program stored in the memory; wherein the computer program is executable by the processor to implement the second-order digital phase-locked loop based time signal performance optimization method.
In order to solve the same technical problem, the present invention also provides a computer-readable storage medium including a stored computer program; and when the computer program runs, controlling the equipment where the computer readable storage medium is located to execute the time signal performance optimization method based on the second-order digital phase-locked loop.
Drawings
FIG. 1: the invention provides a flow diagram of an embodiment of a time signal performance optimization method based on a second-order digital phase-locked loop;
FIG. 2: the invention provides a schematic diagram of the implementation principle of one embodiment of the time signal performance optimization method based on a second-order digital phase-locked loop;
FIG. 3: the invention provides a comparison graph of single-sideband phase noise curves of a cesium clock and a high-stability crystal oscillator based on an embodiment of a time signal performance optimization method of a second-order digital phase-locked loop;
FIG. 4: the invention provides a frequency stability curve contrast diagram of a cesium clock and a high-stability crystal oscillator of an embodiment of a time signal performance optimization method based on a second-order digital phase-locked loop;
FIG. 5: the invention provides a frequency stability curve contrast diagram of a cesium clock, a high-stability crystal oscillator and a driven high-stability crystal oscillator under different time constants for an embodiment of a time signal performance optimization method based on a second-order digital phase-locked loop;
FIG. 6: the invention provides a schematic diagram of a second-order digital phase-locked loop structure of an embodiment of a time signal performance optimization method based on a second-order digital phase-locked loop;
FIG. 7: the invention provides a time signal performance optimization method based on a second-order digital phase-locked loop, which comprises the steps of comparing frequency stability curves of a cesium clock, a high-stability crystal oscillator and a driven high-stability crystal oscillator under different proportionality coefficients;
FIG. 8: the invention provides a frequency stability curve contrast diagram of a driven high-stability crystal oscillator under the combination of a cesium clock, the high-stability crystal oscillator and different parameters of an embodiment of a time signal performance optimization method based on a second-order digital phase-locked loop;
FIG. 9: the invention provides a structure schematic diagram of a time signal performance optimization device based on a second-order digital phase-locked loop.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
The first embodiment is as follows:
referring to fig. 1, a method for optimizing a time signal performance based on a second-order digital phase-locked loop according to an embodiment of the present invention includes steps S1 to S3, where the steps are as follows:
step S1, a first single-sideband phase noise curve and a first frequency stability curve of the input frequency source, and a second single-sideband phase noise curve and a second frequency stability curve of the local crystal oscillator are obtained, and a first loop gain of the second-order digital phase-locked loop is determined based on the first single-sideband phase noise curve and the second single-sideband phase noise curve.
As an example, with a cesium clock Cs as an input frequency source and a high-stability crystal oscillator OSA as a local crystal oscillator, referring to fig. 2, a description is specifically given of an expression of an output signal of the driven high-stability crystal oscillator OSA based on a second-order Digital Phase Locked Loop (DPLL) by using a principle that the cesium clock Cs drives the high-stability crystal oscillator OSA, referring to equation (1). Where Ref represents the input signal of the second-order digital phase-locked loop/output signal of the cesium clock Cs, OCXO represents the output signal of the high-stability crystal oscillator OSA, stepped OCXO represents the output signal of the driven high-stability crystal oscillator OSA, and g (Z) represents the open-loop transfer function of the DPLL in the Z-domain.
Wherein H (z) and H e (z) represents the closed loop system transfer function and the closed loop error transfer function of the DPLL, respectively. As can be seen from equation (1), the phase noise in the DPLL loop mainly comes from the input signal Ref and the high stability oscillator OSA.
Based on the above, phase noise index data of the two frequency sources under different bandwidths are respectively obtained, and specific index data are detailed in table 1. According to the acquired index data, single-sideband phase noise curves of the cesium clock (Cs3000) and the high-stability crystal oscillator (OSA8607) are respectively drawn, please refer to fig. 3, which is a comparison graph of single-sideband phase noise curves of two frequency sources formed by original single-sideband phase noise curves of the cesium clock (Cs3000) and the high-stability crystal oscillator (OSA8607), wherein a horizontal axis represents a bandwidth lg (f), and a vertical axis represents single-sideband phase noise (SSB phase noise).
TABLE 1 SSB phase noise index data for cesium clock (Cs3000) and high stability crystal oscillator (OSA8607)
| Bandwidth lg (f)/ |
1 | 10 | 100 | 1000 | 10000 |
| SSB phase noise of OSA8607 | －121 | －137 | －146 | －146 | －146 |
| SSB phase noise of Cs3000 | －110 | －130 | －140 | －140 | －140 |
Because the DPLL filters the input signal Ref in a low-pass manner and the high-stability crystal oscillator OSA in a high-pass manner, and the phase noise is superior to the near-end phase noise of the cesium clock Cs and the far-end phase noise of the high-stability crystal oscillator OSA, the loop gain is set at the intersection of the single-sideband phase noise curves of the two frequency sources, the phase noise of the cesium clock Cs is output in band, the phase noise of the high-stability crystal oscillator OSA is output out of band, and the optimization of the time signal phase noise is realized.
As an example, the loop gain K takes a value of 0.5.
Step S2, determining a first time constant of the second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve, and the second frequency stability curve based on a preset parameter selection condition, and determining a first scaling factor of the second-order digital phase-locked loop by combining the first loop gain, the first time constant, the first frequency stability curve, and the second frequency stability curve.
Preferably, the step S2 includes steps S21 to S24, and each step is as follows:
step S21, according to the first loop gain, combining a plurality of second time constants to obtain a plurality of fourth frequency stability curves of the time signal; the second time constant and the fourth frequency stability curve are in one-to-one correspondence, and the intersection sampling period is a sampling period corresponding to an intersection of the first frequency stability curve and the second frequency stability curve.
In the present embodiment, the time constant T indicates how often the high-stability crystal oscillator OSA is controlled by adjustment, i.e., the cesium clock Cs is automatically "aligned" with the high-stability crystal oscillator OSA by the phase-locked loop every time T elapses. Within the time constant T, the high-stability crystal oscillator OSA works according to the characteristics of the high-stability crystal oscillator OSA, and if the time constant T does not accord with the speed of the change of the current loop allowed signal, the instability of the loop or the reduction of the tracking performance can be caused, so that the selection of the time constant has an important influence on the result of the frequency stability.
In addition, since the frequency stability of the frequency source cannot be characterized by standard deviation in the time domain, the frequency stability is usually described by allen (Allan) variance, and the Allan variance can remove the influence of a shorter time scale and a longer time scale, and accurately describe the stability within one order of magnitude. Frequency stability index data of the two frequency sources under different sampling periods are respectively obtained, and specific index data are detailed in table 2. According to the acquired index data, frequency stability index curves of the cesium clock (Cs3000) and the high-stability crystal oscillator (OSA8607) are respectively drawn. And simultaneously simulating the cesium clock (Cs3000) and the high-stability crystal oscillator (OSA8607) to respectively obtain frequency stability simulation curves of the cesium clock (Cs3000) and the high-stability crystal oscillator (OSA8607), judging the reasonability of the frequency stability simulation curves according to the attaching degrees of the frequency stability index curve and the frequency stability simulation curve of the frequency source, and when the attaching degrees meet preset requirements, respectively taking the frequency stability simulation curve of the cesium clock (Cs3000) and the frequency stability simulation curve of the high-stability crystal oscillator (OSA8607) as a first frequency stability curve of the input frequency source and a second frequency stability curve of the local crystal oscillator as the basis for parameter adjustment and optimization. Alternatively, the frequency stability index curves of the cesium clock (Cs3000) and the high-stability crystal oscillator (OSA8607) may be directly used as the first frequency stability curve of the input frequency source and the second frequency stability curve of the local crystal oscillator, respectively.
Fig. 4 is a graph comparing the frequency stability index curves of the cesium clock (Cs3000) and the high stable crystal oscillator (OSA8607), and it is obvious from the graph that the cesium clock (Cs3000) has excellent long-term stability and the high stable crystal oscillator (OSA8607) has excellent frequency stability index curves8607) The short-term stability of (2) is excellent, so the optimal output of the frequency stability is: the performance of a high-stability crystal oscillator (OSA8607) is output within a sampling period corresponding to an intersection of two frequency stability curves, and the performance of a cesium clock (Cs3000) is output outside the sampling period corresponding to the intersection. Thus, it can be concluded that: the intersection value tau of a first frequency stability curve of an input frequency source and a second frequency stability curve of a local crystal oscillator 0 The time constant T of the second-order DPLL is adjusted for a plurality of times based on the preset value as a preset value of the time constant T, the time constant T is infinitely approximated, and the time signal output by the driven high-stability crystal oscillator can be made to have the long-term stability of the cesium clock (Cs3000) and the short-term stability of the high-stability crystal oscillator (OSA8607) at the same time.
TABLE 2 frequency stability index data for cesium clock (Cs3000) and high stability crystal oscillator (OSA8607)
| Sampling period tau/ |
1 | 10 | 100 | 1000 | 10000 |
| Frequency stability of OSA8607 | 1.7×10 -13 | 1.3×10 -13 | 1.4×10 -13 | 2.5×10 -13 | 1.7×10 -12 |
| Frequency stability of |
3×10 -12 | 2.4×10 -12 | 5.2×10 -13 | 1.9×10 -13 | 5×10 -14 |
As an example, the intersection value τ of two frequency stability curves 0 The time constant is 500s, namely the preset value of the time constant is 500s, several second time constants are selected near the preset value, and are respectively 200s, 250s, 300s and 400s, then the time constant of the second-order DPLL is respectively set to 200s, 250s, 300s and 400s, so as to obtain an Allan variance curve of the driven high-stability crystal oscillator corresponding to each second time constant, please refer to fig. 5, which is a comparison graph of frequency stability curves of the driven high-stability crystal oscillator under different time constants, and a cesium clock (Cs3000), a high-stability crystal oscillator (OSA8607) which are jointly formed by the Allan variance curve of the cesium clock (Cs3000), the Allan variance curve of the high-stability crystal oscillator (OSA8607) and the Allan variance curves of the driven high-stability crystal oscillator corresponding to the four different second time constants. Wherein the horizontal axis of the contrast chart is the sampling period tau in seconds(s), such as 10 0 Represents a sample per second, 10 1 Represents sampling every ten seconds; the vertical axis is dimensionless Allan variance, with relativity. The smaller the Allan variance is, the smaller the data fluctuation amplitude under the corresponding sampling period is, and the higher the stability of the time sequence is.
Step S22, obtaining a relationship between the second time constant and the intersection sampling period based on the comparative analysis among the first frequency stability curve, the second frequency stability curve, and all the fourth frequency stability curves, and determining the first time constant of the second-order digital phase-locked loop according to the relationship between the second time constant and the sampling period.
Referring to fig. 5, the frequency stability curves of the driven high-stability crystal oscillator under four different time constants have approximately the same trend, and the Allan variance increases from small to large and then decreases from large to small as the sampling period increases. It is clear that the use of a phase locked loop keeps the good stability of the high stability crystal oscillator (OSA8607) on the short time scale and the good stability of the cesiated clock (Cs3000) on the long time scale, except for the deterioration interval of hundreds to thousands of seconds.
In addition, when the sampling period is 300s, the acquisition process of the Allan variance is abnormal, so that the Allan variance curve corresponding to the sampling period of 300s is excluded to avoid the influence on the analysis result. Then, by comparing the cases where the sampling periods are 200s, 250s, 400s longitudinally, respectively, it can be concluded that: the stability at each scale is best, the second is. From this, an empirical conclusion can be drawn: the time constant can be selected to be half of the sampling period corresponding to the intersection point of the two frequency source alan variance curves, and the relational expression is shown in equation (2). And then, in the subsequent debugging process, determining a first time constant of the second-order digital phase-locked loop according to the sampling period corresponding to the intersection point of the current two frequency source Allan variance curves and the combination formula (2).
Step S23, according to the first loop gain and the first time constant, combining a plurality of second proportionality coefficients to obtain a fifth frequency stability curve of a plurality of time signals; and the second proportionality coefficient corresponds to the fifth frequency stability curve one by one.
In this embodiment, please refer to fig. 6, which is a schematic diagram of a second-order DPLL structure, where the loop gain expression of the second-order DPLL refers to equation (3), and the closed-loop system transfer function expression of the second-order DPLL refers to equation (4). Wherein PD denotes a phase detector for identifying a phase difference between an input signal (i.e., an output signal of the cesium clock Cs) and an output signal (i.e., an output signal of the mounted high-stability crystal oscillator OSA);the VCO represents a voltage controlled oscillator for controlling the frequency of its output signal; k is a radical of p Representing a scaling factor of the phase detector; k is a radical of 1 A first scale factor representing a first scale unit; k is a radical of 2 A second scaling factor representing a second scaling unit; k is a radical of v Represents the integral coefficient of the voltage controlled oscillator.
K＝k p k v k 1 (3)
For DPLL stability, the most straightforward way to determine is to determine whether the poles of the closed-loop system transfer function h (Z) in the Z domain are all within the unit circle, and if any one pole in the loop is outside the unit circle, the loop must be unstable, where the pole expression of h (Z) refers to equation (5). For the DPLL, as long as k 2 <1, expression of stability margin refers to equation (6), and when k 2 >When 1, the loop is unstable because the loop gain K is more than 0.
Therefore, the selection of the second-order DPLL proportionality coefficient can affect the loop gain of the second-order DPLL and the stability of the second-order DPLL to a certain extent, thereby affecting the frequency stability of the driven high-stability crystal oscillator. Based on this, as an example, according to k 2 <1, randomly selecting a plurality of second proportionality coefficients, such as 1.5 × 10 -5 、1.2×10 -5 、1×10 -5 And 8X 10 -6 And setting the proportionality coefficients of the second-order DPLL to the selected values of the second proportionality constants, respectively, to obtain an allen variance curve of the driven highly stable crystal oscillator corresponding to each second proportionality coefficient, please refer to fig. 7, which is a curve obtained by cesium clock (Cs 30)00) The Allan variance curve of the high-stability crystal oscillator (OSA8607) and the Allan variance curve of the driven high-stability crystal oscillator corresponding to the four different second proportionality coefficients form a cesium clock (Cs3000), the high-stability crystal oscillator (OSA8607) and a frequency stability curve contrast diagram of the driven high-stability crystal oscillator under different proportionality coefficients. Wherein the horizontal axis of the contrast plot is also the sampling period τ in seconds, e.g. 10 0 Represents a sample per second, 10 1 Represents sampling every ten seconds; the vertical axis is also dimensionless Allan variance with relativity. The smaller the Allan variance is, the smaller the data fluctuation amplitude under the corresponding sampling period is, and the higher the stability of the time sequence is.
Step S24, based on the comparative analysis among the first frequency stability curve, the second frequency stability curve, and all the fifth frequency stability curves, selecting the second scaling factor corresponding to the fifth frequency stability curve meeting a third preset condition from all the fifth frequency stability curves as the first scaling factor of the second-order digital phase-locked loop.
Referring to fig. 7, the trend of the frequency stability curve of the driven high-stability crystal oscillator under four different scaling factors is approximately the same, and as the sampling period increases, the Allan variance increases from small to large and then decreases from large to small. It can be seen that the frequency curves corresponding to the time signals output by all the high-stability crystal oscillators driven by the cesium clock (Cs3000) can better approach the high-stability crystal oscillator (OSA8607) in short-term stability and approach the cesium clock (Cs3000) in long-term stability, respectively, and compared with fig. 5, the frequency deterioration interval of the time signals output by the high-stability crystal oscillator driven by the cesium clock is obviously narrowed, i.e., the stability of the time signals is further improved.
By longitudinal contrast of the proportionality coefficient k 2 Is 1.5X 10 -5 、1.2×10 -5 、1×10 -5 Or 8X 10 -6 In the case of (2), it can be found that the different proportionality coefficients k 2 All the Allan variance curves of the corresponding driven high-stability crystal oscillators intersect at the position of tau being 900 s. When k is 2 >1×10 -5 When τ is 900s, the left curve ratio k 2 ＝1×10 -5 The curve of (a) is higher, i.e. the stability performance is worse,curve ratio k to the right of τ 900s 2 ＝1×10 -5 The curve of (a) is lower, i.e. the stability is better. However, when k is 2 <1×10 -5 When τ is 900s, the left curve ratio k 2 ＝1×10 -5 Is lower, i.e. stability is higher, the curve ratio k to the right of t 900s 2 ＝1×10 -5 The curve of (a) is higher, i.e., the stability is worse. And calculating the total attenuation according to the comparison of the short-term stability of the driven high-stability crystal oscillator and the original high-stability crystal oscillator and the long-term stability of the cesium clock under each proportionality coefficient, wherein the lower the total attenuation is, the better the stability performance is. Combining the above analyses, select k 2 ＝1.2×10 -5 And the first scale coefficient is used as the first scale coefficient of the second-order digital phase-locked loop to finish the initial selection of the scale coefficient.
And step S3, adjusting final loop parameters of the second-order digital phase-locked loop according to the first loop gain, the first time constant and the first scale factor, so as to optimize performance of a time signal, wherein the time signal is output by the local crystal oscillator after being manipulated based on the input frequency source of the second-order digital phase-locked loop.
Preferably, the step S3 includes a step S31 to a step S32, and each step is as follows:
step S31, adjusting the first time constant and the first scale factor for several times, and obtaining a third frequency stability curve of the time signal after each adjustment.
After the time constant T and the proportionality coefficient k are finished in sequence 2 After the rough parameter adjustment, the first time constant and the first scaling factor are adjusted several times, for example, 200s, k can be taken as ═ T ═ k 2 Two parameter combinations of 1.25 × 10-5, T250 s, and k2 1.2 × 10-5 are set, and the time constant T and the proportionality constant k of the second-order DPLL are set according to the parameter combinations described above 2 To obtain the Allan variance curve of the driven highly stable crystal oscillator corresponding to different parameter combinations, please refer to FIG. 8, which is the Allan variance curve of the cesium clock (Cs3000), the highly stable crystal oscillator (OSA8607) and the driven highly stable crystal oscillator corresponding to the above two different parameter combinationsThe Allan variance curve of the stable crystal oscillator and the frequency stability curve contrast chart of the driven high-stability crystal oscillator under different parameter combinations of the cesium clock (Cs3000), the high-stability crystal oscillator (OSA8607) and the stable crystal oscillator which are jointly formed.
Step S32, based on the comparative analysis among the first frequency stability curve, the second frequency stability curve, and all the third frequency stability curves, selecting the first loop gain, the first time constant, and the first scale coefficient corresponding to the third frequency stability curve that satisfies a first preset condition from all the third frequency stability curves as final loop parameters of the second-order digital phase-locked loop, and completing the optimization of the performance of the time signal.
In the embodiment, the time constant T and the proportionality coefficient k of different second-order DPLLs are compared longitudinally 2 When T is 200s, k is 2 ＝1.25×10 -5 The riding effect is optimal. Therefore, the parameter combination is selected as the final loop parameter of the second-order digital phase-locked loop, the joint parameter adjustment of the loop parameter of the second-order DPLL is completed, the integral driving performance is further improved, and the phase noise, the long-term frequency stability and the short-term frequency stability of the time signal are synchronously optimized.
Correspondingly, referring to fig. 9, the time signal performance optimizing apparatus based on a second-order digital phase-locked loop according to the embodiment of the present invention includes a data obtaining module 1, a parameter selecting module 2, and a performance optimizing module 3, where each module specifically includes:
the data acquisition module 1 is configured to acquire a first single-sideband phase noise curve and a first frequency stability curve of an input frequency source, and a second single-sideband phase noise curve and a second frequency stability curve of a local crystal oscillator, and determine a first loop gain of a second-order digital phase-locked loop based on the first single-sideband phase noise curve and the second single-sideband phase noise curve;
the parameter selection module 2 is configured to determine a first time constant of the second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve, and the second frequency stability curve based on a preset parameter selection condition, and determine a first scaling factor of the second-order digital phase-locked loop by combining the first loop gain, the first time constant, the first frequency stability curve, and the second frequency stability curve;
and a performance optimization module 3, configured to adjust a final loop parameter of the second-order digital phase-locked loop according to the first loop gain, the first time constant, and the first scale coefficient, so as to complete performance optimization of a time signal, where the time signal is output after the local crystal oscillator is manipulated by the second-order digital phase-locked loop.
As a preferred scheme, the performance optimization module 3 specifically includes:
the parameter adjusting unit is used for respectively adjusting the first time constant and the first proportional coefficient for a plurality of times and acquiring a third frequency stability curve of the time signal after each adjustment;
and the performance optimization unit is used for selecting the first loop gain, the first time constant and the first scale coefficient which meet a first preset condition and correspond to the third frequency stability curve from all the third frequency stability curves based on comparative analysis among the first frequency stability curve, the second frequency stability curve and all the third frequency stability curves, and using the first loop gain, the first time constant and the first scale coefficient as final loop parameters of the second-order digital phase-locked loop to finish the optimization of the performance of the time signal.
As a preferred scheme, the parameter selection module 2 specifically includes:
the first parameter selection unit is used for acquiring a fourth frequency stability curve of the plurality of time signals by combining a plurality of second time constants according to the first loop gain; obtaining the relation between the second time constant and the intersection sampling period based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fourth frequency stability curves, and determining the first time constant of the second-order digital phase-locked loop according to the relation between the second time constant and the sampling period; the second time constant and the fourth frequency stability curve are in one-to-one correspondence, and the sampling period of the intersection point is a sampling period corresponding to the intersection point of the first frequency stability curve and the second frequency stability curve;
a second parameter selection unit, configured to obtain, according to the first loop gain and the first time constant, a fifth frequency stability curve of the plurality of time signals by combining a plurality of second scaling coefficients; based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fifth frequency stability curves, selecting the second proportional coefficient corresponding to the fifth frequency stability curve meeting a third preset condition from all the fifth frequency stability curves as a first proportional coefficient of the second-order digital phase-locked loop; and the second proportionality coefficient corresponds to the fifth frequency stability curve one by one.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working process of the apparatus described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
The embodiment of the invention also provides a terminal, which comprises a processor, a memory and a computer program stored in the memory; wherein the computer program is executable by the processor to implement the second-order digital phase-locked loop based time signal performance optimization method.
An embodiment of the present invention further provides a computer-readable storage medium, where the computer-readable storage medium includes a stored computer program; when the computer program runs, the device on which the computer-readable storage medium is located is controlled to execute the time signal performance optimization method based on the second-order digital phase-locked loop according to the first embodiment.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
the invention provides a time signal performance optimization method and a time signal performance optimization device based on a second-order digital phase-locked loop, which adopt a method for adjusting loop parameters of the second-order digital phase-locked loop for multiple times, carry out multiple adjustment and analysis on a time constant and a proportionality coefficient of the second-order digital phase-locked loop, and complete the improvement of the tracking and locking performance of the second-order digital phase-locked loop, so that an output time signal can integrate the advantages of an input frequency source and a local crystal oscillator after a local crystal oscillator is driven by the input frequency source based on the second-order digital phase-locked loop, and finally a time signal which considers the long-term stability characteristic of the input frequency source and the short-term stability characteristic of the local crystal oscillator is obtained. Additionally, before the time constant is adjusted, the loop bandwidth of the second-order digital phase-locked loop is determined according to the comparison of the single-sideband phase noise curves of the input frequency source and the local crystal oscillator, the optimization of the single-sideband phase noise of the finally output time signal is realized, the contrast effect of the single-sideband phase noise on the frequency stability is avoided, the synchronous optimization of the time signal on the single-sideband phase noise and the frequency stability is further realized, and the optimization effect of the time signal performance is further improved.
The above-mentioned embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, and it should be understood that the above-mentioned embodiments are only examples of the present invention and are not intended to limit the scope of the present invention. It should be understood that any modifications, equivalents, improvements and the like, which come within the spirit and principle of the invention, may occur to those skilled in the art and are intended to be included within the scope of the invention.
Claims (9)
1. A time signal performance optimization method based on a second-order digital phase-locked loop is characterized by comprising the following steps:
acquiring a first single-sideband phase noise curve and a first frequency stability curve of an input frequency source and a second single-sideband phase noise curve and a second frequency stability curve of a local crystal oscillator, and determining a first loop gain of a second-order digital phase-locked loop based on the first single-sideband phase noise curve and the second single-sideband phase noise curve;
determining a first time constant of the second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve and the second frequency stability curve based on a preset parameter selection condition, and determining a first proportional coefficient of the second-order digital phase-locked loop by combining the first loop gain, the first time constant, the first frequency stability curve and the second frequency stability curve;
and adjusting final loop parameters of the second-order digital phase-locked loop according to the first loop gain, the first time constant and the first scale coefficient to optimize the performance of a time signal, wherein the time signal is output by the local crystal oscillator after being manipulated based on the input frequency source of the second-order digital phase-locked loop.
2. The method according to claim 1, wherein the final loop parameter of the second-order digital phase-locked loop is adjusted according to the first loop gain, the first time constant, and the first scaling factor to complete the optimization of the performance of the time signal, specifically:
adjusting the first time constant and the first proportional coefficient for a plurality of times respectively, and obtaining a third frequency stability curve of the time signal after each adjustment;
based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the third frequency stability curves, selecting the first loop gain, the first time constant and the first scale coefficient corresponding to the third frequency stability curve meeting a first preset condition from all the third frequency stability curves as final loop parameters of the second-order digital phase-locked loop, and completing the optimization of the performance of the time signal.
3. The method as claimed in claim 1, wherein the determining a first time constant of the second-order digital pll according to the first loop gain, the first frequency stability curve, and the second frequency stability curve based on a preset parameter selection condition specifically includes:
according to the first loop gain, combining a plurality of second time constants to obtain a plurality of fourth frequency stability curves of the time signals;
obtaining a relation between the second time constant and an intersection sampling period based on comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fourth frequency stability curves, and determining a first time constant of the second-order digital phase-locked loop according to the relation between the second time constant and the sampling period;
the second time constant and the fourth frequency stability curve are in one-to-one correspondence, and the intersection sampling period is a sampling period corresponding to an intersection of the first frequency stability curve and the second frequency stability curve.
4. The method according to claim 1, wherein the determining a first scaling factor of the second-order digital phase-locked loop according to the first loop gain and by combining the first loop gain, the first time constant, the first frequency stability curve, and the second frequency stability curve specifically comprises:
according to the first loop gain and the first time constant, combining a plurality of second proportionality coefficients to obtain a plurality of fifth frequency stability curves of the time signals;
based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fifth frequency stability curves, selecting the second proportionality coefficient corresponding to the fifth frequency stability curve meeting a second preset condition from all the fifth frequency stability curves as a first proportionality coefficient of the second-order digital phase-locked loop;
and the second proportionality coefficient corresponds to the fifth frequency stability curve one by one.
5. A time signal performance optimization device based on a second-order digital phase-locked loop is characterized by comprising:
the data acquisition module is used for acquiring a first single-sideband phase noise curve and a first frequency stability curve of an input frequency source and a second single-sideband phase noise curve and a second frequency stability curve of a local crystal oscillator, and determining a first loop gain of the second-order digital phase-locked loop based on the first single-sideband phase noise curve and the second single-sideband phase noise curve;
the parameter selection module is used for determining a first time constant of the second-order digital phase-locked loop according to the first loop gain, the first frequency stability curve and the second frequency stability curve based on a preset parameter selection condition, and determining a first proportional coefficient of the second-order digital phase-locked loop by combining the first loop gain, the first time constant, the first frequency stability curve and the second frequency stability curve;
and the performance optimization module is used for adjusting final loop parameters of the second-order digital phase-locked loop according to the first loop gain, the first time constant and the first scale coefficient to complete optimization of the performance of a time signal, wherein the time signal is output after the local crystal oscillator is manipulated by the second-order digital phase-locked loop.
6. The apparatus according to claim 5, wherein the performance optimization module specifically comprises:
the parameter adjusting unit is used for respectively adjusting the first time constant and the first proportional coefficient for a plurality of times and acquiring a third frequency stability curve of the time signal after each adjustment;
and the performance optimization unit is used for selecting the first loop gain, the first time constant and the first scale coefficient corresponding to the third frequency stability curve meeting a first preset condition from all the third frequency stability curves based on the contrastive analysis among the first frequency stability curve, the second frequency stability curve and all the third frequency stability curves, and using the first loop gain, the first time constant and the first scale coefficient as final loop parameters of the second-order digital phase-locked loop to complete the optimization of the performance of the time signal.
7. The apparatus for optimizing time signal performance based on a second-order digital phase-locked loop according to claim 5, wherein the parameter selection module specifically comprises:
the first parameter selection unit is used for acquiring a fourth frequency stability curve of the plurality of time signals by combining a plurality of second time constants according to the first loop gain; obtaining the relation between the second time constant and the intersection sampling period based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fourth frequency stability curves, and determining the first time constant of the second-order digital phase-locked loop according to the relation between the second time constant and the sampling period; the second time constant and the fourth frequency stability curve are in one-to-one correspondence, and the sampling period of the intersection point is a sampling period corresponding to the intersection point of the first frequency stability curve and the second frequency stability curve;
a second parameter selection unit, configured to obtain, according to the first loop gain and the first time constant, a fifth frequency stability curve of the plurality of time signals by combining a plurality of second scaling factors; based on the comparative analysis among the first frequency stability curve, the second frequency stability curve and all the fifth frequency stability curves, selecting the second proportional coefficient corresponding to the fifth frequency stability curve meeting a third preset condition from all the fifth frequency stability curves as a first proportional coefficient of the second-order digital phase-locked loop; and the second proportionality coefficient corresponds to the fifth frequency stability curve one by one.
8. A terminal comprising a processor, a memory, and a computer program stored in the memory; wherein the computer program is executable by the processor to implement the method for time signal performance optimization based on a second order digital phase locked loop according to any one of claims 1 to 4.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a stored computer program; wherein the computer program controls an apparatus on which the computer readable storage medium is executed to perform the method for optimizing time signal performance based on a second-order digital phase-locked loop according to any one of claims 1 to 4.
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