CN115048332A - Data transmission method, electronic system and storage medium - Google Patents
Data transmission method, electronic system and storage medium Download PDFInfo
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- CN115048332A CN115048332A CN202111050869.3A CN202111050869A CN115048332A CN 115048332 A CN115048332 A CN 115048332A CN 202111050869 A CN202111050869 A CN 202111050869A CN 115048332 A CN115048332 A CN 115048332A
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Abstract
The application is applicable to the technical field of processors, and provides a data transmission method, an electronic system and a storage medium, wherein the method comprises the following steps: when data needing to be transmitted outwards exist in the second kernel, the second kernel packages the first data to be transmitted to obtain a data message corresponding to the first data; when the destination address of the data message comprises a second processor, the second kernel sends the data message to the first kernel; the first kernel sends a data message to the second processor through the external bus; according to the method and the device, the second kernel packages the data to be transmitted into the data message matched with the type of the external bus, and the first kernel can send the data message to the external bus without processing the data message, so that the data transmission efficiency is improved.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to a data transmission method, an electronic system, and a storage medium.
Background
A multi-core processor refers to the integration of multiple processor cores on a single chip. The multi-core processor can provide higher processor performance and more effective power utilization rate under lower main frequency, and occupies smaller physical space, so the multi-core processor is widely applied to various fields.
For multi-core processors, efficient data transfer is one of the indicators that evaluate processor performance. At present, when data is transmitted between processor cores, a slave core needs to process transmitted data for the first time, and then transmits the data processed for the first time to a master core. For data which needs to be transmitted to other processors, the main kernel needs to analyze the data after the first processing, and then transmit the data obtained by analysis to other processors after the second processing. According to the inter-processor data transmission method, the main kernel needs to process the data twice, so that the data transmission efficiency is low.
Disclosure of Invention
The embodiment of the application provides a data transmission method, an electronic system and a storage medium, which can solve the problem of low data transmission efficiency.
In a first aspect, an embodiment of the present application provides a data transmission method, which is applied to an electronic device, where the electronic device includes a first processor and a second processor, the first processor and the second processor are connected through an external bus, the first processor includes a first core and a second core, the first core is connected to the external bus, and the method includes:
the second kernel packages first data to be transmitted to obtain a data message corresponding to the first data, wherein the format of the data message is determined according to the type of the external bus;
when the destination address of the data message comprises the second processor, the second kernel sends the data message to the first kernel;
and the first kernel sends the data message to the second processor through the external bus.
In a second aspect, an embodiment of the present application provides an electronic system, including: a memory, a first processor, a second processor and a computer program stored in the memory and executable on the first processor, the first processor implementing the data transmission method of any one of the above first aspects when executing the computer program.
In a third aspect, embodiments of the present application provide a vehicle including an electronic system as described in the second aspect above.
In a fourth aspect, the present application provides a computer-readable storage medium, where a computer program is stored, and the computer program, when executed by a processor, implements the data transmission method according to any one of the first aspect.
In a fifth aspect, an embodiment of the present application provides a computer program product, which, when run on a terminal device, causes the terminal device to execute the data transmission method according to any one of the above first aspects.
Compared with the prior art, the embodiment of the first aspect of the application has the following beneficial effects: the second kernel needs to package the data to be transmitted into a data message matched with the type of the external bus; because the first kernel is a kernel connected with the external bus, when the destination address of the data message includes the second processor, the second kernel needs to send the data message to the first kernel, so that the first kernel transmits the data message to the second processor through the external bus; compared with the process that the main kernel needs to analyze and package data to be transmitted into a data message which can be transmitted by an external bus in the prior art, the second kernel directly packages the data to be transmitted into the data message matched with the type of the external bus, and the first kernel can send the data message to the external bus without processing the data message, so that the efficiency of data transmission is improved.
It is understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings may be obtained according to these drawings without inventive labor.
FIG. 1 is a schematic diagram of a plurality of core processors provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of an electronic system according to an embodiment of the present application;
fig. 3 is a schematic flowchart of a data transmission method according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a method for generating a data packet according to an embodiment of the present application;
FIG. 5 is a block diagram of a first processor according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an electronic system according to another embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.
A processor (CPU) is a final execution Unit for information Processing and program execution, and serves as an operation and control core of a computer system. There are cores in a processor, which are digital processing cores, used to perform all computations, accept/store commands, process data, etc. With the increasing amount of data to be processed, processors with multi-core cooperation have appeared in order to increase the processing speed of the processors.
By way of example, as shown in fig. 1, the processor in fig. 1 includes a plurality of cores, which are core a, core B, core C, and the like. The plurality of cores in the processor perform data transmission through Inter-process communication (IPC).
At present, in an electronic system, a plurality of processors are often required to cooperate to complete data processing. By way of example, if an electronic system includes a first processor A and a second processor B. The first processor a includes a master core a1 and a slave core a2, the master core a1 being a core connected to an external bus.
The primary core a1 includes a first application module, a first data processing module, and a first transmission module. The slave core a2 includes a second application module and a second data processing module.
When the core a2 needs to send data to the second processor, the second application module sends the data to be transmitted to the second data processing module. And the second data module carries out structural body serialization on the data to be transmitted to obtain the first data. The second data module transmits the first data to the first data processing module of the master core a 1. The first data processing module carries out structural body deserialization on the first data to obtain data to be transmitted. When data to be transmitted needs to be sent to the second processor, the first data processing module sends the data to be transmitted to the first transmission module. The first transmission module packages the data to be transmitted into a message matched with the external bus, then sends the message to the external bus, and transmits the message to the second processor through the external bus. When the data to be transmitted does not need to be sent to the second processor, the first data processing module sends the data to be transmitted to the first application module.
As can be seen from the above analysis, the main core needs to deserialize the received data, package the deserialized data, and transmit the packaged data to the external bus. The main kernel needs to process twice to transmit data outwards, the data processing process is complex, and the data processing time is long. In order to improve the data processing speed, the data transmission method can reduce the data processing process and improve the data processing speed.
Fig. 2 is an electronic system provided in an embodiment of the present application, where the electronic system includes a first processor and a second processor. The first processor and the second processor are connected by an external bus. The first processor includes a first core and a second core, the first core coupled to the external bus, the second core not coupled to the external bus.
In this embodiment, the first processor may include at least one first core therein. One or more second cores may be included in the first processor.
In this embodiment, the external bus may be a CAN (controller Area network) bus, a CAN/LIN bus, an I2C bus, or an SCI bus, etc.
The data transmission method according to the embodiment of the present application is described in detail below with reference to fig. 2.
Fig. 3 shows a schematic flow chart of a data transmission method provided by the present application, and with reference to fig. 3, the method is described in detail as follows:
s101, the second kernel packages the first data to be transmitted to obtain a data message corresponding to the first data.
In this embodiment, the first data may be one data or a plurality of data. The first data may be application data.
In this embodiment, in order to enable the first data to be matched with the external bus and improve data transmission efficiency, when the second core processes the first data, the second core needs to encapsulate the first data according to the type of the external bus to obtain a data packet matched with the external bus.
As shown in fig. 4, in a possible implementation manner, if the external bus is a CAN bus, the implementation process of step S101 may include:
and S1011, the second kernel carries out serialization processing on the first data to obtain a serialized data packet.
In the present embodiment, the first data is subjected to the serialization processing, that is, the signal arrangement of the first data. Specifically, the serialization process is to arrange a plurality of signals in a specific format, in this case, a plurality of first data. One particular format is determined in the present application based on the serialized format of the messages transmitted by the external bus. The serialized format of the serialized data packet is consistent with the serialized format of the message transmitted by the external bus.
By way of example, the CAN serialization format is bitwise ordered. If 10 signals (with different signal lengths) need to be serialized, the signal 1 (with the length of 10 bits) is arranged at the 1 st bit to the 10 th bit, the signal 2 (with the length of 5 bits) is arranged at the 11 th bit to the 15 th bit, the signals are sequentially arranged according to the above mode, and the rest bits which are not arranged are all filled with 0, so that the serialized data packet is obtained.
S1012, obtaining an identifier corresponding to the first data based on the data content of the first data.
In this embodiment, different data contents correspond to different identifiers, so that each piece of first data uniquely corresponds to one identifier, and the content of the identifier can be set as required.
By way of example, if the first data is vehicle speed data, the identifier to which the first data corresponds may be Y. If the first data is the vehicle window data, the identifier corresponding to the first data may be X.
For example, if the identifier of the first data is 0x001, the identifier of the PDU file is 0x001, that is, the identifier of the data packet is 0x 001.
And S1013, the second kernel packages the serialized data packets and the identifiers of the first data to obtain PDU files, wherein the PDU files are the data messages.
In this embodiment, the identifier of the first Data may be an identifier of a pdu (protocol Data unit) file, that is, an identifier of a Data packet. The data packet includes a serialized data packet and an identifier.
In this embodiment, the PDU format file is a file format suitable for CAN bus transmission. The first data is converted to a PDU file for subsequent encapsulation and transmission on the external bus.
In this embodiment, in order to facilitate data transmission, when the identifier of the first data is set, the format of the identifier of the first data may be set according to the format of the identifier required for the external bus transmission packet. Because the format of the identifier of the first data is the same as that of the identifier required by the external bus transmission message, the format of the identifier of the data message obtained according to the identifier of the first data is the same as that of the identifier required by the external bus transmission message. The format of the identifier of the data message is set to be the format of the identifier required by the external bus transmission message, so that the data processing process can be reduced, the data packaging process is simpler and more convenient, and the data processing efficiency is improved.
In this embodiment, the length of the data packet matches the type of the external bus, for example, the CAN bus may be set to 64 bytes at maximum, and the length of the data packet may be set to 64 bytes. The data message may also include a message length, etc.
Optionally, in order to ensure completeness of data transmission, when the PDU file is encapsulated, a check code of the serialized data packet may be generated first, the check code is stored in the serialized data packet, and then the second core encapsulates the serialized data packet in which the check code is stored and the identifier of the first data, so as to obtain the PDU file. In this embodiment, the Check code may include a Cyclic Redundancy Check (Cyclic Redundancy Check-CRC) value and/or a Counter value.
And S102, when the destination address of the data message comprises the second processor, the second kernel sends the data message to the first kernel.
In this embodiment, after the second kernel obtains the data packet, the destination address of the data packet may be determined by the identifier of the data packet, and if the destination address includes the second processor, the data packet is determined to be a data packet that needs to be sent to the outside of the first processor. An identifier may correspond to one or more destination addresses.
By way of example, if the identifier is 0x001, the destination address corresponding to the identifier may include the second processor and the first core, etc.
In this embodiment, because the first core is connected to the external bus, the second core is not connected to the external bus, and the second core cannot communicate with the outside, when the second core needs to send a data packet to the second processor, the second core needs to send the data packet to the first core first, and send the data packet to the outside through the first core.
And S103, the first kernel sends the data message to the second processor through the external bus.
In this embodiment, after the first core receives the data packet sent by the second core, the destination address of the data packet may be determined by the identifier of the data packet. If the first kernel determines that the destination address of the data message comprises the second processor, the first kernel can not process the data message because the serialization format of the data message is consistent with the serialization format of the external bus message, and the first kernel can directly send the data message to the external bus and send the data message to the second processor through the external bus. Based on the design, if the second core needs to send data to the first core, the second core can also convert the data to be sent into a data message and send the data message to the first core, so that the consistency of inter-core communication and inter-processor communication is ensured.
In this embodiment, data transmission may be performed between the second core and the first core in an IPC communication manner. The IPC communication mode adopts a mode of sharing a memory to carry out data transmission. Specifically, the second kernel stores the data packet in the shared memory, and the first kernel obtains the data packet from the shared memory.
In the embodiment of the application, the second kernel needs to package the data to be transmitted into a data message matched with the type of the external bus; when the destination address of the data message comprises the second processor, the second kernel needs to send the data message to the first kernel so that the first kernel can transmit the data message to the second processor through the external bus; compared with the process that the main kernel needs to analyze and package data to be transmitted into a data message which can be transmitted by an external bus in the prior art, the second kernel packages the data to be transmitted into the data message which is matched with the type of the external bus, and the first kernel can send the data message to the external bus without processing the data message, so that the process of data processing is reduced, and the efficiency of data transmission is improved. The data unpacking method and the data unpacking device reduce the unpacking times of the data and reduce the error rate of data transmission.
In a possible implementation manner, after step S101, the method may further include:
s201, the second kernel determines a destination address corresponding to the identifier of the data message, and takes the destination address corresponding to the identifier as the destination address of the data message.
In this embodiment, the second kernel may search for a destination address corresponding to the identifier of the data packet, so as to determine the destination address of the data packet.
S202, if the destination address comprises the first kernel, the second kernel sends a data message to the first kernel.
In this embodiment, when the second core determines that the data packet needs to be sent to the first core, it indicates that the data packet is data required by the first core, and the second core needs to send the data packet to the first core.
S203, the first kernel receives the data message sent by the second kernel, and the first kernel analyzes the data message to obtain the first data.
In this embodiment, after receiving the data packet, the first core determines the destination address according to the identifier of the data packet. And if the destination address comprises the first kernel, determining that the first kernel needs to unpack the data message to obtain the first data.
In this embodiment, when the first kernel parses the data packet, if the data packet includes the check code, the first kernel may calculate a CRC value and/or a Counter value of the data packet when unpacking the data packet. And determining the integrity of the data in the data message received by the first core by comparing the CRC value and/or the Counter value calculated by the first core with the CRC value and/or the Counter value in the data message.
Specifically, when the check code includes a CRC value, if the CRC value calculated by the first kernel is the same as the CRC value in the data packet, it is determined that the first data obtained by analyzing the data packet is complete data; otherwise, frame loss is determined during transmission, and the first data obtained through data message analysis is incomplete.
Specifically, when the check code includes a Counter value, if the Counter value calculated by the first kernel is the same as the Counter value in the data packet, it is determined that the first data obtained through the data packet analysis is complete data; otherwise, frame loss is determined during transmission, and the first data obtained through data message analysis is incomplete.
And S204, if the destination address comprises the third kernel, the second kernel sends the data message to the third kernel.
In this embodiment, the third core is another core of the first processor except the first core and the second core. The third core is not connected to the external bus. The third core may implement the data transmission method implemented in the second core.
And S205, the third kernel receives the data message sent by the second kernel, and the third kernel analyzes the data message to obtain the first data.
In this embodiment, after receiving the data packet, the third core determines the destination address according to the identifier of the data packet. And if the destination address comprises the third kernel, determining that the third kernel needs to unpack the data message to obtain the first data. Specifically, the process of parsing the data message by the third core is the same as the process of parsing the data message by the first core, and please refer to the process of parsing the data message by the first core, which is not described herein again.
In the embodiment of the application, when the data message does not need to be sent to the second processor, the inter-core communication in the first processor is also carried out in the form of the data message, so that the inter-core communication and the inter-processor communication can be kept consistent, the data processing amount of the processor is reduced, and the data transmission speed is improved.
In a possible implementation manner, if data to be sent to the second processor exists in the first core, the first core encapsulates the data to be sent into a data packet, and then sends the data packet to the second processor through the external bus.
If the first kernel has data to be sent to the second kernel, the first kernel packages the data to be sent into a data message, and then sends the data message to the second kernel.
In one possible implementation, the first kernel and the second kernel may be kernels based on an automobile Open system architecture (AUTomotive Open architecture-AUTomotive).
As shown in fig. 5, in one possible implementation, the second core includes: a first COM module and a first PDU Router module. The first COM module comprises a first application unit, a first RTE unit and a first COM unit. The first application unit is used for obtaining first data to be transmitted. The first RTE unit has a function of forwarding data. The first COM unit encapsulates the first data. The first COM unit is also used for analyzing the received data message. The first application unit belongs to the first application layer, the first RTE unit belongs to the first RTE layer, and the first COM unit belongs to the first COM layer.
The first PDU Router module comprises a first PDU Router unit and a first IPC driving unit. The first PDU Router unit obtains the destination address of the data message according to the identifier of the data message, and then allocates a corresponding route according to the destination address of the data message. The first IPC driver unit stores a driver for IPC, which may be stored in a CDD file. The first PDU Router unit belongs to the first PDU Router layer, and the first IPC driving unit belongs to the first IPC driving layer.
The first core includes: the second COM module, the second PDU Router module and the bus communication module. The second COM module includes a second application unit, a second RTE unit, and a second COM unit. The second COM unit is used for analyzing the data message. The second COM unit is also used for packaging data to be transmitted. The second application unit belongs to a second application layer, the second RTE unit belongs to a second RTE layer, and the second COM unit belongs to a second COM layer.
The second PDU Router module comprises a second PDU Router unit and a second IPC driving unit. The bus communication module comprises a bus interface unit and a bus driving unit. When the external bus is a CAN bus, the bus interface unit is a CAN IF unit, and the bus driving unit is a CAN Driver unit. The second PDU Router unit belongs to a second PDU Router layer, and the second IPC driving unit belongs to a second IPC driving layer. The bus interface unit belongs to a bus interface layer, and the bus driving unit belongs to a bus driving layer.
The first processor can also comprise a bus data transceiver module, the bus data transceiver module is connected with an external bus, and the bus data transceiver module is also connected with the bus driving unit. When the external bus is a CAN bus, the bus data transceiver module is a CAN Transceiver module. The bus data transceiving module belongs to a bus data transceiving layer.
The first processor comprises an IPC communication module, and the second PDU Router module in the first kernel is connected with the first PDU Router module in the second kernel through the IPC communication module.
In this embodiment, the first application unit in the second kernel transmits the first data to the first COM unit through the first RTE unit. And the first COM unit packages the first data to be transmitted to obtain a data message corresponding to the first data. And the first COM unit sends the data message to a first PDU Router unit.
And the first PDU Router unit obtains the destination address of the data message according to the identifier of the data message. And when the destination address of the data message comprises the second processor and/or the first kernel, the second kernel sends the data message to the first IPC driving unit through the first PDU Router unit. The first IPC driving unit sends a data message to the IPC communication module.
The first kernel acquires the data message from the IPC communication module through the second IPC driving unit. And the second IPC driving unit transmits the data message to a second PDU Router unit. And the second PDU Router unit obtains the destination address of the data message through the identifier of the data message. And if the destination address comprises the second processor, the second PDU Router unit sends the data message to the bus interface layer. And the bus interface unit sends the data message to the bus driving unit. The bus driving unit packages the data message into a data frame and then transmits the data frame to the bus data receiving and transmitting unit. The bus data receiving and sending unit sends the data message to an external bus.
And if the destination address comprises the first kernel, the second PDU Router unit sends the data message to the second COM unit. And after receiving the data message, the second COM unit analyzes the data message to obtain first data. The second COM unit sends the first data to the second RTE unit. And the second RTE unit sends the data message to the second application unit.
In a possible implementation manner, if there is data to be transmitted in the second application unit, the second application unit transmits the data to be transmitted to the second COM unit through the second RTE unit, and the second COM unit encapsulates the data to be transmitted into a data packet and sends the data packet to the second PDU Router unit.
The second PDU Router unit obtains the destination address through the identifier of the data message, and if the destination address comprises the second processor, the second PDU Router unit sends the data message to the external bus through the bus communication module. And if the destination address comprises the second kernel, the second PDU Router unit sends the data message to the IPC communication module through the second IPC driving unit. And the first PDU Router unit in the second kernel transmits the data message to the first COM unit. And the first COM unit analyzes the data message to obtain data to be transmitted. The first COM unit sends data to be transmitted to the first RTE unit, and the first RTE unit sends the data to be transmitted to the first application unit.
In a possible implementation manner, the first core may obtain the data packet from the external bus through the bus communication module, and transmit the data packet to the second PDU Router unit, and the second PDU Router unit transmits the data packet through the destination address. And if the second PDU Router unit determines that the identifier of the data message comprises the first kernel, the second PDU Router unit sends the data message to the second COM unit for analysis. And if the second PDU Router unit determines that the identifier of the data message comprises the second kernel, the second PDU Router unit sends the data message to the second IPC driving unit, and the second IPC driving unit sends the data message to the first IPC driving unit through the IPC communication module. And the first IPC driving unit transmits the data message to the first COM unit through the first PDU Router unit, and the first COM unit analyzes the data message.
In the embodiment of the application, the first kernel and the second kernel are simple in structure, the simple structure can save the space of the kernels, and meanwhile, the simple structure can enable the kernels to process data faster.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
The embodiment of the present application further provides an electronic system, and referring to fig. 6, the electronic system 400 may include: a first processor 410, a memory 420, and a computer program stored in the memory 420 and operable on the first processor 410, wherein the first processor 410, when executing the computer program, implements the steps of any of the above-mentioned method embodiments, for example, the steps S101 to S103 in the embodiment shown in fig. 3.
Illustratively, the computer program may be divided into one or more modules/units, which are stored in the memory 420 and executed by the first processor 410 to accomplish the present application. The one or more modules/units may be a series of computer program segments capable of performing certain functions, the program segments describing the execution of the computer program in the electronic system 400.
Those skilled in the art will appreciate that fig. 6 is merely an example of an electronic system and is not limiting of electronic systems and may include more or fewer components than shown, or some components in combination, or different components such as input output devices, network access devices, buses, etc.
The first Processor 410 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 420 may be an internal storage unit of the electronic system, or an external storage device of the electronic system, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. The memory 420 is used for storing the computer programs and other programs and data required by the electronic system. The memory 420 may also be used to temporarily store data that has been output or is to be output.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
The data transmission method provided by the embodiment of the application can be applied to terminal equipment such as automobiles, computers, tablet computers, notebook computers, netbooks and Personal Digital Assistants (PDAs), and the embodiment of the application does not limit the specific types of the terminal equipment at all. In the case of application to an automobile, the processor may be an ECU.
The embodiment of the application also provides a vehicle comprising the electronic system.
An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the embodiments of the data transmission method described above.
The embodiment of the present application provides a computer program product, which when running on a mobile terminal, enables the mobile terminal to implement the steps in the embodiments of the data transmission method when executed.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. The data transmission method is applied to an electronic system, wherein the electronic system comprises a first processor and a second processor, the first processor and the second processor are connected through an external bus, the first processor comprises a first kernel and a second kernel, and the first kernel is connected with the external bus;
the method comprises the following steps:
the second kernel packages first data to be transmitted to obtain a data message corresponding to the first data, wherein the format of the data message is determined according to the type of the external bus;
when the destination address of the data message comprises the second processor, the second kernel sends the data message to the first kernel;
and the first kernel sends the data message to the second processor through the external bus.
2. The data transmission method according to claim 1, wherein the external bus is a CAN bus;
the method for encapsulating first data to be transmitted by the second core to obtain a data packet corresponding to the first data includes:
the second kernel carries out serialization processing on the first data to obtain a serialized data packet, wherein the serialized format of the serialized data packet is the same as the serialized format of the message transmitted by the external bus;
obtaining an identifier corresponding to the first data based on the data content of the first data;
and the second kernel packages the serialized data packet and the identifier of the first data to obtain a PDU file, wherein the PDU file is the data message, and the identifier of the data message is the identifier of the first data.
3. The data transmission method of claim 2, wherein the second kernel encapsulates the serialized data packet and the identifier of the first data to obtain a PDU file, comprising:
generating a check code of the serialized data packet to obtain the serialized data packet containing the check code;
and the second kernel encapsulates the serialized data packet containing the check code and the identifier of the first data to obtain the PDU file.
4. The data transmission method according to claim 1, wherein after obtaining the data packet corresponding to the first data, the method includes:
the second kernel determines a destination address corresponding to an identifier of the data message, and takes the destination address corresponding to the identifier as the destination address of the data message;
if the destination address comprises the first kernel, the second kernel sends the data message to the first kernel;
and the first kernel receives the data message sent by the second kernel, and the first kernel analyzes the data message to obtain the first data.
5. The data transmission method according to claim 1, wherein after obtaining the data packet corresponding to the first data, the method includes:
if the destination address comprises a third kernel, the second kernel sends the data message to the third kernel, wherein the third kernel is other kernels except the first kernel and the second kernel in the first processor;
and the third kernel receives the data message sent by the second kernel, and the third kernel analyzes the data message to obtain the first data.
6. The data transfer method of claim 1, the second core comprising: the first core comprises a second PDU Router module and a bus communication module, and the method comprises the following steps:
the second kernel packages the first data to be transmitted through the first COM module to obtain a data message corresponding to the first data;
when the destination address of the data message comprises the second processor, the second core sends the data message to the second PDU Router module of the first core through the first PDU Router module;
and the second PDU Router module in the first core sends the data message to the external bus through the bus communication module, so that the data message is sent to the second processor through the external bus.
7. The data transmission method of claim 6, wherein the first processor includes an IPC communication module, the second PDU Router module in the first core and the first PDU Router module in the second core are connected through the IPC communication module;
the sending, by the second core, the data packet to the second PDU Router module of the first core through the first PDU Router module includes:
and the first PDU Router module in the second kernel sends the data message to the second PDU Router module through the IPC communication module.
8. The data transmission method of claim 4, wherein the first kernel comprises a second COM module;
the analyzing the data message by the first kernel to obtain the first data includes:
and the first kernel analyzes the data message through the second COM module to obtain the first data.
9. An electronic system comprising a memory, a first processor, a second processor and a computer program stored in said memory and capable of running on said first processor, characterized in that said first processor implements the data transmission method according to any one of claims 1 to 8 when executing said computer program.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the data transmission method according to any one of claims 1 to 8.
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| CN202111050869.3A CN115048332A (en) | 2021-09-08 | 2021-09-08 | Data transmission method, electronic system and storage medium |
| PCT/CN2022/117612 WO2023036194A1 (en) | 2021-09-08 | 2022-09-07 | Data transmission method, electronic system, and storage medium |
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| CN107547508B (en) * | 2017-06-29 | 2021-07-30 | 新华三信息安全技术有限公司 | Message sending and receiving method, device and network equipment |
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