CN115048130A - FPGA-based firmware program reliable online upgrading system and method - Google Patents
FPGA-based firmware program reliable online upgrading system and method Download PDFInfo
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Abstract
The invention relates to a reliable online upgrading system and method for firmware programs based on an FPGA (field programmable gate array), belonging to the field of firmware upgrading. The invention can ensure that the firmware upgrading data can be completely and correctly upgraded to the firmware memory FLASH; firstly, the software architecture needs to carry out integrity check on a received upgrade data packet; the MAC interface logic of the logic architecture needs to carry out integrity check on the received data packet; a format analysis module of the logic architecture carries out format correctness verification on the received data packet; and (4) a corresponding processing mechanism of the software architecture firmware upgrading program to the response message carrying the abnormal mark. The invention provides a reliable online upgrading method of firmware programs based on an FPGA. The flexibility of the online upgrading method is ensured, the remote program updating can be realized, the operation of the matched interface is simple, the use is flexible, and the risk of incapability of starting due to updating failure is avoided.
Description
Technical Field
The invention belongs to the field of firmware upgrading, and particularly relates to a reliable online upgrading system and method for firmware programs based on an FPGA.
Background
Firmware program upgrading methods based on FPGA are divided into off-line upgrading and on-line upgrading. Off-line upgrading generally adopts an FPGA writer to update programs; on-line upgrades typically implement program updates through software and hardware coordination.
The traditional firmware program offline updating method adopts an FPGA writer to update programs, is simple, but is relatively complex to operate for non-technical personnel, and cannot realize remote program updating;
the traditional firmware program online upgrading method generally realizes program updating through software and hardware matching, is more flexible, can realize remote program updating, but has the risk of updating failure, and once the updating failure occurs, the FPGA cannot be started.
Disclosure of Invention
Technical problem to be solved
The invention provides a reliable on-line upgrading system and method of a firmware program based on an FPGA (field programmable gate array), and aims to solve the problems that the traditional firmware program off-line upgrading method is relatively complex in operation and cannot realize remote program updating, the traditional firmware program on-line upgrading has the risk of updating failure, and the FPGA cannot be started once the updating failure occurs.
(II) technical scheme
In order to solve the technical problems, the invention provides a reliable online upgrading system for firmware programs based on an FPGA (field programmable gate array), which comprises a software architecture and a logic architecture, wherein the software architecture comprises a firmware updating application program and a network interface distribution and convergence module, and the logic architecture comprises a network interface MAC (media access control) module, a data receiving module, a format analysis module, a data sending module, a format encapsulation module, a FLASH control module and a configuration interface IP (Internet protocol) module;
the firmware updating application program is used for receiving the updating data, dividing the data packet and controlling the updating process, and is connected to the internet access distribution convergence module;
the network port distribution and convergence module comprises a distribution function and a convergence function, and the convergence function is used for receiving a data packet of an upper application program and sending the data packet to the logic architecture through lower hardware; the distribution function is used for receiving the data packet from the hardware of the lower-layer logic architecture, analyzing the data packet and distributing the data packet according to the category of the analysis result;
the network port MAC module is used for receiving and sending a link layer network data packet, the downlink direction of the data packet is from a software architecture to a logic architecture, and the logic architecture needs to realize frame synchronization, frame interval check and FCS check of the link layer data packet; the data packet uplink direction, namely the data packet is from a logic architecture to a software architecture, and the logic architecture needs to realize FCS calculation of a link layer network data packet, addition of a data packet frame head and a data packet tail and control of a frame gap;
the data receiving module is connected with the network port MAC module and is used for temporary storage of downlink data packets and clock domain crossing data transmission from a network port clock domain to a system clock domain;
the data sending module is connected with the network port MAC module and is used for temporary storage of an uplink data packet and clock domain crossing data transmission from a system clock domain to a network port clock domain;
the format analysis module is connected with the data receiving module and is used for analyzing the format of the downlink data packet, extracting key information, configuring the cache of data and initiating requests of firmware erasing, firmware writing, firmware reading and the like to the FLASH control module according to the type of the key information;
the format encapsulation module is connected with the data sending module and is used for encapsulating the format of the uplink data packet;
the FLASH control module is connected with the format parsing module and the format packaging module and is used for controlling erasing, writing and reading of the FLASH chip through the configuration interface IP; when the FLASH control module receives a firmware erasing request of the format analysis module, the FLASH control module initiates an erasing operation of the FLASH, generates an erasing completion signal after the FLASH is erased, sends the erasing completion signal to the format packaging module, and finally sends the erasing completion signal to a firmware updating application program of the software architecture; when receiving a firmware writing request, the FLASH control module initiates writing operation of FLASH, generates a writing completion signal after writing data into the FLASH is completed, sends the writing completion signal to the format packaging module, and finally sends the writing completion signal to a firmware updating application program of a software framework; when receiving a firmware reading request, the FLASH control module initiates a FLASH reading operation, generates a reading completion signal after the FLASH reading is completed, sends the reading completion signal and the read data to the format packaging module, and finally sends the reading completion signal to a firmware updating application program of the software architecture;
the configuration interface IP module is connected with the FLASH control module and the FPGA loading FLASH and is used for data communication between the internal logic and the FPGA loading FLASH.
Furthermore, the software architecture also comprises other application programs, the other application programs are designed according to the function definition, and communicate with the logic architecture through the internet access distribution convergence module, wherein the communication comprises register configuration, table item configuration and audit messages.
Further, the processing procedure of the firmware updating application program comprises the following steps:
s11, the firmware updating application program firstly receives the complete updating data and verifies the integrity of the data;
s12, after the integrity verification is passed, dividing the updating data into a plurality of data packets with 1KB byte, and sending the data packets to the logic architecture in sequence;
s13, the firmware updating application program firstly sends a firmware erasing command, and starts to send data to the logic architecture after the erasing is finished;
s14, after the firmware updating application program sends out a data packet each time, the response message after the data packet is written into the FLASH is waited;
s15, after receiving the response message of completing writing the data packet, the firmware updating application program starts to send the next packet of data;
and S16, when the firmware updating application program finishes sending a data packet, the response packet is not received within the specified time, or the received response packet carries abnormal updating information, the firmware updating application program considers that the data packet transmission process is abnormal, and the current updating is immediately stopped.
Further, the format of the format encapsulation module encapsulation comprises a link layer header, a type, a state and a load; wherein, the state is 0, which indicates normal return, otherwise, the state is abnormal return; the payload is filled with valid data only when the firmware reads the command, otherwise 0 is filled.
Furthermore, if the format analysis module analyzes that the data format is wrong or abnormal, the data packet is directly discarded, a format abnormal signal is generated and sent to the format packaging module, and finally the data packet is sent to a firmware updating application program of the software architecture.
The invention also provides a reliable online upgrading method of the firmware program based on the FPGA, which comprises the following steps:
the first step is as follows: the software architecture firmware updating application program receives the updating data until the data reception is completed;
the second step is that: the software architecture firmware updating application program carries out integrity verification on the complete firmware updating data packet, carries out next operation on the data packet passing the verification, and returns an error if not;
the third step: a software architecture firmware updating application program divides a data packet into a plurality of data packets with 1KB byte for complete firmware and performs message encapsulation;
the fourth step: the software architecture firmware updating application program sends a firmware erasing command to the logic architecture, and the next operation is carried out after the erasing is finished;
the fifth step: after the software architecture firmware updating application program sends a data packet to the logic architecture, a response message of the data packet written into the FLASH is waited;
and a sixth step: the network port MAC module of the logic structure carries out frame synchronization, frame interval inspection and FCS (field control protocol) inspection on the data packet in the downlink direction; the verification is carried out to the next step through the flow;
the seventh step: the format analysis module of the logic architecture finishes the extraction of the key information and initiates erasing, writing and reading requests to the FLASH control module according to the type of the key information;
eighth step: the FLASH control module of the logic framework performs corresponding FLASH operations according to the types of the erasing, writing and reading requests, and returns a normal completion response packet through the format encapsulation module after the operations are completed;
the ninth step: the format packaging module of the logic framework completes the packaging of the response packet according to the request types of the format analysis module and the FLASH control module and outputs the response packet to the network port MAC module through the data sending module;
the tenth step: the network port MAC module of the logic architecture processes the uplink direction data packet and then sends the processed uplink direction data packet to the software architecture through the network port;
the eleventh step: the network port distribution and convergence module of the software architecture analyzes the corresponding answer data packet and distributes the answer data packet to a corresponding application program according to the answer category;
the twelfth step: if the response message is not received after timeout or the response message carrying abnormal information is received, skipping to the fourth step to restart the firmware upgrading; if the normal response message is received and the data packet is not completely transmitted, jumping to the fifth step, otherwise, jumping to the next step;
the thirteenth step: and finishing the on-line upgrading of the firmware program.
Furthermore, the software architecture also comprises other application programs, the other application programs are designed according to the function definition, and communicate with the logic architecture through the internet access distribution convergence module, wherein the communication comprises register configuration, table item configuration and audit messages.
Furthermore, in the seventh step, if the format analysis module analyzes that the data format is wrong or abnormal, the data packet is directly discarded, a format abnormal signal is generated and sent to the format packaging module, and finally the data packet is sent to the firmware updating application program of the software architecture.
Further, the format of the package of the response packet in the ninth step includes: link layer head, type, status and load; wherein, the state is 0, which indicates normal return, otherwise, the state is abnormal return; the payload is filled with valid data only when the firmware reads the command, otherwise 0 is filled.
Further, the packet processing in the tenth step includes FCS calculation, adding a header and a trailer to the packet, and controlling the inter-frame gap.
(III) advantageous effects
The invention provides a reliable on-line upgrading system and method of firmware program based on FPGA, the invention can ensure that firmware upgrading data can be completely and correctly upgraded to a firmware memory FLASH; firstly, the software architecture needs to carry out integrity check on a received upgrade data packet; the MAC interface logic of the logic architecture needs to carry out integrity check on the received data packet; a format analysis module of the logic architecture carries out format correctness verification on the received data packet; and (4) a corresponding processing mechanism of the software architecture firmware upgrading program to the response message carrying the abnormal mark. The invention provides a reliable online upgrading method of firmware programs based on an FPGA. The flexibility of the online upgrading method is ensured, the remote program can be updated, the operation of the matched interface is simple, the use is flexible, and the risk of incapability of starting due to updating failure is avoided.
Drawings
FIG. 1 is an overall scheme architecture of the reliable on-line upgrading system of the firmware program based on FPGA of the present invention;
FIG. 2 is an overall flowchart of the reliable on-line upgrading method of the firmware program based on FPGA according to the present invention;
FIG. 3 is a diagram of a data packet format sent by the software architecture to the logic architecture according to the present invention;
FIG. 4 is a diagram illustrating a data packet format sent by the logic architecture to the software architecture according to the present invention.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The invention discloses a reliable online upgrading system and method of a firmware program based on an FPGA (field programmable gate array), and mainly aims to invent a reliable online upgrading method suitable for realizing the FPGA. The method has strong flexibility, can realize remote program updating, and has no risk of incapability of starting due to updating failure.
The overall scheme architecture of the FPGA-based firmware program reliable online upgrade system is shown in FIG. 1, and the system comprises a Software (Software) architecture part and a logic (FPGA) architecture part.
The Software (Software) architecture part is mainly responsible for initiating the firmware online upgrading function, upgrading data transmission, upgrading data reliability measurement, flow processing under the condition of abnormal data transmission and the like.
The logic (FPGA) architecture part is mainly responsible for receiving a data packet through a network interface, calculating FCS of the data packet, analyzing the format of the data packet, writing data of the data packet into FLASH loaded by the FPGA through a firmware configuration interface, and returning a response packet of the currently received data packet after the writing is finished.
The software architecture comprises a firmware updating application program, other application programs and a network port distribution and convergence module, wherein the firmware updating application program and the other application programs are connected to the network port distribution and convergence module.
The firmware update application program is mainly responsible for updating the firmware according to the requirements of users, is used for receiving update data, dividing data packets and controlling an update process, and mainly comprises the following processes:
s11, the firmware updating application program firstly receives the complete updating data and verifies the integrity of the data;
s12, after the integrity verification is passed, dividing the updating data into a plurality of data packets with 1KB byte, and sending the data packets to the logic architecture in sequence;
s13, the firmware updating application program firstly sends a firmware erasing command, and starts to send data to the logic architecture after the erasing is finished;
s14, after the firmware updating application program sends out a data packet each time, the response message after the data packet is written into the FLASH is waited;
s15, after receiving the response message of completing writing the data packet, the firmware updating application program starts to send the next packet of data;
s16, when the firmware update application finishes sending a data packet, no response packet is received within a specified time (20 ms), or the received response packet carries information about abnormal update, the firmware update application considers that the data packet transmission process is abnormal, and can immediately stop the current update.
Other application programs in the software architecture are designed according to the function definition, and the other application programs communicate with the logic architecture through the internet access distribution convergence module, including but not limited to register configuration, table entry configuration, audit messages and the like.
The network port distribution and convergence module in the software architecture comprises distribution and convergence functions. The convergence function is mainly responsible for receiving the data packet of the upper application program and sending the data packet to the logic architecture through the lower hardware; the distribution function is mainly responsible for receiving the data packet from the hardware of the lower-layer logic architecture, analyzing the data packet and distributing the data packet according to the category of the analysis result.
The logic architecture comprises a network port MAC module, a data receiving module, a format analyzing module, a data sending module, a format packaging module, a FLASH control module and a configuration interface IP module.
The network port MAC module is mainly responsible for receiving and sending link layer network data packets. In the downlink direction of a data packet (from a software architecture to a logic architecture), the logic architecture needs to realize the functions of frame synchronization, frame interval check, FCS check and the like of a link layer data packet; in the uplink direction of a data packet (from a logic architecture to a software architecture), the logic architecture needs to implement FCS calculation of a link layer network data packet, addition of a data packet header (synchronization header) and a data packet tail (FCS), control of a frame gap, and the like.
The data receiving module in the logic architecture is connected with the network port MAC module and is mainly responsible for temporary storage of downlink data packets and clock domain crossing data transmission from the network port clock domain to the system clock domain.
The data sending module in the logic architecture is connected with the network port MAC module and is mainly responsible for temporary storage of uplink data packets and clock domain crossing data transmission from a system clock domain to a network port clock domain.
The format analysis module in the logic architecture is connected with the data receiving module, and is mainly responsible for format analysis (format shown in fig. 3) of the downlink data packet, key information extraction (type field extraction), data caching configuration (data caching is performed when the firmware is written in the operation command), and requests such as firmware erasing, firmware writing and firmware reading are initiated to the FLASH control module according to the type of the key information. If the format analysis module analyzes that the data format is wrong or abnormal, the data packet is directly discarded, a format abnormal signal is generated, and the format abnormal signal is sent to the format packaging module. And finally to a firmware update application of the software architecture.
The format encapsulation module in the logic architecture is connected to the data transmission module and is mainly responsible for format encapsulation of the uplink data packet (the format is shown in fig. 4). The encapsulation includes information encapsulation such as link layer header, type (corresponding encapsulation is performed according to the downlink data type), state (the state of the response packet, 0 is normal return, otherwise is abnormal return), load (only when the firmware reads the command, the valid data is filled, otherwise, 0 is filled), and the like.
The FLASH control module in the logic architecture is connected with the format analysis module and the format encapsulation module and is mainly responsible for controlling the erasing, writing and reading functions of the FLASH chip through the configuration interface IP. When the FLASH control module receives a firmware erasing request of the format analysis module, the FLASH control module initiates an erasing operation of the FLASH, generates an erasing completion signal after the FLASH is erased, sends the erasing completion signal to the format packaging module, and finally sends the erasing completion signal to a firmware updating application program of the software architecture; when the FLASH control module receives a firmware writing request, writing operation of the FLASH is initiated, and after the FLASH writing data is completed, a writing completion signal is generated and sent to the format packaging module, and finally the writing completion signal is sent to a firmware updating application program of the software architecture. When receiving a firmware reading request, the FLASH control module initiates a FLASH reading operation, generates a reading completion signal after the FLASH reading is completed, sends the reading completion signal and the read data to the format packaging module, and finally sends the reading completion signal to a firmware updating application program of the software architecture.
A configuration interface IP module in the logic architecture is connected with the FLASH control module and the FPGA loading FLASH and is mainly responsible for data communication between the internal logic and the FPGA loading FLASH.
The flow of the reliable online upgrading method of the firmware program based on the FPGA is shown in FIG. 2, and the specific steps are as follows:
the first step is as follows: the software architecture firmware updating application program receives the updating data until the data reception is completed;
the second step is that: the software architecture firmware updating application program carries out integrity verification on the complete firmware updating data packet, carries out next operation on the data packet passing the verification, and returns an error if not;
the third step: a software architecture firmware updating application program divides a data packet into a plurality of data packets with 1KB byte for complete firmware and performs message encapsulation;
the fourth step: the software architecture firmware updating application program sends a firmware erasing command to the logic architecture, and the FLASH is relatively slow to erase, so that the waiting time is long, and the next operation is carried out after the erasing is finished;
the fifth step: after the software architecture firmware updating application program sends a data packet to the logic architecture, a response message of the data packet written into the FLASH is waited;
and a sixth step: the network port MAC module of the logic structure carries out frame synchronization, frame interval check and FCS check on a data packet in the downlink direction (from software to logic). The verification proceeds to the next step through the flow;
the seventh step: and the format analysis module of the logic architecture finishes extracting the key information and initiates requests of erasing, writing, reading and the like to the FLASH control module according to the type of the key information. And if the format analysis module analyzes that the format of the data packet is wrong, the data packet is directly discarded to generate a format abnormal signal, and a response packet carrying abnormal information content is requested to be generated from the format packaging module.
Eighth step: and the FLASH control module of the logic architecture performs corresponding FLASH operations according to different request types such as erasing, writing and reading, and returns a normal completion response packet through the format encapsulation module after the operations are completed.
The ninth step: and the format packaging module of the logic framework completes the packaging of the response packet according to the request types of the format analysis module and the FLASH control module and outputs the response packet to the network port MAC module through the data sending module.
The tenth step: the network port MAC module of the logic architecture processes the uplink direction (the data packet is from logic to software) data packet and then sends the processed data packet to the software architecture through the network port; the packet processing includes FCS calculation, adding a header and a trailer to the packet, and controlling the inter-frame gap.
The eleventh step: and the network port distribution and convergence module of the software architecture analyzes the corresponding answer data packet and distributes the answer data packet to the corresponding application program according to the answer category.
The twelfth step: if the response message is not received after timeout or the response message carrying abnormal information is received, skipping to the fourth step to restart the firmware upgrading; if the normal response message is received and the data packet is not completely transmitted, jumping to the fifth step, otherwise, jumping to the next step;
the thirteenth step: and finishing the on-line upgrading of the firmware program.
The key points of the invention are as follows:
the method can ensure that the firmware upgrading data can be completely and correctly upgraded to the firmware memory FLASH.
The software architecture first needs to perform integrity check on the received upgrade data packet.
The MAC interface logic of the logic architecture needs to perform integrity check on the received data packet.
And the format analysis module of the logic architecture carries out format correctness verification on the received data packet.
And (4) a corresponding processing mechanism of the software architecture firmware upgrading program to the response message carrying the abnormal mark.
The invention has the following effects:
the invention provides a reliable online upgrading method of firmware programs based on an FPGA. The flexibility of the online upgrading method is ensured, the remote program can be updated, the operation of the matched interface is simple, the use is flexible, and the risk of incapability of starting due to updating failure is avoided.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A reliable online upgrading system of firmware programs based on FPGA is characterized in that the system comprises a software architecture and a logic architecture, wherein the software architecture comprises a firmware updating application program and a network port distribution and convergence module, and the logic architecture comprises a network port MAC module, a data receiving module, a format analysis module, a data sending module, a format encapsulation module, a FLASH control module and a configuration interface IP module;
the firmware updating application program is used for receiving the updating data, dividing the data packet and controlling the updating process, and is connected to the internet access distribution convergence module;
the network port distribution and convergence module comprises a distribution function and a convergence function, and the convergence function is used for receiving a data packet of an upper application program and sending the data packet to the logic architecture through lower hardware; the distribution function is used for receiving the data packet from the hardware of the lower-layer logic architecture, analyzing the data packet and distributing the data packet according to the category of the analysis result;
the network port MAC module is used for receiving and sending a link layer network data packet, the data packet is in a downlink direction, namely the data packet is from a software architecture to a logic architecture, and the logic architecture needs to realize frame synchronization, frame interval check and FCS check of the link layer data packet; the data packet uplink direction, namely the data packet is from a logic architecture to a software architecture, and the logic architecture needs to realize FCS calculation of a link layer network data packet, addition of a data packet frame head and a data packet tail and control of a frame gap;
the data receiving module is connected with the network port MAC module and is used for temporary storage of downlink data packets and clock domain crossing data transmission from a network port clock domain to a system clock domain;
the data sending module is connected with the network port MAC module and is used for temporary storage of an uplink data packet and clock domain crossing data transmission from a system clock domain to a network port clock domain;
the format analysis module is connected with the data receiving module and is used for analyzing the format of the downlink data packet, extracting key information, configuring the cache of data and initiating requests of firmware erasing, firmware writing, firmware reading and the like to the FLASH control module according to the type of the key information;
the format encapsulation module is connected with the data sending module and is used for encapsulating the format of the uplink data packet;
the FLASH control module is connected with the format analysis module and the format encapsulation module and is used for controlling the erasing, writing and reading of the FLASH chip through the configuration interface IP; when the FLASH control module receives a firmware erasing request of the format analysis module, the FLASH control module initiates an erasing operation of the FLASH, generates an erasing completion signal after the FLASH is erased, sends the erasing completion signal to the format packaging module, and finally sends the erasing completion signal to a firmware updating application program of the software architecture; when receiving a firmware writing request, the FLASH control module initiates writing operation of FLASH, generates a writing completion signal after writing data into the FLASH is completed, sends the writing completion signal to the format packaging module, and finally sends the writing completion signal to a firmware updating application program of a software framework; when receiving a firmware reading request, the FLASH control module initiates a FLASH reading operation, generates a reading completion signal after the FLASH reading is completed, sends the reading completion signal and the read data to the format packaging module, and finally sends the reading completion signal to a firmware updating application program of the software architecture;
the configuration interface IP module is connected with the FLASH control module and the FPGA loading FLASH and is used for data communication between the internal logic and the FPGA loading FLASH.
2. The reliable online upgrade system for firmware programs based on FPGA of claim 1, wherein the software architecture further comprises other applications, the other applications are designed according to the function definition, and communicate with the logic architecture through the portal distribution aggregation module, including register configuration, table entry configuration, and audit messages.
3. The reliable on-line upgrade system for firmware programs based on FPGA of claim 1, characterized in that the processing procedure of the firmware update application program comprises:
s11, the firmware updating application program firstly receives the complete updating data and verifies the integrity of the data;
s12, after the integrity verification is passed, dividing the updating data into a plurality of data packets with 1KB byte, and sending the data packets to the logic architecture in sequence;
s13, the firmware updating application program firstly sends a firmware erasing command, and starts to send data to the logic architecture after the erasing is finished;
s14, after the firmware updating application program sends out a data packet each time, the response message after the data packet is written into the FLASH is waited;
s15, after receiving the response message of completing writing the data packet, the firmware updating application program starts to send the next packet of data;
and S16, when the firmware updating application program finishes sending a data packet, the response packet is not received within the specified time, or the received response packet carries abnormal updating information, the firmware updating application program considers that the data packet transmission process is abnormal, and the current updating is immediately stopped.
4. The FPGA-based firmware program reliable online upgrade system of claim 1, wherein the format of the format encapsulation module encapsulation includes a link layer header, a type, a status, and a payload; wherein, the state is 0, which indicates normal return, otherwise, the state is abnormal return; the payload is filled with valid data only when the firmware reads the command, otherwise 0 is filled.
5. The FPGA-based firmware program reliable online upgrade system as claimed in claim 4, wherein if the format parsing module parses the data packet to be incorrect or abnormal, the data packet is directly discarded, a format abnormal signal is generated and sent to the format encapsulation module, and finally the format abnormal signal is sent to the firmware update application program of the software architecture.
6. A reliable online upgrading method for firmware programs based on FPGA is characterized by comprising the following steps:
the first step is as follows: the software architecture firmware updating application program receives the updating data until the data reception is completed;
the second step is that: the software architecture firmware updating application program carries out integrity verification on the complete firmware updating data packet, carries out next operation on the data packet passing the verification, and returns an error if not;
the third step: a software architecture firmware updating application program divides a data packet into a plurality of data packets with 1KB byte for complete firmware and performs message encapsulation;
the fourth step: the software framework firmware updating application program sends a firmware erasing command to the logic framework, and the next operation is carried out after the erasing is finished;
the fifth step: after the software architecture firmware updating application program sends a data packet to the logic architecture, a response message of the data packet written into the FLASH is waited;
and a sixth step: the network port MAC module of the logic structure carries out frame synchronization, frame interval inspection and FCS (field control protocol) inspection on the data packet in the downlink direction; the verification is carried out to the next step through the flow;
the seventh step: the format analysis module of the logic architecture finishes the extraction of the key information and initiates erasing, writing and reading requests to the FLASH control module according to the type of the key information;
eighth step: the FLASH control module of the logic framework performs corresponding FLASH operations according to the types of the erasing, writing and reading requests, and returns a normal completion response packet through the format encapsulation module after the operations are completed;
the ninth step: the format packaging module of the logic framework completes the packaging of the response packet according to the request types of the format analysis module and the FLASH control module and outputs the response packet to the network port MAC module through the data sending module;
the tenth step: the network port MAC module of the logic architecture processes the uplink direction data packet and then sends the processed uplink direction data packet to the software architecture through the network port;
the eleventh step: the network port distribution and convergence module of the software architecture analyzes the corresponding answer data packet and distributes the answer data packet to a corresponding application program according to the answer category;
the twelfth step: if the response message is not received after timeout or the response message carrying abnormal information is received, skipping to the fourth step to restart the firmware upgrading; if the normal response message is received and the data packet is not completely transmitted, jumping to the fifth step, otherwise, jumping to the next step;
the thirteenth step: and finishing the on-line upgrading of the firmware program.
7. The method according to claim 6, wherein the software architecture further comprises other applications, and the other applications are designed according to the function definition and communicate with the logic architecture through the portal distribution convergence module, including register configuration, table entry configuration, and audit messages.
8. The FPGA-based firmware program reliable online upgrade method as claimed in claim 6, wherein in the seventh step, if the format parsing module parses that the data format is wrong or abnormal, the data packet is directly discarded, a format abnormal signal is generated and sent to the format encapsulation module, and finally the data packet is sent to the firmware update application program of the software architecture.
9. The method for reliable online upgrade of firmware programs based on FPGA of claim 6, wherein the format of the package of the response packet in the ninth step comprises: link layer head, type, status and load; wherein, the state is 0, which indicates normal return, otherwise, the state is abnormal return; the payload is filled with valid data only when the firmware reads the command, otherwise 0 is filled.
10. The method for reliable on-line upgrade of firmware programs based on FPGA according to claim 6, wherein the packet processing of the tenth step includes FCS calculation, adding frame header and tail to the packet, and frame gap control operation.
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