CN115037194A - Driving circuit with interlocked upper and lower bridge arms, three-phase motor and automobile - Google Patents

Driving circuit with interlocked upper and lower bridge arms, three-phase motor and automobile Download PDF

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Publication number
CN115037194A
CN115037194A CN202210862397.XA CN202210862397A CN115037194A CN 115037194 A CN115037194 A CN 115037194A CN 202210862397 A CN202210862397 A CN 202210862397A CN 115037194 A CN115037194 A CN 115037194A
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CN
China
Prior art keywords
circuit
driving circuit
bridge arm
electrically connected
lower bridge
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Pending
Application number
CN202210862397.XA
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Chinese (zh)
Inventor
韩振洋
蔡军
周红梅
李卫海
杨超
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Beijing Electric Vehicle Co Ltd
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Beijing Electric Vehicle Co Ltd
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Publication date
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Priority to CN202210862397.XA priority Critical patent/CN115037194A/en
Publication of CN115037194A publication Critical patent/CN115037194A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
    • H02P6/08—Arrangements for controlling the speed or torque of a single motor
    • H02P6/085—Arrangements for controlling the speed or torque of a single motor in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/72—Electric energy management in electromobility

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention provides a driving circuit with interlocked upper and lower bridge arms, a three-phase motor and an automobile, relates to the technical field of electric automobile driving, and solves the problem that the upper and lower bridge arms are conducted due to external influence. The drive circuit with interlocked upper and lower bridge arms comprises: a microcontroller control unit for generating a control signal; the at least one path of interlocking circuit is electrically connected with the microcontroller control unit and is used for carrying out high-low level conversion on the control signals so that each phase of output control signals are not high level signals at the same time; the signal driving circuit is electrically connected with the interlocking circuit and is used for receiving the control signal processed by the interlocking circuit and controlling the on-off of the upper bridge arm driving circuit and the lower bridge arm driving circuit through the control signal; and the upper and lower bridge arm driving circuits are electrically connected with the signal driving circuit and are used for controlling the output of the voltage of the power battery. The scheme of the invention realizes that the on-off of the upper and lower bridge arm driving circuits is not influenced by the outside.

Description

Driving circuit with interlocked upper and lower bridge arms, three-phase motor and automobile
Technical Field
The invention relates to the technical field of electric automobile driving, in particular to a driving circuit with interlocked upper and lower bridge arms, a three-phase motor and an automobile.
Background
The vehicle-mounted motor of the electric automobile is a source of power output of the electric automobile, the motor mostly adopts three alternating current permanent magnet synchronous motors, three power sources of the motor are direct current of a battery, and the direct current is converted into three alternating currents which can be used by the motor through a power device. The power device adopts 3 sets of power devices IGBT with upper and lower bridge arms, the motor controller drives the IGBT by controlling the high-voltage integrated circuit, and then controls the conduction of the upper bridge arm or the lower bridge arm of each path, so that the voltage output by each path is high or low. However, in the use process of the IGBT, if the upper and lower arms of the same IGBT are turned on at the same time, the IGBT is short-circuited between the power supply and the ground, and a large current passes through the IGBT crystal instantly, which may cause the IGBT to be burned.
Aiming at the hidden trouble, software is mostly used in the industry, a pair of opposite PWM waves of a main control chip sent from a high-voltage integrated circuit respectively drive an upper bridge arm and a lower bridge arm of each path through corresponding circuits, and dead time is set on the software, so that the simultaneous conduction of the upper bridge arm and the lower bridge arm is avoided.
Disclosure of Invention
The invention aims to provide a driving circuit with interlocked upper and lower bridge arms, a three-phase motor and an automobile, so that the on-off of the driving circuit of the upper and lower bridge arms is not influenced by the outside.
In order to solve the technical problems, the technical scheme of the invention is as follows:
an upper and lower leg interlocked drive circuit comprising:
a microcontroller control unit for generating a control signal;
the at least one path of interlocking circuit is electrically connected with the microcontroller control unit and is used for carrying out high-low level conversion on the control signals so that each phase of output control signals are not high level signals at the same time;
the signal driving circuit is electrically connected with the interlocking circuit and is used for receiving the control signal processed by the interlocking circuit and controlling the on-off of the upper bridge arm driving circuit and the lower bridge arm driving circuit through the control signal;
and the upper and lower bridge arm driving circuits are electrically connected with the signal driving circuit and are used for controlling the output of the voltage of the power battery.
Optionally, the at least one interlock circuit includes:
the first path of interlocking circuit, the second path of interlocking circuit and the third path of interlocking circuit;
the first path of interlocking circuit, the second path of interlocking circuit and the third path of interlocking circuit are all identical in circuit structure, and input ends of the first path of interlocking circuit, the second path of interlocking circuit and the third path of interlocking circuit are respectively and electrically connected with the microcontroller control unit.
Optionally, the first way of interlock circuit, the second way of interlock circuit, and the third way of interlock circuit all include:
the first input end of the first AND gate circuit is electrically connected with the microcontroller control unit and is used for receiving a first control signal sent by the microcontroller control unit;
the first input end of the second AND gate circuit is electrically connected with the microcontroller control unit and is used for receiving a second control signal sent by the microcontroller control unit;
the input end of the first NOT gate circuit is electrically connected with the microcontroller control unit and is used for receiving a first control signal sent by the microcontroller control unit, and the output end of the first NOT gate circuit is electrically connected with the second input end of the second AND gate circuit;
the input end of the second NOT gate circuit is electrically connected with the microcontroller control unit and is used for receiving a second control signal sent by the microcontroller control unit, and the output end of the second NOT gate circuit is electrically connected with the second input end of the first AND gate circuit;
when the first control signal and the second control signal are the same and are both at a high level, the first control signal is input to the first input end of the first and-gate circuit, the second control signal is input to the first input end of the second and-gate circuit, the second control signal passing through the second not-gate circuit is input to the second input end of the first and-gate circuit and is at a low level, the first control signal passing through the first not-gate circuit is input to the second input end of the second and-gate circuit and is at a low level, and the first and-gate circuit and the second and-gate circuit output a low level at the same time;
when the first control signal and the second control signal are the same and are both low level, the first control signal is input into the first input end of the first and gate circuit, the second control signal is input into the first input end of the second and gate circuit, the second control signal passing through the second not gate circuit is input into the second input end of the first and gate circuit and is high level, the first control signal passing through the first not gate circuit is input into the second input end of the second and gate circuit and is high level, and the first and gate circuit and the second and gate circuit output low level simultaneously;
the first control signal and the second control signal are different, the first input end of the first and-gate circuit inputs the high level of the first control signal, when the first input end of the second and-gate circuit inputs the low level of the second control signal, the second control signal which passes through the second not-gate circuit and is input by the second input end of the first and-gate circuit is high level, the first control signal which passes through the first not-gate circuit and is input by the second input end of the second and-gate circuit is low level, the first and-gate circuit outputs high level, and the second and-gate circuit outputs low level;
the first control signal is different from the second control signal, a high level of the first control signal is input to a first input end of the first and-gate circuit, when a low level of the second control signal is input to a first input end of the second and-gate circuit, the second control signal passing through the second not-gate circuit is input to a second input end of the first and-gate circuit and is a low level, the first control signal passing through the first not-gate circuit is input to a second input end of the second and-gate circuit and is a high level, the first and-gate circuit outputs a low level, and the second and-gate circuit outputs a high level.
Optionally, the signal driving circuit includes:
the first signal driving circuit, the second signal driving circuit and the third signal driving circuit;
the first signal driving circuit, the second signal driving circuit and the third signal driving circuit have the same structure;
the first input end and the second input end of the first path of signal driving circuit are respectively and electrically connected with the output of the first path of interlocking circuit;
the first input end and the second input end of the second path of signal driving circuit are respectively and electrically connected with the output of the second path of interlocking circuit;
and the first input end and the second input end of the third path of signal driving circuit are respectively and electrically connected with the output of the third path of interlocking circuit.
Optionally, the upper and lower bridge arm driving circuits include:
the driving circuit comprises a first upper bridge arm driving circuit, a second upper bridge arm driving circuit, a third upper bridge arm driving circuit and a third lower bridge arm driving circuit;
the first upper bridge arm driving circuit, the second upper bridge arm driving circuit and the third upper bridge arm driving circuit are identical in structure;
a first input end and a second input end of the first upper bridge arm driving circuit and the first lower bridge arm driving circuit are respectively and electrically connected with the output of the first path of signal driving circuit;
the first input end and the second input end of the second upper bridge arm driving circuit and the second upper bridge arm driving circuit are respectively and electrically connected with the output of the second path of signal driving circuit;
and the first input end and the second input end of the third upper and lower bridge arm driving circuit are respectively electrically connected with the output of the third signal driving circuit.
Optionally, the first upper and lower bridge arm driving circuit, the second upper and lower bridge arm driving circuit, and the third upper and lower bridge arm driving circuit are connected in parallel to the power battery.
Optionally, the output end of the first upper and lower bridge arm driving circuit is electrically connected to a U phase of the three-phase motor, and is configured to control an input voltage on the U phase of the three-phase motor by turning on and off the first upper and lower bridge arm driving circuit;
the output end of the second upper and lower bridge arm driving circuit is electrically connected with the V phase of the three-phase motor and is used for controlling the input voltage on the V phase of the three-phase motor through the on-off of the second upper and lower bridge arm driving circuit;
and the output end of the third upper and lower bridge arm driving circuit is electrically connected with the W phase of the three-phase motor and is used for controlling the input voltage on the W phase of the three-phase motor through the on-off of the third upper and lower bridge arm driving circuit.
Optionally, the first upper and lower bridge arm driving circuit, the second upper and lower bridge arm driving circuit, and the third upper and lower bridge arm driving circuit all include:
a first insulated gate bipolar transistor and a second insulated gate bipolar transistor;
the grid electrodes of a first insulated gate bipolar transistor and a second insulated gate bipolar transistor of the first upper bridge arm driving circuit and the first lower bridge arm driving circuit are electrically connected with the output end of the first path of signal driving circuit, the source electrode of the first insulated gate bipolar transistor is electrically connected with the anode of the power battery, the drain electrode of the first insulated gate bipolar transistor is electrically connected with the U phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor, and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the cathode of the power battery;
the grid stages of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor of the second upper and lower bridge arm driving circuit are electrically connected with the output end of the second signal driving circuit, the source electrode of the first insulated gate bipolar transistor is electrically connected with the positive electrode of the power battery, the drain electrode of the first insulated gate bipolar transistor is electrically connected with the V phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor, and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the negative electrode of the power battery;
the grid stages of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor of the third upper and lower bridge arm driving circuit are electrically connected with the output end of the third signal driving circuit, the source electrode of the first insulated gate bipolar transistor is electrically connected with the anode of the power battery, the drain electrode of the first insulated gate bipolar transistor is electrically connected with the W phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor, and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the cathode of the power battery. The embodiment of the invention also provides a three-phase motor which comprises the driving circuit with interlocked upper and lower bridge arms.
The embodiment of the invention also provides a three-phase motor which comprises the driving circuit with the interlocked upper and lower bridge arms.
Embodiments of the present invention also provide an automobile including the three-phase motor as described above.
The scheme of the invention at least comprises the following beneficial effects:
in the above aspect of the present invention, the driving circuit interlocked by the upper and lower bridge arms includes: a microcontroller control unit for generating a control signal; the at least one path of interlocking circuit is electrically connected with the microcontroller control unit and is used for carrying out high-low level conversion on the control signals so that each phase of output control signals are not high level signals at the same time; the signal driving circuit is electrically connected with the interlocking circuit and is used for receiving the control signal processed by the interlocking circuit and controlling the on-off of the upper bridge arm driving circuit and the lower bridge arm driving circuit through the control signal; and the upper and lower bridge arm driving circuits are electrically connected with the signal driving circuit and are used for controlling the output of the voltage of the power battery. The problem that the upper and lower bridge arms are conducted due to the fact that the upper and lower bridge arm driving circuits are interfered by factors such as PCB design, structural layout, external EMC interference and parasitic capacitance of a circuit board is solved, the fact that the on-off of the upper and lower bridge arm driving circuits is not influenced by the outside is achieved, meanwhile, the fact that the upper bridge arm circuit and the lower bridge arm circuit cannot output high-level signals simultaneously is guaranteed, and the conducting of the upper and lower bridge arms is avoided.
Drawings
FIG. 1 is a schematic structural diagram of a driving circuit for interlocking upper and lower bridge arms according to the present invention;
fig. 2 is a schematic structural diagram of an interlock circuit in the drive circuit for interlocking the upper and lower bridge arms according to the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As shown in fig. 1, an embodiment of the present invention provides a lower bridge arm interlocking driving circuit, including:
a microcontroller control unit 1 for generating a control signal;
at least one path of interlocking circuit 2 electrically connected with the microcontroller control unit 1 and used for performing high-low level conversion on the control signal to ensure that each phase of output control signal is not a high-level signal at the same time; specifically, the two control signals of each phase are not high level at the same time.
The signal driving circuit 3 is electrically connected with the interlocking circuit 2 and is used for receiving the control signal processed by the interlocking circuit and controlling the on-off of the upper bridge arm driving circuit 4 and the lower bridge arm driving circuit 4 through the control signal;
and an upper and lower arm drive circuit 4 electrically connected to the signal drive circuit 3, for controlling the output of the voltage of the power battery 5.
In this embodiment, the microcontroller control unit 1 sends six control signals UPWM-H, UPWM-L, VPWM-H, VPWM-L, WPWM-H, and WPWM-L, where UPWM-H and UPWM-L signals are used to control the on/off of upper and lower bridge arms on a U-phase of the three-phase motor, VPWM-H and VPWM-L signals are used to control the on/off of upper and lower bridge arms on a V-phase, WPWM-H and WPWM-L signals are used to control the on/off of upper and lower bridge arms on a W-phase of the three-phase motor, and meanwhile, the off time of the two control signals on each phase has a delayed dead time, so that the upper and lower bridge arms are not disconnected at the same time, thereby ensuring that a continuous and stable voltage is provided for the motor.
In an optional embodiment of the present invention, the at least one way interlock circuit 2 includes:
a first way of interlocking circuit 21, a second way of interlocking circuit 22 and a third way of interlocking circuit 23;
the first interlocking circuit 21, the second interlocking circuit 22 and the third interlocking circuit 23 have the same circuit structure, and the input ends of the first interlocking circuit, the second interlocking circuit and the third interlocking circuit are respectively and electrically connected with the microcontroller control unit 1.
In this embodiment, the first interlocking circuit 21 is configured to receive a UPWM-H signal and a UPWM-L signal sent by the microcontroller control unit 1, the second interlocking circuit 22 is configured to receive a VPWM-H signal and a VPWM-L signal sent by the microcontroller control unit 1, and the third interlocking circuit 23 is configured to receive a WPWM-H signal and a WPWM-L signal sent by the microcontroller control unit 1.
As shown in fig. 2, in an optional embodiment of the present invention, the first interlock circuit 21, the second interlock circuit 22, and the third interlock circuit 23 each include:
a first input end of the first and gate circuit 211 is electrically connected to the microcontroller control unit 1, and is configured to receive a first control signal sent by the microcontroller control unit 1;
a second and gate circuit 212, a first input end of the second and gate circuit 212 is electrically connected with the microcontroller control unit 1, and is configured to receive a second control signal sent by the microcontroller control unit 1;
the input end of the first not gate circuit 213 is electrically connected to the microcontroller control unit 1, and is configured to receive a first control signal sent by the microcontroller control unit 1, and the output end of the first not gate circuit 213 is electrically connected to the second input end of the second and gate circuit 212;
a second not gate circuit 214, an input end of the second not gate circuit 214 is electrically connected to the microcontroller control unit 1, and is configured to receive a second control signal sent by the microcontroller control unit 1, and an output end of the second not gate circuit 214 is electrically connected to a second input end of the first and gate circuit 211;
when the first control signal and the second control signal are the same and both are at a high level, the first control signal is input to the first input end of the first and circuit 211, the second control signal is input to the first input end of the second and circuit 212, the second control signal, which passes through the second not circuit 214, is input to the second input end of the first and circuit 211 and is at a low level, the first control signal, which passes through the first not circuit 213, is input to the second input end of the second and circuit 212 and is at a low level, and the first and circuit 211 and the second and circuit 212 output a low level at the same time;
when the first control signal and the second control signal are the same and both are at a low level, the first control signal is input to the first input end of the first and-gate circuit 211, the second control signal is input to the first input end of the second and-gate circuit 212, the second control signal after passing through the second not-gate circuit 214 is input to the second input end of the first and-gate circuit 211 and is at a high level, the first control signal after passing through the first not-gate circuit 213 is input to the second input end of the second and-gate circuit 212 and is at a high level, and the first and-gate circuit 211 and the second and-gate circuit 212 output a low level at the same time;
the first control signal and the second control signal are different, a high level of the first control signal is input to a first input end of the first and-gate circuit 211, when a low level of the second control signal is input to a first input end of the second and-gate circuit 212, a second control signal which passes through the second not-gate circuit 214 and is input to a second input end of the first and-gate circuit 211 is a high level, a first control signal which passes through the first not-gate circuit 213 and is input to a second input end of the second and-gate circuit 212 is a low level, the first and-gate circuit 211 outputs a high level, and the second and-gate circuit 212 outputs a low level;
the first control signal and the second control signal are different, when the first input end of the first and gate circuit 211 inputs the high level of the first control signal, and when the first input end of the second and gate circuit 212 inputs the low level of the second control signal, the second control signal input by the second input end of the first and gate circuit 211 after passing through the second not gate circuit 214 is at the low level, the first control signal input by the second input end of the second and gate circuit 212 after passing through the first not gate circuit 213 is at the high level, the first and gate circuit 211 outputs the low level, and the second and gate circuit 212 outputs the high level.
In this embodiment, when the control signals input to the input ends of the first not gate circuit 213 and the second not gate circuit 214 are high level signals, a low level is output, and when the low level control signals are input, a high level is output, and only when the control signals input to the input ends of the first and gate circuit 211 and the second and gate circuit 212 are both high level signals, a high level is output, otherwise, a low level is output uniformly.
The first control signal and the second control signal are a UPWM-H signal and a UPWM-L signal, respectively.
When the UPWM-H signal and the UPWM-L signal output high levels at the same time, the first input terminal of the first and circuit 211 and the first input terminal of the second and circuit 212 input the high level of the UPWM-H signal and the high level of the UPWM-L signal, respectively, the input terminals of the first and circuit 213 and the second not circuit 214 input the high level of the UPWM-H signal and the high level of the UPWM-L signal, respectively, and then the output terminals of the first and circuit 213 and the second not circuit 214 output the low level of the UPWM-H signal and the low level of the UPWM-L signal, respectively, the second input terminal of the first and circuit 211 inputs the low level of the UPWM-L signal after passing through the second not circuit 214, the second input terminal of the second and circuit 212 inputs the low level of the UPWM-H signal after passing through the first not circuit 213, the first and circuit 211 and the second and circuit 212 simultaneously output a low level to the UPWM-H-OUT signal and the UPWM-L-OUT signal.
When the UPWM-H signal and the UPWM-L signal output a low level simultaneously, the first input terminal of the first and-gate circuit 211 and the first input terminal of the second and-gate circuit 212 input a low level of the UPWM-H signal and a low level of the UPWM-L signal respectively, the input terminals of the first and-gate circuit 213 and the second not-gate circuit 214 input a low level of the UPWM-H signal and a low level of the UPWM-L signal respectively, then the output terminals of the first and-gate circuit 213 and the second not-gate circuit 214 output a high level of the UPWM-H signal and a high level of the UPWM-L signal respectively, the second input terminal of the first and-gate circuit 211 inputs a high level of the UPWM-L signal that passes through the second not-gate circuit 214, the second input terminal of the second and-gate circuit 212 inputs a high level of the UPWM-H signal that passes through the first not-gate circuit 213, the first and circuit 211 and the second and circuit 212 simultaneously output a low level to the UPWM-H-OUT signal and the UPWM-L-OUT signal.
When the UPWM-H signal outputs a high level and the UPWM-L signal outputs a low level, the first input terminal of the first and circuit 211 and the first input terminal of the second and circuit 212 respectively input the high level of the UPWM-H signal and the low level of the UPWM-L signal, the input terminals of the first and circuit 213 and the second not circuit 214 respectively input the high level of the UPWM-H signal and the low level of the UPWM-L signal, then the output terminals of the first and circuit 213 and the second not circuit 214 respectively output the low level of the UPWM-H signal and the high level of the UPWM-L signal, the second input terminal of the first and circuit 211 inputs the high level of the UPWM-L signal after passing through the second not circuit 214, the second input terminal of the second and circuit 212 inputs the low level of the UPWM-H signal after passing through the first not circuit 213, the first and circuit 211 outputs a high level to the UPWM-H-OUT signal and the second and circuit 212 outputs a low level to the UPWM-L-OUT signal.
When the UPWM-H signal outputs a low level and the UPWM-L signal outputs a high level, the first input terminal of the first and circuit 211 and the first input terminal of the second and circuit 212 respectively input a low level of the UPWM-H signal and a high level of the UPWM-L signal, the input terminals of the first and circuit 213 and the second not circuit 214 respectively input a low level of the UPWM-H signal and a high level of the UPWM-L signal, the output terminals of the first and circuit 213 and the second not circuit 214 respectively output a high level of the UPWM-H signal and a low level of the UPWM-L signal, the second input terminal of the first and circuit 211 inputs a low level of the UPWM-L signal after passing through the second not circuit 214, the second input terminal of the second and circuit 212 inputs a high level of the UPWM-H signal after passing through the first not circuit 213, the first and circuit 211 outputs a low level to the UPWM-H-OUT signal and the second and circuit 212 outputs a high level to the UPWM-L-OUT signal.
Through the design of the interlocking circuit, the interlocking output design of the upper bridge arm circuit and the lower bridge arm circuit on each phase of the three-phase motor is realized, the upper bridge arm circuit and the lower bridge arm circuit cannot simultaneously output high-level signals, and the conduction of the upper bridge arm and the lower bridge arm is avoided.
In an alternative embodiment of the present invention, the signal driving circuit 3 includes:
a first signal driving circuit 31, a second signal driving circuit 32, and a third signal driving circuit 33;
the first signal driving circuit 31, the second signal driving circuit 32 and the third signal driving circuit 33 have the same structure;
a first input end and a second input end of the first path of signal driving circuit 31 are electrically connected with an output of the first path of interlocking circuit 21 respectively;
the first input end and the second input end of the second signal driving circuit 32 are electrically connected to the output of the second interlock circuit 22 respectively;
the first input terminal and the second input terminal of the third signal driving circuit 33 are electrically connected to the output of the third interlock circuit 23.
In this embodiment, the first signal driving circuit 31 is configured to receive the UPWM-H-OUT signal and the UPWM-L-OUT signal output by the first interlock circuit 21, the second signal driving circuit 32 is configured to receive the VPWM-H-OUT signal and the VPWM-L-OUT signal output by the second interlock circuit 22, and the third signal driving circuit 33 is configured to receive the WPWM-H-OUT signal and the WPWM-L-OUT signal output by the third interlock circuit 23.
In an optional embodiment of the present invention, the upper and lower bridge arm driving circuit 4 includes:
a first upper and lower arm drive circuit 41, a second upper and lower arm drive circuit 42, and a third upper and lower arm drive circuit 43;
the first upper and lower bridge arm drive circuit 41, the second upper and lower bridge arm drive circuit 42, and the third upper and lower bridge arm drive circuit 43 have the same structure;
a first input end and a second input end of the first upper and lower bridge arm driving circuit 41 are respectively electrically connected with the output of the first path of signal driving circuit 31;
a first input end and a second input end of the second upper and lower bridge arm driving circuit 42 are respectively electrically connected with the output of the second path of signal driving circuit 32;
the first input end and the second input end of the third upper and lower bridge arm driving circuit 43 are electrically connected to the output of the third signal driving circuit 33, respectively.
In this embodiment, the upper arm circuit of the first upper and lower arm driving circuit 41 is configured to receive the UPWM-H-OUT signal output by the first path signal driving circuit 31, and control the on/off of the upper arm circuit according to the high and low levels of the signal, so as to control the output of the positive electrode voltage of the rechargeable battery 5 on the U-phase;
the lower bridge arm circuit of the first upper and lower bridge arm driving circuit 41 is configured to receive the UPWM-L-OUT signal output by the first signal driving circuit 31, and control the on/off of the lower bridge arm circuit according to the high and low levels of the UPWM-L-OUT signal; thereby controlling the output of the negative electrode voltage of the power battery 5 on the U phase.
The upper bridge arm circuit of the second upper and lower bridge arm driving circuit 42 is configured to receive the VPWM-H-OUT signal output by the second signal driving circuit 32, and control the on-off of the upper bridge arm circuit according to the high and low levels of the VPWM-H-OUT signal, so as to control the output of the positive electrode voltage of the rechargeable battery 5 on the V phase;
the lower bridge arm circuit of the second upper and lower bridge arm driving circuit 42 is configured to receive the VPWM-L-OUT signal output by the second signal driving circuit 32, and control the on/off of the lower bridge arm circuit according to the high and low levels of the VPWM-L-OUT signal; thereby controlling the output of the negative electrode voltage of the power battery 5 on the V phase.
The upper bridge arm circuit of the third upper and lower bridge arm driving circuit 43 is configured to receive the WPWM-H-OUT signal output by the third signal driving circuit 33, and control the on-off of the upper bridge arm circuit according to the high and low levels of the WPWM-H-OUT signal, so as to control the output of the positive voltage of the power battery 5 on the W phase;
the lower bridge arm circuit of the third upper and lower bridge arm driving circuit 43 is configured to receive the WPWM-L-OUT signal output by the third signal driving circuit 33, and control the on/off of the lower bridge arm circuit according to the high and low levels of the WPWM-L-OUT signal; thereby controlling the output of the negative electrode voltage of the power cell 5 on the W phase.
In an alternative embodiment of the present invention, the first upper and lower bridge arm driving circuit 41, the second upper and lower bridge arm driving circuit 42, and the third upper and lower bridge arm driving circuit 43 are connected in parallel to the power battery 5.
The output end of the first upper and lower bridge arm driving circuit 41 is electrically connected with a U phase of the three-phase motor, and is used for controlling the input voltage on the U phase of the three-phase motor by switching on and off the first upper and lower bridge arm driving circuit 41;
the output end of the second upper and lower bridge arm driving circuit 42 is electrically connected with the V phase of the three-phase motor, and is used for controlling the input voltage on the V phase of the three-phase motor through the on-off of the second upper and lower bridge arm driving circuit 42;
the output end of the third upper and lower bridge arm driving circuit 43 is electrically connected to the W phase of the three-phase motor, and is configured to control the input voltage on the W phase of the three-phase motor by turning on and off the third upper and lower bridge arm driving circuit 43.
The first upper and lower arm drive circuit 41, the second upper and lower arm drive circuit 42, and the third upper and lower arm drive circuit 43 each include:
a first insulated gate bipolar transistor and a second insulated gate bipolar transistor;
the gates of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor of the first upper and lower bridge arm driving circuit 41 are electrically connected with the output end of the first signal driving circuit 31, the source electrode of the first insulated gate bipolar transistor is electrically connected with the positive electrode of the power battery 5, the drain electrode of the first insulated gate bipolar transistor is electrically connected with the U-phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor, and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the negative electrode of the power battery 5;
the gates of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor of the second upper and lower bridge arm driving circuit 42 are electrically connected with the output end of the second signal driving circuit 32, the source of the first insulated gate bipolar transistor is electrically connected with the positive electrode of the power battery 5, the drain of the first insulated gate bipolar transistor is electrically connected with the V-phase of the three-phase motor and the source of the second insulated gate bipolar transistor, and the drain of the second insulated gate bipolar transistor is electrically connected with the negative electrode of the power battery 5;
the gate levels of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor of the third upper and lower bridge arm driving circuit 43 are electrically connected with the output end of the third signal driving circuit 33, the source electrode of the first insulated gate bipolar transistor is electrically connected with the positive electrode of the power battery 5, the drain electrode of the first insulated gate bipolar transistor is electrically connected with the W phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor, and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the negative electrode of the power battery 5.
In this embodiment, the first igbt and the second igbt are an upper bridge arm and a lower bridge arm of the first upper and lower bridge arm driving circuit 41, respectively, and the upper and lower bridge arms are controlled to be on and off by a UPWM-H-OUT signal and a UPWM-L-OUT signal, respectively, so as to control input of voltage, and convert direct current of the power battery 5 into alternating current to be output to the U phase of the three-phase motor.
The specific working principle of the driving circuit with interlocked upper and lower bridge arms provided by the embodiment of the invention is as follows:
firstly, the microcontroller control unit sends OUT six control signals of UPWM-H, UPWM-L, VPWM-H, VPWM-L, WPWM-H and WPWM-L, wherein the UPWM-H and UPWM-L signals output an UPWM-H-OUT signal and an UPWM-L-OUT signal which do not lead the first upper and lower bridge arm driving circuit 41 to be conducted through the first interlocking circuit 21, and the UPWM-H-OUT signal and the UPWM-L-OUT signal respectively control the on-off of the upper bridge arm circuit and the lower bridge arm circuit of the first upper and lower bridge arm driving circuit 41 through the first signal driving circuit 31, so that the voltage on the U phase of the three-phase motor is controlled;
the VPWM-H and VPWM-L signals output VPWM-H-OUT signals and VPWM-L-OUT signals which do not enable the second upper and lower bridge arm driving circuits 42 through the second interlocking circuit 22, and the VPWM-H-OUT signals and the VPWM-L-OUT signals respectively control the on-off of the upper bridge arm circuit and the lower bridge arm circuit of the second upper and lower bridge arm driving circuits 42 through the second signal driving circuit 32, so that the voltage on the V phase of the three-phase motor is controlled;
the WPWM-H and WPWM-L signals output WPWM-H-OUT signals and WPWM-L-OUT signals which do not enable the third upper and lower bridge arm driving circuits 43 to be conducted through the third interlocking circuit 23, and the WPWM-H-OUT signals and the WPWM-L-OUT signals respectively control the connection and disconnection of the upper bridge arm circuit and the lower bridge arm circuit of the third upper and lower bridge arm driving circuits 43 through the third interlocking circuit 33, so that the voltage on the W phase of the three-phase motor is controlled; the operation of the three-phase motor is ultimately controlled by the voltages on the U, V, W three phases.
The embodiment of the invention also provides a three-phase motor which comprises the driving circuit with interlocked upper and lower bridge arms in any one of the embodiments. All technical features in the above embodiments are applicable to the embodiment, and the same technical effects can be achieved.
An embodiment of the present invention also provides an automobile including the three-phase motor as described above.
The upper and lower bridge arm interlocking driving circuit solves the problem that the upper and lower bridge arm driving circuits are conducted due to the interference of factors such as PCB design, structural layout, external EMC interference, parasitic capacitance and the like of a circuit board; the design is simple and concise based on a hardware digital circuit, the investment cost is low, and the logic of the digital circuit is not high, namely low, and is more reliable than an analog circuit, so that the difference of driving signals of an upper bridge arm and a lower bridge arm is effectively ensured, even if the upper bridge arm and the lower bridge arm are not conducted due to the interference of factors such as PCB design, structural layout, external EMC interference, parasitic capacitance and the like of a circuit board, and the function and the safety of a motor are ensured.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A drive circuit with interlocked upper and lower bridge arms is characterized by comprising:
a microcontroller control unit (1) for generating a control signal;
the interlocking circuit (2) is electrically connected with the microcontroller control unit (1) and is used for performing high-low level conversion on the control signals to ensure that each phase of output control signals are not high level signals at the same time;
the signal driving circuit (3) is electrically connected with the interlocking circuit (2) and is used for receiving the control signal processed by the interlocking circuit and controlling the on-off of the upper bridge arm driving circuit and the lower bridge arm driving circuit (4) through the control signal;
and the upper and lower bridge arm driving circuits (4) are electrically connected with the signal driving circuit (3) and are used for controlling the output of the voltage of the power battery (5).
2. The upper and lower bridge arm interlocking drive circuit according to claim 1, wherein the at least one interlock circuit (2) comprises:
a first way of interlocking circuit (21), a second way of interlocking circuit (22) and a third way of interlocking circuit (23);
the first path of interlocking circuit (21), the second path of interlocking circuit (22) and the third path of interlocking circuit (23) are identical in circuit structure, and input ends of the first path of interlocking circuit, the second path of interlocking circuit and the third path of interlocking circuit are respectively and electrically connected with the microcontroller control unit (1).
3. The upper and lower bridge arm interlocking drive circuit according to claim 2, wherein the first interlock circuit (21), the second interlock circuit (22) and the third interlock circuit (23) each comprise:
the first input end of the first AND gate circuit (211) is electrically connected with the microcontroller control unit (1) and is used for receiving a first control signal sent by the microcontroller control unit (1);
a first input end of the second AND gate circuit (212) is electrically connected with the microcontroller control unit (1) and is used for receiving a second control signal sent by the microcontroller control unit (1);
the input end of the first NOT gate circuit (213) is electrically connected with the microcontroller control unit (1) and is used for receiving a first control signal sent by the microcontroller control unit (1), and the output end of the first NOT gate circuit (213) is electrically connected with the second input end of the second AND gate circuit (212);
the input end of the second not gate circuit (214) is electrically connected with the microcontroller control unit (1) and is used for receiving a second control signal sent by the microcontroller control unit (1), and the output end of the second not gate circuit (214) is electrically connected with the second input end of the first and gate circuit (211);
when the first control signal and the second control signal are the same and both are at a high level, the first control signal is input to a first input end of the first and gate circuit (211), the second control signal is input to a first input end of the second and gate circuit (212), the second control signal which is input to a second input end of the first and gate circuit (211) and passes through the second not gate circuit (214) is at a low level, the first control signal which is input to a second input end of the second and gate circuit (212) and passes through the first not gate circuit (213) is at a low level, and the first and gate circuit (211) and the second and gate circuit (212) output low levels at the same time;
when the first control signal and the second control signal are the same and are both low level, the first control signal is input to the first input end of the first and gate circuit (211), the second control signal is input to the first input end of the second and gate circuit (212), the second control signal which is input to the second input end of the first and gate circuit (211) and passes through the second not gate circuit (214) is high level, the first control signal which is input to the second input end of the second and gate circuit (212) and passes through the first not gate circuit (213) is high level, and the first and gate circuit (211) and the second and gate circuit (212) output low level simultaneously;
the first control signal is different from the second control signal, a first input end of the first and gate circuit (211) inputs a high level of the first control signal, when a first input end of the second and gate circuit (212) inputs a low level of the second control signal, a second input end of the first and gate circuit (211) inputs the second control signal passing through the second not gate circuit (214) and is a high level, a second input end of the second and gate circuit (212) inputs the first control signal passing through the first not gate circuit (213) and is a low level, the first and gate circuit (211) outputs a high level, and the second and gate circuit (212) outputs a low level;
the first control signal is different from the second control signal, a first input end of the first and gate circuit (211) inputs a high level of the first control signal, when a first input end of the second and gate circuit (212) inputs a low level of the second control signal, the second control signal which is input through the second not gate circuit (214) by a second input end of the first and gate circuit (211) is low level, the first control signal which is input through the first not gate circuit (213) by a second input end of the second and gate circuit (212) is high level, the first and gate circuit (211) outputs low level, and the second and gate circuit (212) outputs high level.
4. Upper and lower leg interlocked driving circuit according to claim 2, wherein the signal driving circuit (3) comprises:
a first path of signal driving circuit (31), a second path of signal driving circuit (32) and a third path of signal driving circuit (33);
the first signal driving circuit (31), the second signal driving circuit (32) and the third signal driving circuit (33) are all identical in structure;
a first input end and a second input end of the first path of signal driving circuit (31) are respectively and electrically connected with an output of the first path of interlocking circuit (21);
the first input end and the second input end of the second path of signal driving circuit (32) are respectively and electrically connected with the output of the second path of interlocking circuit (22);
the first input end and the second input end of the third path signal driving circuit (33) are respectively and electrically connected with the output of the third path interlocking circuit (23).
5. Upper and lower leg interlocked drive circuit according to claim 4, characterized in that the upper and lower leg drive circuit (4) comprises:
a first upper and lower arm drive circuit (41), a second upper and lower arm drive circuit (42), and a third upper and lower arm drive circuit (43);
the first upper and lower bridge arm driving circuit (41), the second upper and lower bridge arm driving circuit (42) and the third upper and lower bridge arm driving circuit (43) are identical in structure;
a first input end and a second input end of the first upper and lower bridge arm driving circuit (41) are respectively and electrically connected with the output of the first path of signal driving circuit (31);
a first input end and a second input end of the second upper and lower bridge arm driving circuit (42) are respectively and electrically connected with the output of the second path of signal driving circuit (32);
and a first input end and a second input end of the third upper and lower bridge arm driving circuit (43) are respectively and electrically connected with the output of the third signal driving circuit (33).
6. Upper and lower leg interlocked drive circuit according to claim 5,
the first upper and lower bridge arm driving circuit (41), the second upper and lower bridge arm driving circuit (42) and the third upper and lower bridge arm driving circuit (43) are connected in parallel on the power battery (5).
7. Upper and lower leg interlocked drive circuit according to claim 6,
the output end of the first upper and lower bridge arm driving circuit (41) is electrically connected with the U phase of the three-phase motor and is used for controlling the input voltage on the U phase of the three-phase motor through the on-off of the first upper and lower bridge arm driving circuit (41);
the output end of the second upper and lower bridge arm driving circuit (42) is electrically connected with the V phase of the three-phase motor and is used for controlling the input voltage on the V phase of the three-phase motor through the on-off of the second upper and lower bridge arm driving circuit (42);
the output end of the third upper and lower bridge arm driving circuit (43) is electrically connected with the W phase of the three-phase motor and is used for controlling the input voltage on the W phase of the three-phase motor through the on-off of the third upper and lower bridge arm driving circuit (43).
8. The upper-lower bridge arm interlocking drive circuit according to claim 7, wherein each of the first upper-lower bridge arm drive circuit (41), the second upper-lower bridge arm drive circuit (42), and the third upper-lower bridge arm drive circuit (43) includes:
a first insulated gate bipolar transistor and a second insulated gate bipolar transistor;
the grid levels of a first insulated gate bipolar transistor and a second insulated gate bipolar transistor of the first upper bridge arm driving circuit and the first lower bridge arm driving circuit (41) are electrically connected with the output end of the first path of signal driving circuit (31), the source electrode of the first insulated gate bipolar transistor is electrically connected with the positive electrode of the power battery (5), the drain electrode of the first insulated gate bipolar transistor is electrically connected with the U phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor, and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the negative electrode of the power battery (5);
the grid levels of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor of the second upper and lower bridge arm driving circuit (42) are electrically connected with the output end of the second signal driving circuit (32), the source electrode of the first insulated gate bipolar transistor is electrically connected with the positive electrode of the power battery (5), the drain electrode of the first insulated gate bipolar transistor is electrically connected with the V phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor, and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the negative electrode of the power battery (5);
the grid stages of the first insulated gate bipolar transistor and the second insulated gate bipolar transistor of the third upper and lower bridge arm driving circuit (43) are electrically connected with the output end of the third signal driving circuit (33), the source electrode of the first insulated gate bipolar transistor is electrically connected with the positive electrode of the power battery (5), the drain electrode of the first insulated gate bipolar transistor is electrically connected with the W phase of the three-phase motor and the source electrode of the second insulated gate bipolar transistor,
and the drain electrode of the second insulated gate bipolar transistor is electrically connected with the negative electrode of the power battery (5).
9. A three-phase electric machine comprising a drive circuit in which upper and lower arms are interlocked according to any one of claims 1 to 8.
10. A motor vehicle comprising a three-phase electric machine according to claim 9.
CN202210862397.XA 2022-07-21 2022-07-21 Driving circuit with interlocked upper and lower bridge arms, three-phase motor and automobile Pending CN115037194A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210862397.XA CN115037194A (en) 2022-07-21 2022-07-21 Driving circuit with interlocked upper and lower bridge arms, three-phase motor and automobile

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210862397.XA CN115037194A (en) 2022-07-21 2022-07-21 Driving circuit with interlocked upper and lower bridge arms, three-phase motor and automobile

Publications (1)

Publication Number Publication Date
CN115037194A true CN115037194A (en) 2022-09-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210862397.XA Pending CN115037194A (en) 2022-07-21 2022-07-21 Driving circuit with interlocked upper and lower bridge arms, three-phase motor and automobile

Country Status (1)

Country Link
CN (1) CN115037194A (en)

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