CN115036251A - Alignment method of fan-out packaging wafer and fan-out packaging wafer - Google Patents

Alignment method of fan-out packaging wafer and fan-out packaging wafer Download PDF

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CN115036251A
CN115036251A CN202210636457.6A CN202210636457A CN115036251A CN 115036251 A CN115036251 A CN 115036251A CN 202210636457 A CN202210636457 A CN 202210636457A CN 115036251 A CN115036251 A CN 115036251A
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alignment
fan
chips
chip
point
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陈海杰
徐立
潘浩
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Jiangyin Changdian Advanced Packaging Co Ltd
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

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Abstract

The invention relates to the technical field of chip packaging, in particular to an alignment method of a fan-out packaging wafer and the fan-out packaging wafer. The invention determines the position of the alignment point by sacrificing the alignment point chips of several alignment areas and moving the alignment point chips to the middle positions of four adjacent first chips according to the preset moving rule without additional alignment point pattern manufacture.

Description

Fan-out packaging wafer and alignment method thereof
Technical Field
The invention relates to the technical field of chip packaging, in particular to a fan-out packaging wafer and an alignment method thereof.
Background
As the application of wafer fan-out packaging is becoming widespread, different types of product applications and packaging requirements derive, but the chip pitch in the packaging process also varies greatly, for example:
1. the pitch change is many after the chip is redistributed: the chip spacing after redistribution is determined by different packaging positions and sizes;
2. the range of fan-out ratios (chip area/package area) varies widely: a large fan-out ratio means an increase in chip pitch;
3. compared with the original chip spacing which is the size of the wafer scribing channel, the chip spacing can be obviously enlarged after the chips are rearranged.
Meanwhile, in the current advanced packaging process, the wafer fan-out package after the redistribution of the chips needs to be optimized for wiring through a redistribution layer, and a metal conductive layer needs to be formed by utilizing a photoetching process when the redistribution layer is formed.
When a traditional wafer level packaging process is used for a photolithography process of a redistribution layer, as shown in fig. 1, intersection points of scribe lanes 3 between four adjacent chips 1 are often used as exposure alignment points 4, and alignment windows 2 of exposure equipment are used to obtain corresponding exposures to align the exposure alignment points 4 and perform exposure.
When the wafer fan-out package is used for exposure and development in the photolithography process, the chip pitch is significantly enlarged after the redistribution of the chips, but the alignment view field size of the exposure equipment is fixed, and the range of the search alignment mark is fixed, so that an alignment window image as shown in fig. 2 or fig. 3 may appear. As shown in fig. 2, four chips 1 of four package structures are respectively located at four corners of the alignment window 2, and the package structure of the four chips at intervals is very wide, so that the chip distribution after mounting cannot be accurately and quickly determined, and alignment of the fan-out package wafer is difficult; furthermore, as shown in fig. 3, a plurality of, even four, of the four chips 1 of the four package structures are all located outside the range of the alignment window 2, and the alignment window of the exposure apparatus cannot see any chip, so that the specific positions of the package scribe lanes 3 of the four package structures cannot be determined, that is, the distribution of the chips after mounting cannot be determined, and alignment of the fan-out package wafer is difficult.
Disclosure of Invention
The invention provides a fan-out packaging wafer and an alignment method thereof in order to overcome the defects of the prior art.
In order to achieve the above object, an embodiment of the present invention further provides an alignment method for a fan-out package wafer, including:
providing a fan-out packaging wafer substrate, wherein the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips pasted in the first fan-out packaging areas, at least three alignment areas are selected in the fan-out packaging wafer substrate, and the alignment areas at least comprise four adjacent first chips of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
in the chip mounting process, the contraposition point chip is moved and mounted from a preset mounting position of the contraposition fan-out packaging area to the middle positions of four adjacent first chips according to a preset moving rule, so that the actual mounting position of the contraposition point chip is positioned in an exposure equipment contraposition window corresponding to the subsequent process;
and determining the chip mounting position of the whole fan-out packaging wafer substrate according to the position of the alignment point chip on the alignment window of the exposure equipment and a preset moving rule.
Optionally, each alignment region selects two first chips with diagonal angles as alignment point chips, and the two alignment point chips move from the predetermined patch positions of the corresponding alignment fan-out packaging region to the actual patch positions according to a predetermined movement rule and are then mounted.
Optionally, each alignment region selects one first chip as an alignment point chip, and the alignment point chip moves from a predetermined patch position of the corresponding alignment fan-out packaging region to an actual patch position according to a predetermined movement rule and patches the patch.
Optionally, when the predetermined position of the chip is located in the alignment window of the exposure apparatus corresponding to the subsequent photolithography process, the actual position of the chip is still located in the alignment fan-out package region corresponding to the chip after the chip moves to the middle position.
Optionally, when the predetermined placement positions corresponding to the alignment point chips are all located outside the alignment window of the exposure apparatus corresponding to the subsequent photolithography process, during placement, after the alignment point chips move to the middle position, the maximum movement position corresponding to the alignment point chips does not exceed the minimum width area required by the package scribing lane between the four adjacent first fan-out package areas.
Optionally, the first fan-out package region has a plurality of other chips besides the first chip, and the other chips are attached to predetermined attachment positions corresponding to the other chips.
An embodiment of the present invention provides a fan-out package wafer, including:
the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips pasted in the first fan-out packaging areas;
the fan-out packaging wafer substrate is at least provided with three alignment areas, and the alignment areas at least comprise four adjacent first chips of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
and in the chip mounting process, the contraposition point chip is moved and mounted from the preset mounting position of the contraposition fan-out packaging area to the middle positions of four adjacent first chips according to a preset moving rule, so that the actual mounting position of the contraposition point chip is positioned in an exposure equipment contraposition window corresponding to the subsequent process, and the rest first chips are mounted at the preset mounting positions corresponding to the first fan-out packaging area.
Optionally, each alignment region selects two first chips with diagonal corners as alignment point chips, and the two alignment point chips move and mount from the predetermined mounting positions of the corresponding alignment fan-out packaging regions to the middle positions of the four adjacent first chips according to a predetermined movement rule.
Optionally, one first chip is selected from each alignment area as an alignment point chip, and the alignment point chip moves and mounts the chip from a predetermined mounting position of the corresponding alignment fan-out packaging area to the middle position of four adjacent first chips according to a predetermined movement rule.
Optionally, when all or part of the predetermined patch positions corresponding to the alignment point chips are located in the alignment window of the exposure apparatus corresponding to the subsequent photolithography process, the actual patch positions of the alignment point chips are located in the alignment fan-out packaging regions corresponding to the alignment point chips.
Optionally, when all the predetermined patch positions of the alignment point chip corresponding to the first fan-out packaging regions are located outside the alignment window of the exposure apparatus corresponding to the subsequent photolithography process, the actual patch positions corresponding to the alignment point chip do not exceed the minimum width area required by the packaging scribing channel between the four adjacent first fan-out packaging regions.
Optionally, the first fan-out package region has a plurality of other chips besides the first chip, and the other chips are attached to predetermined attachment positions corresponding to the other chips.
In conclusion, the beneficial effects of the invention are as follows:
the method comprises the steps of selecting at least three alignment areas on a fan-out packaging wafer substrate, wherein the alignment areas at least comprise four adjacent first chips of 2x2, each alignment area selects at least one first chip as an alignment point chip, in a chip mounting process, the alignment point chips are moved from a preset mounting position to the middle positions of the four adjacent first chips according to a preset moving rule, so that the actual mounting positions of the alignment point chips are located in an alignment window of exposure equipment corresponding to a subsequent process, and the chip mounting positions of the whole fan-out packaging wafer substrate are arranged according to the positions of the alignment point chips on the alignment window of the exposure equipment and the preset moving rule. According to the invention, the alignment point chips of several alignment areas are sacrificed, and the alignment point chips are moved to the middle positions of four adjacent first chips according to the preset moving rule to determine the alignment point positions, so that the chip mounting positions of the whole fan-out packaging wafer substrate can be determined, the rows and the columns of the chips cannot be found by mistake when exposure equipment carries out coarse alignment, the method is suitable for photoetching by using the existing photoetching machine, no additional alignment point pattern is required to be manufactured, and the cost is lower.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a photolithography alignment structure of a conventional wafer level packaging process;
FIGS. 2 and 3 are schematic diagrams of a photolithography alignment structure in a photolithography process based on a wafer fan-out package according to the prior art;
FIG. 4 is a flowchart illustrating a method for photolithographic alignment of a fan-out package wafer according to an embodiment of the present invention;
fig. 5-10 are schematic structural diagrams of fan-out package wafers according to embodiments of the invention.
Detailed Description
The present invention will be described in further detail below with reference to specific examples in order to facilitate understanding by those skilled in the art.
The embodiment of the present invention first provides a photolithography alignment method for a fan-out package wafer, please refer to fig. 4, which is a flow diagram of the photolithography alignment method, including:
step S100, providing a fan-out packaging wafer substrate, wherein the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips mounted in the first fan-out packaging areas, at least three alignment areas are selected in the fan-out packaging wafer substrate, and the alignment areas at least comprise four adjacent first chips of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
step S200, selecting at least one first chip as a contraposition point chip in each contraposition area, using a first fan-out packaging area corresponding to the contraposition point chip as a contraposition fan-out packaging area, and moving and mounting the contraposition point chip from a preset mounting position of the contraposition fan-out packaging area to the middle positions of four adjacent first chips according to a preset moving rule in a chip mounting process to enable the actual mounting position of the contraposition point chip to be positioned in a contraposition window of exposure equipment corresponding to a subsequent process;
and step S300, determining the position of the alignment point and the chip mounting position of the whole fan-out packaging wafer substrate according to the position of the alignment point chip on the alignment window of the exposure equipment and a preset moving rule.
Specifically, step S100 is executed, please refer to fig. 5 and 8, in which fig. 5 is a schematic structural diagram of the fan-out package wafer as a whole, and fig. 8 is a schematic structural diagram of four adjacent first chips in one alignment area and four corresponding adjacent first fan-out package areas.
In this embodiment, the fan-out package wafer substrate is a substrate for fan-out package of a subsequent chip, and the fan-out package wafer substrate may be one of a package carrier, a glass carrier, a blank semiconductor wafer, and the like.
In the wafer fan-out packaging process, chip mounting is carried out at a preset position on the surface of a fan-out packaging wafer substrate, and chip plastic packaging is carried out on the surface of the fan-out packaging wafer substrate and the surface of a chip to form a chip packaging structure; and then stripping the fan-out packaging wafer substrate from the chip packaging structure, and forming a redistribution layer on the stripping surface corresponding to the chip packaging structure, wherein a metal pattern is required to be formed by utilizing a photoetching process when the redistribution layer is formed.
The photolithography process needs to perform rough alignment on the alignment points, and if the wafer fan-out package is not used, the photolithography process is performed to form the redistribution layer, as shown in fig. 1, scribe lane intersections between four adjacent chips are often used as the alignment points for the rough alignment. However, with the diversification of the layout of the fan-out package wafer, the positions of the chips on the package structure are different and have different fan-out ratios, which causes the pitch to change more and become larger after the redistribution of the chips, and even larger than the size of the alignment window of the exposure equipment corresponding to the photolithography process (as shown in fig. 3), that is, no chip can be found in the alignment window of the existing exposure equipment, so that the alignment cannot be performed accordingly, and the alignment error is easily caused by the above method, which causes the alignment failure.
For this reason, in this embodiment, the fan-out package wafer substrate 10 is divided into a plurality of first fan-out package regions 20, one first fan-out package region 20 is used to form one fan-out package structure, and the size of the first fan-out package region 20 is larger than that of the first chip to be mounted.
When coarse alignment is carried out, at least three alignment points are needed for alignment of the fan-out packaging wafer so as to determine chip distribution after chip mounting. Therefore, at least three alignment areas 15 are selected in the fan-out package wafer substrate, and each alignment area 15 corresponds to one alignment point.
As shown in fig. 5 and 6, a dashed box shows one alignment area 15, and six adjacent first fan-out package areas 20 and six adjacent predetermined patch positions 31 of the first chip are included in the alignment area 15.
In other embodiments, each alignment area includes at least four adjacent first fan-out package areas 20 of 2x2 and four adjacent first chips of 2x 2.
In the following description, four adjacent first chips 30 are respectively b, c, d, e, and one first chip 30 corresponds to one first fan-out package region 20. Four first chips 30 have corresponding predetermined patch locations 31 within corresponding first fan-out package areas 20.
In the present embodiment, as shown in fig. 6 to 10, one first fan-out package region 20 is used for packaging only one first chip 30.
In other embodiments, a first fan-out package region encapsulates other chips in addition to a first chip. The first chip and the other chips may be the same in chip type and size or different in chip type and size. The first chip differs from the other chips only in that: in an alignment area of the fan-out packaging wafer substrate, at least one first chip serving as an alignment chip moves to the middle positions of four adjacent first chips, so that the actual chip mounting position of the alignment chip is located in an alignment window of exposure equipment corresponding to a subsequent photoetching process.
Step S200 is executed, as shown in fig. 6 to 8, each alignment area at least has four adjacent first chips, at least one first chip is selected as an alignment point chip 30 ', a first fan-out packaging area corresponding to the alignment point chip 30' is selected as an alignment fan-out packaging area 20 ', in the chip mounting process, the alignment point chip 30' is moved from a predetermined mounting position 31 of the alignment fan-out packaging area 20 'to the middle position of the four adjacent first chips according to a predetermined moving rule and is mounted, so that an actual mounting position 32' of the alignment point chip is located in an alignment window of the exposure equipment corresponding to the subsequent process, and the remaining first chips 30 are still mounted at the predetermined mounting positions 31 corresponding to the first fan-out packaging area 20.
Fig. 6 is a schematic structural diagram of a predetermined chip position of a first chip including the pair of site chips b and e in the alignment area, fig. 7 is a schematic structural diagram of an actual chip position of the first chip including the pair of site chips b and e in the alignment area, and fig. 8 is a schematic structural diagram of a moving position in the first chip mounting process.
The preset patch position of the alignment point chip corresponding to the first fan-out packaging region can be located in the alignment window view of the exposure equipment corresponding to the subsequent photoetching process, and can also be located outside the alignment window view of the exposure equipment corresponding to the subsequent photoetching process.
In the present embodiment, as shown in fig. 8, the pair of dot chips are two first chips, and the pair of dot chips b and e are diagonally arranged. When all or part of the preset patch positions 31 of the alignment point chips b and e corresponding to the first fan-out packaging region are located in the alignment window 40 of the exposure equipment corresponding to the subsequent photoetching process, and the preset patch positions are moved to the middle position according to the preset moving rule, the actual patch positions 32 of the alignment point chips b and e are still located in the alignment fan-out packaging region 20' corresponding to the alignment point chips.
The predetermined movement rule may be a fixed value, or a movement rule determined according to the position and size of the first chip in the first fan-out package region 20.
In the embodiment shown in fig. 9, since the predetermined patch position 31 and the actual patch position 32 of the contraposition chip are all located in the contraposition window 40 of the exposure apparatus, the contraposition chip b and e can be used to determine the contraposition by moving only a specific position. As shown in table 1, the dimensions of four adjacent first fan-out package regions and four adjacent first chips.
Figure BDA0003682291990000071
Figure BDA0003682291990000081
TABLE 1
The maximum moving distance of the contraposition point chip b in the X-axis direction is (L-X)/2- (O '-O), the minimum moving distance is 2um, the maximum moving distance of the contraposition point chip b in the Y-axis direction is (W-Y)/2+ (P' -P), and the minimum moving distance is 2 um.
The maximum moving distance of the contraposition point chip e in the X-axis direction is (L-X)/2+ (O '-O), the minimum moving distance is 2um, the maximum moving distance of the contraposition point chip b in the Y-axis direction is (W-Y)/2- (P' -P), and the minimum moving distance is 2 um.
The minimum moving distance can be adjusted according to different processes.
In other embodiments, as shown in fig. 10, when all the predetermined patch positions 31 corresponding to the pair of dot chips 30 'are located outside the alignment window 40 of the exposure apparatus corresponding to the subsequent photolithography process, and the pair of dot chips 30' are moved to the middle position, the maximum moving position of the predetermined patch positions corresponding to the pair of dot chips 30 'does not exceed the minimum width area required by the package scribe lane between the four adjacent first fan-out package regions, and the actual patch positions corresponding to the pair of dot chips 30' do not exceed the minimum width area required by the package scribe lane between the four adjacent first fan-out package regions.
The maximum moving distance of the contraposition point chip b in the X-axis direction is (L-X + K-K ')/2- (O' -O), the minimum moving distance is (L-X + K-M)/2- (O '-O), the maximum moving distance of the contraposition point chip b in the Y-axis direction is (W-Y + K-K')/2 + (P '-P), and the minimum moving distance is (W-Y + K-N)/2+ (P' -P).
The maximum moving distance of the contraposition point chip e in the X-axis direction is (L-X + K-K ')/2 + (O' -O), the minimum moving distance is (L-X + K-M)/2+ (O '-O), the maximum moving distance of the contraposition point chip b in the Y-axis direction is (W-Y + K-K')/2- (P '-P), and the minimum moving distance is (W-Y + K-N)/2- (P' -P).
Because the preset chip positions corresponding to the alignment point chips are all positioned outside the alignment window 40 of the exposure equipment corresponding to the subsequent photoetching process, the preset moving distance of the alignment point chips needs to be increased, and even if the actual chip positions of the alignment point chips are positioned in the preset scribing channel area (namely the area with the width of K), the subsequent scribing and cutting are not influenced as long as the minimum width area (namely the area with the width of K') required by the packaging finished product scribing channel is not covered.
In this embodiment, in the chip mounting process, the alignment point chip is moved to the middle positions of four adjacent first chips according to a predetermined movement rule, so that the actual mounting position of the alignment point chip is located in the alignment window of the exposure apparatus corresponding to the subsequent photolithography process, but other first chips not serving as the alignment point chip are still normally mounted at the predetermined mounting position, and the fan-out package structure corresponding to the first chip can still normally operate.
The fan-out packaging structure comprises a fan-out packaging wafer, a plurality of alignment point chips, a plurality of fan-out packaging structures and a plurality of alignment point chips.
In other embodiments, when the first chip and the other chips are simultaneously mounted in the first fan-out packaging region, the alignment fan-out packaging region is also simultaneously mounted with the alignment point chip and the other chips, and only the alignment point chip is moved to adjust the position of the mounting, while the other chips in the alignment fan-out packaging region are not moved and are still mounted at the corresponding predetermined mounting positions.
In other embodiments, when the first chip and the other chips are simultaneously mounted in the first fan-out packaging region, only the alignment point chip is mounted in the alignment fan-out packaging region, and the other chips are not mounted, so that the alignment point chip after moving is prevented from overlapping with the other chips.
In this embodiment, the normal first chip is used for the alignment point chip 30' of the alignment fan-out package region for mounting, and in other embodiments, the alignment point chip of the alignment fan-out package region may also be a waste chip or a blank chip for mounting.
And executing the step S300, and determining the position of the alignment point and the chip mounting position of the whole fan-out packaging wafer substrate according to the position of the alignment point chip on the alignment window of the exposure equipment and the preset moving rule.
In this embodiment, the two aligning point chips 30' move to the middle positions of the four adjacent first chips by different distances, and move according to the predetermined movement rule, the middle positions of the two aligning point chips b and e are the center positions of the aligning points, and the chip mounting positions of the whole fan-out package wafer substrate are determined by using the positions of the aligning points.
In other embodiments, one corner of two alignment point chips can be used as an alignment point.
In the embodiment, the alignment point is determined by using the alignment point chip, and the chip layout position of the fan-out package wafer is roughly positioned by using the alignment point, so that the actual position of the alignment point can be set within the range of the alignment window of the exposure equipment as required, and no special limitation is imposed.
In other embodiments, the distance that two of the alignment point chips respectively move to the middle positions of four adjacent first chips may also be the same, and the position of the alignment point may also be determined by obtaining the size of the alignment point chip, the size of the first fan-out packaging region, the size of the scribe lane, the position of the predetermined patch position of the alignment point chip in the first fan-out packaging region, and the distance that the alignment point chip moves to the middle position.
In other embodiments, only one alignment point chip corresponding to one alignment area may be provided, and only one alignment point chip in the four first chips moves to the middle position of the four adjacent first chips, and when the position of the alignment point chip in the first fan-out package area, the position of the predetermined pasting position of the alignment point chip in the first fan-out package area, the distance of the alignment point chip moving to the middle position, and the accurate position of the alignment point chip in the alignment window of the exposure device are obtained, the position of the alignment point can also be determined.
In other embodiments, more than 2 alignment point chips corresponding to one alignment area may be used to position the alignment point chips by adjusting the positions of the alignment point chips.
An embodiment of the present invention further provides a fan-out package wafer, as shown in fig. 5 to 8, including:
the fan-out packaging wafer substrate 10 is provided with a plurality of first fan-out packaging areas 20 and first chips 30 mounted in the first fan-out packaging areas;
the fan-out package wafer substrate 10 at least has three alignment regions 15 therein, and the alignment regions 15 at least include four adjacent first chips 30 of 2 × 2 and four adjacent first fan-out package regions 20 corresponding to each first chip;
at least one first chip in each alignment area is used as an alignment point chip 30 ', a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area 20 ', in the chip mounting process, the alignment point chip 30 ' is moved and mounted from a preset mounting position 31 ' of the alignment fan-out packaging area to the middle position of four adjacent first chips according to a preset moving rule, so that the actual mounting position of the alignment point chip 30 ' is located in an exposure equipment alignment window 40 corresponding to the subsequent process, and the rest first fan-out chips 30 are mounted at the preset mounting positions 31 corresponding to the first fan-out packaging areas.
In the present embodiment, as shown in fig. 8 and 9, the dot chips 30' are two first chips, and the dot chips b and e are diagonally arranged. When all or part of the preset patch positions 31 of the alignment fan-out packaging regions 20 ' corresponding to the alignment chips b and e are located in the alignment windows 40 of the exposure equipment corresponding to the subsequent lithography process, and the preset patch positions are moved to the middle positions according to the preset moving rule, the actual patch positions of the alignment chips b and e are still located in the alignment fan-out packaging regions 20 ' corresponding to the alignment chips 30 '.
In one embodiment, the predetermined movement rule is specifically:
the maximum moving distance of the contraposition point chip b in the X-axis direction is (L-X)/2- (O '-O), the minimum moving distance is 2um, the maximum moving distance of the contraposition point chip b in the Y-axis direction is (W-Y)/2+ (P' -P), and the minimum moving distance is 2 um.
The maximum moving distance of the contraposition point chip e in the X-axis direction is (L-X)/2+ (O '-O), the minimum moving distance is 2um, the maximum moving distance of the contraposition point chip b in the Y-axis direction is (W-Y)/2- (P' -P), and the minimum moving distance is 2 um.
In other embodiments, as shown in fig. 10, when all the predetermined patch positions 31 'corresponding to the first fan-out package regions of the alignment chip 30' are located outside the alignment window 40 of the exposure apparatus corresponding to the subsequent photolithography process, after the alignment chip 30 'moves to the middle position, the maximum moving position of the predetermined patch positions corresponding to the alignment chip does not exceed the minimum width region (i.e., the region with the width K') required by the package scribe lane between four adjacent first fan-out package regions.
The maximum moving distance of the contraposition chip b in the X-axis direction is (L-X + K-K ')/2- (O' -O), the minimum moving distance is (L-X + K-M)/2- (O '-O), the maximum moving distance of the contraposition chip b in the Y-axis direction is (W-Y + K-K')/2 + (P '-P), and the minimum moving distance is (W-Y + K-N)/2+ (P' -P).
The maximum moving distance of the contraposition point chip e in the X-axis direction is (L-X + K-K ')/2 + (O' -O), the minimum moving distance is (L-X + K-M)/2+ (O '-O), the maximum moving distance of the contraposition point chip b in the Y-axis direction is (W-Y + K-K')/2- (P '-P), and the minimum moving distance is (W-Y + K-N)/2- (P' -P).
In other embodiments, the first fan-out package region has a plurality of other chips besides the first chip, and the chip types and sizes of the first chip and the other chips may be the same or different. The first chip differs from the other chips only in that: in an alignment area of the fan-out packaging wafer substrate, at least one first chip is used as an alignment point chip to move to the middle positions of four adjacent first chips, so that the actual chip mounting position of the alignment point chip is located in an alignment window of exposure equipment corresponding to a subsequent photoetching process.
In other embodiments, when the first chip and the other chips are simultaneously mounted in the first fan-out packaging region, only the alignment point chip is mounted in the alignment fan-out packaging region, and the other chips are not mounted, so that the alignment point chip after moving is prevented from overlapping with the other chips.
In this embodiment, the normal first chip is used for chip mounting on the alignment point chip, and in other embodiments, a waste chip or a blank chip may be selected for chip mounting.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.

Claims (12)

1. An alignment method for a fan-out package wafer is characterized by comprising the following steps:
providing a fan-out packaging wafer substrate, wherein the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips pasted in the first fan-out packaging areas, at least three alignment areas are selected in the fan-out packaging wafer substrate, and the alignment areas at least comprise four adjacent first chips of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
in the chip mounting process, the contraposition point chip is moved and mounted from a preset mounting position of the contraposition fan-out packaging area to the middle positions of four adjacent first chips according to a preset moving rule, so that the actual mounting position of the contraposition point chip is positioned in an exposure equipment contraposition window corresponding to the subsequent process;
and determining the position of the alignment point and the chip patch position of the whole fan-out packaging wafer substrate according to the position of the alignment point chip on the alignment window of the exposure equipment and a preset moving rule.
2. The alignment method of the fan-out package wafer according to claim 1, wherein each alignment area selects two first chips with diagonal corners as alignment point chips, and the two alignment point chips are moved from the predetermined patch positions of the corresponding alignment fan-out package area to the middle positions of the four adjacent first chips according to a predetermined moving rule and are then patch-mounted.
3. The alignment method of the fan-out package wafer according to claim 1, wherein each alignment area selects one first chip as an alignment point chip, and the alignment point chip moves and attaches the chip from a predetermined attaching position of the corresponding alignment fan-out package area to a middle position of four adjacent first chips according to a predetermined moving rule.
4. The alignment method of the fan-out package wafer according to claim 1, wherein when the predetermined placement positions corresponding to the alignment chips are located in the alignment windows of the exposure equipment corresponding to the subsequent photolithography process, the actual placement positions of the alignment chips are still located in the alignment fan-out package regions corresponding to the alignment chips after the alignment chips are moved to the middle position during placement.
5. The method for aligning the fan-out package wafer according to claim 1, wherein when the predetermined placement positions corresponding to the alignment point chips are all located outside an alignment window of an exposure apparatus corresponding to a subsequent photolithography process, during placement, after the alignment point chips move to the middle position, the maximum movement position corresponding to the alignment point chips does not exceed a minimum width area required by a package scribe lane between four adjacent first fan-out package areas.
6. The photolithographic alignment method for the fan-out package wafer of claim 1, wherein the first fan-out package region has a number of other chips besides the first chip, and the other chips are attached to predetermined attaching positions corresponding to the other chips.
7. A fan-out package wafer, comprising:
the fan-out packaging wafer substrate is provided with a plurality of first fan-out packaging areas and first chips mounted in the first fan-out packaging areas;
the fan-out packaging wafer substrate is at least provided with three alignment areas, and the alignment areas at least comprise four adjacent first chips of 2x2 and four adjacent first fan-out packaging areas corresponding to each first chip;
at least one first chip of each alignment area is used as an alignment point chip, a first fan-out packaging area corresponding to the alignment point chip is used as an alignment fan-out packaging area, in the chip mounting process, the alignment point chip is moved and mounted to the middle positions of four adjacent first chips from the preset mounting position of the alignment fan-out packaging area according to a preset moving rule, the actual mounting position of the alignment point chip is located in an exposure equipment alignment window corresponding to the subsequent process, and the rest first chips are mounted to the preset mounting position corresponding to the first fan-out packaging area.
8. The fan-out package wafer of claim 7, wherein each alignment area selects two first chips with diagonal corners as alignment point chips, and the two alignment point chips are moved from the predetermined placement positions of the corresponding alignment fan-out package area to actual placement positions according to a predetermined movement rule and are placed on the actual placement positions.
9. The fan-out package wafer of claim 7, wherein each alignment area selects one first chip as an alignment point chip, and the alignment point chip is moved from a predetermined placement position of the corresponding alignment fan-out package area to an actual placement position according to a predetermined moving rule and is placed on the actual placement position.
10. The fan-out package wafer of claim 7, wherein when all or part of the predetermined placement positions corresponding to the aligned chips are located in the alignment window of the exposure apparatus corresponding to the subsequent photolithography process, the actual placement positions of the aligned chips are located in the alignment fan-out package region corresponding to the aligned chips.
11. The fan-out package wafer of claim 7, wherein when all of the predetermined placement positions corresponding to the first fan-out package regions of the alignment point chip are located outside the alignment window of the exposure apparatus corresponding to the subsequent photolithography process, the actual placement positions corresponding to the alignment point chip do not exceed a minimum width region required by a package scribe lane between four adjacent first fan-out package regions.
12. The fan-out package wafer of claim 7, wherein the first fan-out package region has a number of other dies in addition to the first die, the other dies being attached to predetermined attachment locations corresponding to the other dies.
CN202210636457.6A 2022-06-07 2022-06-07 Alignment method of fan-out packaging wafer and fan-out packaging wafer Pending CN115036251A (en)

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