CN115035941B - Efuse unit structure and memory - Google Patents
Efuse unit structure and memory Download PDFInfo
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- CN115035941B CN115035941B CN202210964664.4A CN202210964664A CN115035941B CN 115035941 B CN115035941 B CN 115035941B CN 202210964664 A CN202210964664 A CN 202210964664A CN 115035941 B CN115035941 B CN 115035941B
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- fuse
- nmos transistor
- nmos
- nmos tube
- efuse
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
Abstract
The invention provides an efuse unit structure and a memory, belonging to the technical field of semiconductors, wherein the efuse unit structure comprises a first NMOS tube, a second NMOS tube and a fuse, wherein the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are both connected with a power supply, the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with one end of the fuse, and the other end of the fuse is grounded, so that the stability of the fuse is better.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to an efuse cell structure and a memory.
Background
efuse belongs to a one-time programmable memory (OTP), information is stored by whether a fuse wire is fused or not according to an electron transfer (EM) theory by the efuse technology, the resistance of the fuse wire made of a polycrystalline silicon material is very small before the fuse wire is fused, the resistance can be regarded as infinite after continuous high current is fused, and the broken state of the fuse wire is permanently maintained. The efuse technology is widely used for a redundancy circuit to solve the problems of chip failure and the like, and can replace a small-capacity one-time programmable memory.
As shown in FIG. 1, the conventional efuse cell includes an NMOS transistor T and a fuse 1, wherein a drain D of the NMOS transistor T is connected to one end of the fuse 1, the other end of the fuse 1 is connected to a power supply VDD, and a source S of the NMOS transistor T is grounded. Before programming, the fuse 1 in the efuse cell structure is not blown, that is, the fuse is in a conducting state, at this time, the input voltage of the gate G of the NMOS transistor T is less than or equal to 0v, the NMOS transistor T is not turned on, and the resistance of the fuse 1 made of polysilicon is small, which is about 100 Ω. During programming, under normal conditions, the input voltage of the gate G of the NMOS transistor T is stable, and a larger voltage is provided, so that the fuse 1 flows through a larger fusing current, and the fuse 1 is fully fused by the larger fusing current, and the fusing effect of the fuse 1 is good, at this time, the resistance of the fuse 1 is very large, for example, compared with a conductive fuse, the resistance of the fuse 1 at this time is infinite; however, during programming, due to factors such as unstable input voltage of the gate G of the NMOS transistor T or short pulse time of the input voltage of the gate G of the NMOS transistor T, the blowing current flowing through the fuse 1 is small, and the fuse 1 is not completely blown, specifically, as can be seen from the area surrounded by the rectangular frame in fig. 2, the resistance value of the fuse 1 is small due to insufficient blowing of the fuse 1, and is only 100 to 1000 times of the resistance value of the fuse 1 when the fuse is turned on. Compared with the resistance value of a resistor which is infinite, the resistance value of the fuse 1 is smaller, and leakage current passes through the fuse 1 when data is read, so that the efuse unit has the risk of reading failure.
Disclosure of Invention
The present invention is directed to an efuse cell structure and a memory, which can solve the risk of read failure caused by poor fuse blowing effect.
In order to solve the above problems, the present invention provides an efuse unit structure, which includes a first NMOS transistor, a second NMOS transistor, and a fuse, wherein a drain of the first NMOS transistor and a drain of the second NMOS transistor are both connected to a power supply, a source of the first NMOS transistor is connected to a gate of the second NMOS transistor, a source of the second NMOS transistor is connected to one end of the fuse, and another end of the fuse is grounded.
Optionally, the first NMOS transistor and the second NMOS transistor satisfy the following formula:
W2/L2＞W1/L1；
wherein W1 is the channel width of the first NMOS transistor; l1 is the channel length of the first NMOS tube; w2 is the channel width of the second NMOS tube; and L2 is the channel length of the second NMOS tube.
Optionally, the first NMOS transistor and the second NMOS transistor satisfy the following formula:
W2＞W1；
wherein W1 is the channel width of the first NMOS tube; w2 is the channel width of the second NMOS tube.
Optionally, when the second NMOS transistor is not turned on, the fuse is in a conducting state.
Further, the resistance value of the fuse in a conducting state is near 100 Ω.
Optionally, after the second NMOS transistor is turned on, the fuse is in a blown state.
Further, the resistance value of the fuse in the blown state is more than 1E7 omega.
Optionally, the fuse is made of a polysilicon material.
On the other hand, the invention also provides a memory, which comprises the efuse unit structure and a control circuit, wherein the control circuit is connected with the grid electrode of the first NMOS tube and provides starting voltage for the grid electrode of the first NMOS tube.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides an efuse unit structure and a memory, wherein the efuse unit structure comprises a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube and a fuse wire, wherein the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are both connected with a power supply, the source electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube is connected with one end of the fuse wire, and the other end of the fuse wire is grounded. According to the invention, the source electrode of the second NMOS tube is connected with one end of the fuse wire, the other end of the fuse wire is grounded, so that the stability of the fuse wire is better, and the working range of the second NMOS tube is always in a saturation region during programming, so that the current flowing through the fuse wire is ensured to be larger, the fuse wire can be fully fused, and the fusing effect of the fuse wire is good; and the second NMOS tube is controlled to be opened through the first NMOS tube, so that the influence of the input voltage fluctuation provided by the grid electrode of the first NMOS tube by a control circuit is reduced, the influence of the input voltage on the fuse fusing effect is controlled, and the sensitivity is high. In addition, only one NMOS tube is added, so that the circuit change of the efuse unit structure is small.
Drawings
FIG. 1 is a circuit diagram of an efuse cell structure;
FIG. 2 is a schematic diagram of a fuse with poor fusing effect;
fig. 3 is a circuit diagram of an efuse cell structure according to an embodiment of the present invention.
Description of reference numerals:
1. 10-fuse.
Detailed Description
An efuse cell structure and a memory according to the present invention will be described in further detail below. The present invention will now be described in more detail with reference to the appended drawings, in which preferred embodiments of the invention are shown, it being understood that one skilled in the art can modify the invention herein described while still achieving the advantageous effects of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
Fig. 3 is a circuit diagram of an efuse cell structure according to this embodiment. As shown in fig. 3, the efuse unit structure provided by this embodiment includes a first NMOS tube T1, a second NMOS tube T2 and a fuse 10, a drain D1 of the first NMOS tube T1 and a drain D2 of the second NMOS tube T2 are both connected to a power supply VDD, a source S1 of the first NMOS tube T1 is connected to a gate G2 of the second NMOS tube T2, a source S2 of the second NMOS tube T2 is connected to one end of the fuse 10, and another end of the fuse 10 is grounded GND. The gate G1 of the first NMOS transistor T1 is used to connect an external circuit to which an input voltage can be supplied. The voltage supplied by the power supply VDD is relatively large, for example, greater than 4V, specifically, 5V, and the fuse 10 is made of polysilicon.
In this embodiment, the fuse 10 is located between the source S2 of the second NMOS transistor T2 and the ground GND, so that when the second NMOS transistor T2 is not turned on, no current flows through the fuse 10, and the voltage near the fuse 10 is stable and always at a low level. Compared with an NMOS tube in the prior art, the NMOS tube is added, so that the circuit change of the efuse unit structure is small.
When the input voltage of the gate G1 of the first NMOS transistor T1 is less than or equal to 0V, the first NMOS transistor T1 is turned off, the second NMOS transistor T2 is turned off, no current flows through the fuse 10, and at this time, the fuse 10 is in a conducting state, because the fuse 10 is made of polysilicon, the resistance of the fuse 10 in the conducting state is very small, and the resistance of the fuse 10 is, for example, near 100 Ω, specifically, 132 Ω, 133 Ω, and the like.
When the input voltage of the gate G1 of the first NMOS transistor T1 is (0, vth), that is, the input voltage of the gate G1 of the first NMOS transistor T1 is greater than 0 and less than the threshold voltage Vth, the first NMOS transistor T1 is not turned on, so that the input voltage of the gate G2 of the second NMOS transistor T2 is at a low level, and therefore, the second NMOS transistor T2 is not turned on at this time, the fuse 10 is still in a conducting state, that is, the resistance of the fuse 10 is still small.
When the input voltage of the gate G1 of the first NMOS transistor T1 is greater than the threshold voltage Vth, the first NMOS transistor T1 is turned on, and at this time, the input voltage of the gate G2 of the second NMOS transistor T2 is rapidly increased to the voltage provided by the power supply VDD, that is, when the first NMOS transistor T1 is turned on, the drain D1 of the first NMOS transistor T1, the drain D2 of the second NMOS transistor T2, and the gate G2 of the second NMOS transistor T2 are shorted, so that the gate G2 of the second NMOS transistor T2 is rapidly increased from 0V to the voltage value of the drain D2 of the second NMOS transistor T2, so that the second NMOS transistor T2 is turned on, and at this time, since the input voltage of the gate G2 of the second NMOS transistor T2 is relatively large, the current flowing through the fuse 10 is rapidly increased, and the fuse 10 is in a blown state.
Since the larger the gate input voltage of the NMOS transistor, the larger the drain-source voltage VDS of the NMOS transistor, the larger the current ID flowing through the drain of the NMOS transistor, that is, the larger the blowing current flowing through the fuse 10. Therefore, in this embodiment, when the second NMOS transistor T2 is turned on, the input voltage VG of the gate G2 of the second NMOS transistor T2 is rapidly increased to the voltage (e.g., 5V) provided by the power supply VDD, the drain-source voltage VDS of the second NMOS transistor T2 is also the voltage (e.g., 5V) provided by the power supply VDD, so that the operating range of the second NMOS transistor T2 is always in the saturation region, the current of the drain D2 of the second NMOS transistor T2 is larger, and the blowing current flowing through the fuse 10 is larger, so that the fuse 10 can be fully blown under a larger blowing current, that is, the fuse 10 is in a fully blown state, and the resistance value of the fuse 10 in the fully blown state is very large, for example, close to infinity, in this embodiment, the resistance value of the fuse 10 is, for example, above 1E7 Ω.
Compared with the fuse located between the power supply VDD and the drain of the NMOS transistor in the prior art, the fuse 10 of this embodiment is connected between the source S2 of the second NMOS transistor T2 and the ground GND, and the stability of the fuse 10 of this embodiment is better. Meanwhile, in the embodiment, the first NMOS transistor T1 controls the second NMOS transistor T2 to be turned on, when the input voltage provided by the external circuit is unstable (i.e., fluctuates), the first NMOS transistor T1 is only affected whether to be turned on, and the second NMOS transistor T2 is indirectly affected whether to be turned on, which does not affect the fusing effect of the fuse 10, and meanwhile, since the first NMOS transistor T1 is only responsible for turning on the second NMOS in this embodiment, the input voltage provided by the external circuit can fully fuse the fuse 10 only by being greater than the threshold voltage Vth, and does not need a large input voltage, so that the efuse unit structure has high sensitivity.
The first NMOS transistor T1 and the second NMOS transistor T2 satisfy the following formula:
W2/L2＞W1/L1；-------（1）
W2＞W1；---------------（2）
wherein W1 is the channel width of the first NMOS transistor T1; l1 is the channel length of the first NMOS tube T1; w2 is the channel width of the second NMOS transistor T2; and L2 is the channel length of the second NMOS tube T2.
Satisfying the above formula (1) enables the fuse 10 of the efuse cell structure to obtain a larger blowing current. The above formula (2) is satisfied, that is, the channel width W1 of the first NMOS transistor T1 is designed to be smaller, which can reduce the chip area increased by the first NMOS transistor T1.
With reference to fig. 3, the present embodiment further provides a memory, which includes a control circuit and an efuse unit structure, where the efuse unit structure includes a first NMOS transistor T1, a second NMOS transistor T2 and a fuse 10, a drain D1 of the first NMOS transistor T1 and a drain D2 of the second NMOS transistor T2 are both connected to a power supply VDD, a source S1 of the first NMOS transistor T1 is connected to a gate G2 of the second NMOS transistor T2, a source S2 of the second NMOS transistor T2 is connected to one end of the fuse 10, and another end of the fuse 10 is grounded to GND. The gate G1 of the first NMOS transistor T1 is connected to the control circuit (not shown), and the control circuit provides an input voltage for turning on the first NMOS transistor T1 to the gate G1 of the first NMOS transistor T1. The control circuit may be a PWM (Pulse Width Modulation) circuit to provide a Pulse voltage signal (i.e., a square wave voltage signal) to the gate G1 of the first NMOS transistor T1, where the Pulse voltage signal includes a high level and a low level, the gate G1 of the first NMOS transistor T1 is turned on at the high level, and the gate G1 of the first NMOS transistor T1 is turned off at the low level.
In summary, the present invention provides an efuse cell structure and a memory, where the efuse cell structure includes a first NMOS transistor, a second NMOS transistor, and a fuse, a drain of the first NMOS transistor and a drain of the second NMOS transistor are both connected to a power supply, a source of the first NMOS transistor is connected to a gate of the second NMOS transistor, a source of the second NMOS transistor is connected to one end of the fuse, and another end of the fuse is grounded. According to the invention, the source electrode of the second NMOS tube is connected with one end of the fuse wire, and the other end of the fuse wire is grounded, so that the stability of the fuse wire is better, and the working range of the second NMOS tube is always in a saturation region during programming, so that the current flowing through the fuse wire is ensured to be larger, the fuse wire can be fully fused, and the fusing effect of the fuse wire is good; the first NMOS tube is used for controlling the second NMOS tube to be started, so that the influence of the input voltage fluctuation provided by the control circuit on the grid electrode of the first NMOS tube is reduced, the influence of the input voltage on the fuse fusing effect is controlled, and the fuse can be fused well when the voltage of the grid electrode of the first NMOS tube is larger than the threshold voltage, so that the efuse unit structure is high in sensitivity. In addition, only one NMOS tube is added, so that the circuit change of the efuse unit structure is small.
In addition, unless otherwise specified or indicated, the description of the terms "first", "second", and the like in the specification is only used for distinguishing various components, elements, steps, and the like in the specification, and is not used for representing a logical relationship, a sequential relationship, and the like between various components, elements, steps.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, the foregoing description is not intended to limit the invention. It will be apparent to those skilled in the art that many changes and modifications can be made, or equivalents employed, to the presently disclosed embodiments without departing from the intended scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (9)
1. The utility model provides an efuse unit structure, its characterized in that only includes first NMOS pipe, second NMOS pipe and fuse, the drain electrode of first NMOS pipe with the drain electrode of second NMOS pipe all connects the power, the source connection of first NMOS pipe the grid of second NMOS pipe, the source connection of second NMOS pipe the one end of fuse, the other end ground connection of fuse.
2. The efuse cell structure of claim 1, wherein the first NMOS transistor and the second NMOS transistor satisfy the following equation:
W2/L2＞W1/L1；
wherein W1 is the channel width of the first NMOS tube; l1 is the channel length of the first NMOS tube; w2 is the channel width of the second NMOS tube; and L2 is the channel length of the second NMOS tube.
3. The efuse cell structure of claim 1, wherein the first NMOS transistor and the second NMOS transistor satisfy the following formula:
W2＞W1；
wherein W1 is the channel width of the first NMOS tube; w2 is the channel width of the second NMOS tube.
4. The efuse cell structure of claim 1, wherein the fuse is in a conducting state when the second NMOS transistor is not turned on.
5. The efuse cell structure of claim 4, wherein the resistance of the fuse in a conducting state is in the vicinity of 100 Ω.
6. The efuse cell structure of claim 1, wherein the fuse is in a blown state after the second NMOS transistor is turned on.
7. The efuse cell structure according to claim 6, wherein the resistance of the fuse in the blown state is above 1E7 Ω.
8. The efuse cell structure of claim 1, wherein the fuse is made of a polysilicon material.
9. A memory comprising the efuse cell structure of claim 1, further comprising a control circuit, wherein the control circuit is connected to the gate of the first NMOS transistor and provides a turn-on voltage to the gate of the first NMOS transistor.
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| CN202210964664.4A CN115035941B (en) | 2022-08-12 | 2022-08-12 | Efuse unit structure and memory |
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| CN202210964664.4A CN115035941B (en) | 2022-08-12 | 2022-08-12 | Efuse unit structure and memory |
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| CN115035941B true CN115035941B (en) | 2022-11-11 |
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Citations (4)
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| JP2000057799A (en) * | 1998-06-04 | 2000-02-25 | Toshiba Corp | Fuse latch circuit and semiconductor integrated circuit |
| CN1381848A (en) * | 2001-03-30 | 2002-11-27 | 富士通株式会社 | Address generating circuit |
| WO2015001731A1 (en) * | 2013-07-02 | 2015-01-08 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| CN108346449A (en) * | 2017-01-22 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of eFuse storage circuits |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5137408B2 (en) * | 2007-02-05 | 2013-02-06 | パナソニック株式会社 | Electrical fuse circuit |
| CN101826507B (en) * | 2009-03-02 | 2012-01-11 | 晨星软件研发(深圳)有限公司 | Electrical fuse and relevant control circuit thereof |
| US7902903B2 (en) * | 2009-07-14 | 2011-03-08 | Raytheon Company | Programmable efuse and sense circuit |
| CN106601301B (en) * | 2015-10-14 | 2020-06-02 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse storage unit and electric fuse storage array |
| JP6994296B2 (en) * | 2016-08-23 | 2022-01-14 | ユナイテッド・セミコンダクター・ジャパン株式会社 | Non-volatile storage device and programming method for non-volatile storage device |
| US10255982B2 (en) * | 2016-11-02 | 2019-04-09 | Skyworks Solutions, Inc. | Accidental fuse programming protection circuits |
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2022
- 2022-08-12 CN CN202210964664.4A patent/CN115035941B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000057799A (en) * | 1998-06-04 | 2000-02-25 | Toshiba Corp | Fuse latch circuit and semiconductor integrated circuit |
| CN1381848A (en) * | 2001-03-30 | 2002-11-27 | 富士通株式会社 | Address generating circuit |
| WO2015001731A1 (en) * | 2013-07-02 | 2015-01-08 | パナソニックＩｐマネジメント株式会社 | Semiconductor device |
| CN108346449A (en) * | 2017-01-22 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of eFuse storage circuits |
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