TWI524350B - Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit - Google Patents

Description

Method and apparatus for programming an anti-fuse element in a high voltage integrated circuit

The present disclosure is generally directed to a circuit for programming an anti-fuse element in a high voltage integrated circuit.

A general-purpose integrated circuit (IC) device is a metal oxide semiconductor field effect transistor (MOSFET) comprising a source region, a drain region, and a channel region. For high voltage applications, a high voltage MOSFET such as the well known high voltage field effect transistor (HVFET) can be used. The complex HVFETs are constructed using a device that includes an extended drain region that maintains or "blocks" the high voltage (eg, 150 volts or higher when the device is in a "off" or substantially non-conducting state). ). Conventional HVFETs are typically constructed in a lateral or vertical configuration. In a lateral HVFET, current flows, when the HVFET is in an "on" state, is horizontal or substantially parallel to a surface of the semiconductor substrate. In a vertical HVFET, current flows vertically through the semiconductor material, for example, from a top surface of one of the substrates at which the source region is disposed, down to the bottom of the substrate where the drain region is disposed .

Conventional high voltage ICs typically use a large vertical or lateral HVFET in a configuration in which the drain of the output transistor is directly coupled to an external pin that can be placed at a high voltage. The high voltage IC device typically includes a controller circuit that operates at a low voltage (0V-12V) that is separate from the HVFET but can still be included in the same high voltage IC. To provide a starting current for the controller circuit of the high voltage IC, a high external voltage can be applied to the external pin. The internal circuitry of the device is typically limitedly protected from the high externally applied voltage by a Junction Field Effect Transistor (JFET) "tap" configuration. For example, when the drain of the high voltage output transistor is used, for example, 550V, the tap transistor limits the maximum voltage coupled to an internal node to about 50V, and also provides a small (2) -3 mA) current is used for starting the controller. A three-terminal JFET transistor actuated in this manner is disclosed in U.S. Patent No. 7,002,398.

The operational characteristics of high voltage ICs are typically set by a well known method of trimming. More specifically, trimming of high voltage ICs is typically performed prior to application in a useful circuit to adjust certain parameters. More specifically, the trimming process can include selectively closing (or turning on) one or more electrical components that instruct the controller to adjust certain operational characteristics of the high voltage IC. In one example, the electrical components for trimming can be Zener diodes. One or more Zener diodes may be closed (non-conductive electrical components) during the trimming process. To change the conductive state of a Zener element, a voltage (>10 V) is typically applied to break the Zener element. After breaking through the Zener element, a current (150-200 mA) is passed between the anode termination and the cathode termination, permanently shortening the Zener component. The accumulated current flowing through the one or more Zener elements can be used to program one or more analog parameters. For example, a Zener diode can be used to trim or program an analog parameter, such as the switching frequency in a high voltage IC used in a switched mode power supply. For example, in the controller portion of the power IC, by shorting one or more Zener diodes, an analog parameter such as a switching frequency can be set within a particular tolerance.

A method for programming a programmable block of a power integrated circuit (IC) includes programming an anti-fuse element of the programmable block for programming. The anti-fuse element includes first and second capacitive plates separated by a dielectric layer. A voltage pulse is then applied to one of the pins of the power IC device. The pin is connected to a drain of a high voltage output field effect transistor (HVFET) through which an external load is driven during one of the normal operating modes of the power IC device. The voltage pulse is coupled to the first capacitor plate of the anti-fuse element, and has a potential high enough to cause a current to flow through the anti-fuse element to destroy at least a portion of the dielectric layer, thereby The first and second capacitive plates are electrically shorted.

A method for programming an anti-fuse memory block of a power integrated circuit (IC) device, the method comprising: applying an externally applied voltage to a first pin of the power IC, the a pin is connected to a drain of a high voltage output field effect transistor (HVFET) and is also connected to a first terminal of a tap transistor device when an external voltage is applied to the first pin When a clamping voltage of the tap transistor device is exceeded, a substantially constant tap voltage is provided at the second terminal, the first voltage being substantially less than the pinch voltage; and an isolating transistor component is turned on to turn on The externally applied high voltage is coupled to a selected anti-fuse element of the anti-fuse memory block, the select anti-fuse comprising first and second capacitive plates separated by a dielectric layer, the first The capacitive plate is coupled to one of the anti-fuse memory blocks; a read/write element coupled to the selected anti-fuse element is coupled to the second of the selected anti-fuse element Board to ground; the second end of the tap transistor device Coupling to the common contact; applying a pulse voltage substantially higher than the first voltage to the first pin, such that a programming voltage is applied to the first capacitor plate of the selected anti-fuse, the programming The voltage is high enough to cause a current to flow through the selected antifuse sufficient to break at least a portion of the dielectric layer to electrically short the first and second capacitive plates.

The present invention discloses a method for programming an anti-fuse memory block of a power integrated circuit (IC) device, the method comprising: initiating coupling with one of the anti-fuse memory blocks to select an anti-fuse element a switching element comprising: first and second capacitor plates separated by a dielectric layer, the first capacitor plate being coupled to an internal node of the power IC device, the switching element Is coupled to the second board of the selected anti-fuse element; generating an programming voltage at the internal node by an external voltage applied to a pin of the power IC, the pin being connected to a high voltage output a gate of a field effect transistor (HVFET), the programming voltage being high enough to cause a current to flow through the selected antifuse element sufficient to destroy at least a portion of the dielectric layer, thereby electrically electrically The second capacitor plate is shorted.

A method for programming a programmable block of a power integrated circuit (IC) device, the method comprising: selecting an anti-fuse element of the programmable block, the anti-fuse element comprising a first and a second capacitor plate separated by a dielectric layer; applying a voltage pulse to one of the pins of the power IC device, the pin being connected to a drain of a high voltage output field effect transistor (HVFET) Driving an external load through the pin during a normal operation mode of the power IC device, the voltage pulse being coupled to the first capacitor plate of the anti-fuse element, having a high potential sufficient to cause a current flow At least a portion of the dielectric layer is destroyed by the anti-fuse element to electrically short the first and second capacitive plates.

Methods and apparatus for programming an anti-fuse element of a power IC are disclosed. Specific details, voltages, construction features, manufacturing steps, and the like, are set forth in the description which follows. However, it will be apparent to those skilled in the art that the specific details are not required to practice the specific embodiments. References throughout the specification to "one embodiment", "an embodiment", "one" or "an" or "an" Particular features, configurations, or characteristics of the examples are included in at least one embodiment. In the entire description, the words "in one embodiment", "in one embodiment", "one instance" or "one" The examples are not necessarily referring to the same specific embodiments or examples. Furthermore, the particular features, configurations, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples.

It is understood that the elements in the drawings are representative and are not drawn to scale. It should also be appreciated that while an IC that uses most of the N-channel transistor devices (high voltage and low voltage) is disclosed, a P-channel transistor can also be constructed for all suitable doped regions by using opposite conductivity types.

For the purposes of this application, a high voltage or power electro-optic system is any semiconductor transistor construction that can support 150 volts or more in a "off" state or condition. In one embodiment, a power-on relationship is a high voltage field effect transistor (HVFET) which is illustrated as an N-channel metal oxide semiconductor field effect transistor (MOSFET) in the source and drain regions. Support high voltage. In other embodiments, a power switch can include a bipolar junction transistor (BJT), an insulated gate field effect transistor (IGFET), or other device configuration that provides transistor functionality.

For the purposes of this disclosure, "ground" or "ground potential" is a reference voltage or potential that defines or measures all other voltages or potentials to which a circuit or IC is compared. A "pin" provides external electrical connection to a point of an IC device or package to allow external components, circuits, signals, power, loads, etc. to be coupled to internal components and circuitry of a high voltage IC.

It is further observed that in the context of this disclosure, a "high" voltage is defined as a voltage that is substantially 150 V or greater, and an "intermediate" voltage is defined as between 150 V and 50 V. And a "low" voltage system is defined as less than 12 V.

As shown, FIG. 1 is a block diagram showing an exemplary high voltage IC 100 including a high voltage (HV) switch 102, which can be a high voltage field effect transistor (HVFET), a high voltage ( HV) bungee terminal 104, a source terminal 106, a tap element 108, a low voltage (LV) controller 112, an isolation block 114, a trim circuit block 116, a power supply terminal 118, and a feedback terminal 120 representative. As shown, the high voltage switch 102 is coupled between the HV drain terminal 104 and the source terminal 106. In one example, the high voltage switch 102 can be used in a power source to control current through the primary winding of an energy transfer component, such as a coupled inductor. In operation, HV drain terminal 104 is typically coupled to receive input from an external circuit (not shown). As further shown, a source terminal 106 is coupled to the other end of the high voltage switch 102. A tap element 108 is coupled to the HV drain terminal 104. In operation, the tap element 108 provides a buffer between the circuit in the high voltage IC 100 and the HV drain terminal 104. In one example, the tap element 108 includes a three terminal (ie, electrode) transistor device configuration, wherein when the applied voltage is less than one of the clamping devices of the transistor device, the first or minute is A voltage at the terminal of the connector is substantially proportional to an applied voltage across the second and third terminals. When the applied voltage across the second and third terminals exceeds the pinch-off voltage, the voltage provided at the tap terminal is substantially constant or cannot change as the applied voltage increases. In one embodiment, the tap element 108 includes a junction field effect transistor (JFET). In operation, tap element 108 provides a buffer between the HV drain terminal 104 and the internal circuitry in the high voltage IC, the series of which is for lower voltages. For example, during normal operation, the HV drain terminal 104 can be exposed to a voltage exceeding 550 V, and the pinch-off voltage (the maximum voltage of the internal circuit exposed to the high voltage IC 100) does not exceed 50 V. As such, the tap element 108 provides a buffer and prevents other internal components in the high voltage IC from reaching a nominal high voltage, which translates into a smaller high voltage IC 100.

As shown, trim circuit block 116 is coupled to HV drain terminal 104 via isolation block 114. In operation, the trim circuit block 116 takes into account a trimming process of the high voltage IC 100. More specifically, trimming can include selectively closing (or turning on) one or more electrical components, instructing the controller to adjust certain operational characteristics of the high voltage IC. In one example, a trim process is performed on the high voltage IC 100 to ensure performance meets specifications. In accordance with the present invention, trimming is the process of writing or programming an antifuse after sensing certain operating characteristics of the high voltage IC 100. As shown, the trim circuit block 116 includes a programmable anti-fuse block 122 and an anti-fuse programming block 124. In one example, the programmable anti-fuse block 122 is comprised of a series of anti-fuse construction elements or an array of anti-fuse elements. To be more specific, in accordance with the present disclosure, an antifuse is a circuit component that provides a normally open electrical connection in a device configuration, such as the same capacitor, having two or more layers of metal, polysilicon or doped. The hetero semiconductor material is separated by a dielectric layer (eg, oxide, nitride, etc.). The electrical connection between the two layers can be permanently closed by applying a large voltage across the two conductors to break or break the dielectric layer, thereby electrically shorting the two metal layers. Programmable anti-fuse block 122 can be programmed via the HV drain terminal 104 during operation.

As shown, the anti-fuse programming block 124 is coupled to the LV controller 112 and the programmable anti-fuse block 122. In one example, the anti-fuse programming block 124 includes a series of selector switches that are electrically coupled in series with an anti-fuse included in the programmable anti-fuse block 122. A selector switch can be any type of transistor or switch that allows current to pass through its corresponding antifuse. During a trimming operation, certain selector switches of the anti-fuse programming block 124 can be activated (one at a time) to allow a medium voltage (about V) to be applied across an anti-fuse. Electrical breakdown and allow current to pass. As such, the selector switches are coupled to their corresponding antifuse, allowing the antifuse to be shorted when activated (on). In other words, when the antifuse breaks down and allows current to pass, the antifuse is programmed or written. During the trimming process, it is easy to say that the writes of the anti-fuse, low voltage (LV) controller 112 can output the address signal U _ADD and enable the selector switch in the anti-fuse programming block 124. Therefore, its corresponding anti-fuse system can be programmed. As shown, a read block 126 is coupled to the programmable anti-fuse block to determine which anti-fuse in the programmable anti-fuse block 122 has been programmed or shorted. As such, the LV controller 112 can adjust the operational characteristics of the high voltage IC 100.

Isolation block 114 is "on" during a programming operation to couple an external applied voltage to anti-fuse block 122. At the same time, one of the selector switches of the anti-fuse programming block 124 coupled to a target anti-fuse to be shorted is turned on.

The external applied voltage to be applied is considered to traverse only one anti-fuse at a time, so that one capacitor is short-circuited at a time. "Close" all other selector switches in the anti-fuse programming block 124. It will be appreciated that during normal operation of the high voltage IC 100, the isolation block trims the circuit block 116 at one of the nodes 129 of the tap element 108 to operate at a medium voltage (50 V).

As shown, FIG. 2 further illustrates an exemplary high voltage IC 200. As shown, the high voltage IC 200 includes a HV switch 202, an HV terminal 204, a source terminal 206, a tap element 208, an LV controller 212, a calculator/decoder 266, an isolation block 214, and a A trim block 216, a supply terminal 218, a feedback terminal 220, a programmable anti-fuse block (222), a switch block 224, and a read block 226. In one example, HV switch 202, tap element 208, LV controller 212, isolation block 214, trim block 216, switch block 224, and read block 226 can be HV switch 102, tap element 108, LV controller, respectively. 112, an example of isolation block 114, trim block 116, anti-fuse programming block 124, and read block 226.

As shown, in this example, HV IC 200, tap element 208 can include a tap transistor configuration that protects the circuit in the high voltage IC from voltages greater than about 80V. For example, when the voltage is drawn at a high voltage (HV) terminal 204, say 550V, the tap transistor defines a maximum voltage at node 236 to about 80V and also provides a small (2-3 mA) current. . Isolation block 214 isolates trim circuit block 216 from the voltage present at a node 236 under normal operating conditions. Node 238 of one of trim circuit blocks 216 is shown coupled to node 236 via isolation block 214. As further shown, node 236 also includes a first or "tap" terminal of tap element 208. A second terminal of the tap element 208 is coupled to the HV drain terminal 204, which may also be coupled to the drain of the high voltage switch 202. A third terminal coupled to the gate of the JFET tap transistor structure is normally grounded to a ground potential.

Those skilled in the art of semiconductor technology will recognize that tap element 208 and high voltage switch 202 can be integrally formed into a single device configuration. Should enter one It is known that node 236 can receive a sufficiently large voltage from an external or internal voltage source in high voltage IC 200 to trim the antifuse in programmable antifuse block 222, or node 236 can be directly The external voltage source receives the voltage. It will also be appreciated that trim 216 and LV controller 212 are typically constructed of the same 矽 material.

As shown, the isolation block 214 includes a PMOS transistor 230 and an NMOS level shift transistor 232, and a quasi-shift resistor 234. As further shown, the node 236 is coupled to the source of the transistor 230 and to the end of the resistor 234 of the isolation block 214. In one example, PMOS transistor 230 can be rated up to 50V. The other end of the resistor 234 is shown as being coupled to the gate of the transistor 230 and also coupled to the drain of the level shifting transistor 232. The source of the transistor 232 is grounded. It will be appreciated by the practitioner that the resistor 230 of the isolation block 214 functions to isolate the trim block 216 from the medium voltage generated by the tap element 208 at node 236 under normal operating conditions.

In operation, the level shifting transistor 232 and the resistor 234 move the control signal U _CON to the gate control signal of the resistor 230. More specifically, a connection signal U _CON is received at the gate of the level shifting transistor 232 to "turn on" the transistor 232, thereby "turning on" the transistor 230, thereby coupling the nodes 236 through 238. In operation, the connection signal _UCON can connect node 236 to node 238 during a trimming operation and disconnect node 236 from node 238 during normal operation. In one application, the current through the level shifting transistor 232 and resistor 234 can be designed such that when the transistor 232 is turned on, the gate-source voltage of the transistor 230 is limited to about 10 volts. In some embodiments, the gate of the level shifting transistor 232 can be clamped.

As shown, the trim circuit block 216 further includes a programmable anti-fuse block 222 and a switch block 224. As shown, the programmable anti-fuse block 222 includes a plurality of AF ₁ , AF ₂ ... AF _n , where n is an integer. Each programmable anti-fuse element AF is coupled between node 238 and a corresponding selector switch (SW) included in switch block 224. Prior to programming (ie, trimming), the antifuse AF does not have any current flowing through; that is, it appears as an open circuit to a normal DC operating voltage (eg, VDD = 5-6 V).

A selected anti-fuse (e.g., AF ₁ ) in block 216 can be programmed by the corresponding selector switch (i.e., SW ₁ ) in turn-on block 224, and then a voltage pulse is applied at node 238. (For example, 30-35 V, 0.5-1.0 mA for 2-5 ms). The voltage required to blow the antifuse is dependent on the gate oxide thickness (eg, ~30 V for 25 nm oxide). Applying the high voltage pulse can cause the anti-fuse gate oxide structure to rupture, resulting in a permanent short between the top plate and the bottom plate of the anti-fuse AF ₁ , typically having a resistance of several thousand ohms. The state of the anti-fuse AF ₁ can be read by the read block 226 by sensing its resistance. As explained throughout this disclosure, the trimming pulses used to trim the anti-fuse programming component can be externally provided via the HV drain terminal 204.

Practitioners in the industry should be aware that the total amount of current required to trim an antifuse configuration AF is significantly smaller than that of an existing Zener diode, typically requiring >150 mA. Moreover, those skilled in the art will appreciate that the programmable anti-fuse block disclosed herein can reduce the overall size of the trim circuit block 216 of the high voltage IC 200 by about 5 or more as compared to prior art designs. Multiple times. In one embodiment, each of the anti-fuse AFs of the programmable anti-fuse block 222 includes a very small gate oxide area, ~10 μm ² .

In operation, a programmed or trimmed HV pulse can be applied to the HV drain terminal 204 of the high voltage IC 200 and transferred to the trim block 216 via the tap element 208 and the isolation block 214. As shown, the trim circuit block 216 also includes a switch block 224 that includes a plurality of selector switches SW ₁ , SW ₂ ... SW _n , each of which is associated with a corresponding AF ₁ , AF ₂ ... AF _n coupled. In one embodiment, the selector switch SW is a MOSFET S that can withstand voltages up to 50 volts. To program a selective anti-fuse AF, the gate of the corresponding selector switch SW is "turned on" by raising the gate to a high potential, while the source is coupled via a low impedance switch Ground. Turn off all other selector switches SW (related to unselected anti-fuse) (eg, using their source grounded via a high impedance grounded gate). More specifically, the address signal U _ADD is delivered to a corresponding selector switch in the switch block 224 that coincides with the anti-fuse AF that has been selected to be shorted or trimmed. As such, LV controller 212 and decoder 266 can output address signal U _ADD to isolate and trim the antifuse selected for the trimming operation.

According to a specific embodiment, an antifuse AF is trimmed each time. The complex anti-fuse AF can be trimmed (short-circuited) and the trimming operation of each anti-fuse AF is continuously performed. During the trimming operation, the transistor 230 in the isolation block 214 is turned on to connect the programmable anti-fuse block to the node 236. A pulse voltage is then applied to the HV drain terminal 204 causing a lower internal voltage to be generated at node 236. It should be noted that the pulse voltage applied to HV terminal 204 can be hundreds of volts (e.g., 600-700 V), but tap element 208 limits the voltage appearing at node 236 to a lower voltage potential (eg, About 50 V).

It will be appreciated by those skilled in the art that high voltage switch 202, which in one embodiment, can be a MOSFET, is designed and constructed to withstand a high pulse voltage up to about 700 volts during normal operation. In another example, the gate of the selector switch can be pulsed while maintaining a fixed high voltage at the drain terminal 204. When a voltage pulse of about 30 V or more is applied across the selected anti-fuse AF, the gate oxide separated by the two terminals or the capacitor plates is broken, thereby programming (short-circuiting) the anti-fuse structure. . In the case of such unselected anti-fuse AF - that is, those who are not expected to be blown or shorted - the gate of the corresponding selector switch SW is grounded to close the selector switch SW. Thus, the voltage appearing at the bottom circuit board (coupled to the drain of the selector switch SW) potentially rises, essentially tracking the voltage of the top board (coupled to node 238). Thus, the gate oxides of the unselected antifuse AF are not broken and the device configurations maintain an open circuit.

In operation, supply pin 218 provides power to internal circuitry in high voltage IC 200. In one example, supply pin 218 can be coupled to a supply capacitor that is charged by HV drain terminal 204 via tap element 208. In operation, the feedback terminal 220 provides information to the LV controller 112 such that it can drive the high voltage switch 102. In one example, the high voltage IC 200 is used in a switched mode power supply, and the high voltage switch 102 adjusts the transfer of energy by limiting a current through a coupled inductor or a primary winding of a transformer.

Figure 3 is an exemplary flow diagram for programming one of the successive steps of an antifuse shown in the particular embodiment of Figure 2. The sequence begins at block 310 by applying a voltage of 5 V to the HV drain terminal 202. This is a safety measure to confirm that current does not flow out of the HV drain terminal 202. In block 320, a calculator/decoder 266 (eg, timing) can be used to select and turn on the appropriate selector switch SW. That is, a voltage is applied to the gate of the selector switch SW in conjunction with the anti-fuse AF selected for programming, the gate voltage being sufficiently high to turn on the selector switch SW. The other selector switches SW associated with the unselected anti-fuse are coupled to ground to ensure that they remain closed.

Next, as shown in block 330, the "on" level moves the transistor 232 causing the transistor 230 (P1) to conduct. In effect, node 238 is thus coupled to node 236 and is at the same voltage potential. HV terminal 204 is then pulsed with a high voltage; that is, node 236 is boosted to ~50 V and then back down to 5 V. In one embodiment, a 2 ms pulse duration can be applied with a rise/fall time of ~100 μs. At decision block 350, if the trim has been completed for all of the antifuse, the process is completed. If further trimming operations are required, the flow chart proceeds back to block 320 where the calculator/decoder is timed to select and conduct the next selection corresponding to the target antifuse for the trimming operation. Switch.

Although the present invention has been described in connection with the specific embodiments thereof, it is to be understood that Accordingly, the specification and drawings are to be regarded as a

AF ₁ ..AF _n . . . Programmable anti-fuse element

SW. . . Selector switch

U _ADD . . . Address signal

U _CON . . . Connection signal

U _SENSE . . . Inductive signal

U _READ . . . Read signal

100. . . High voltage IC

102. . . High voltage switch

104. . . High voltage bungee terminal

106. . . Source terminal

108. . . Tap component

112. . . Low voltage controller

114. . . Isolation block

116. . . Trimming circuit block

118. . . Power supply terminal

120. . . Feedback terminal

122. . . Programmable antifuse block

124. . . Anti-fuse programming block

126. . . Read block

129. . . node

200. . . High voltage IC

202. . . HV switch

204. . . HV terminal

206. . . Source terminal

208. . . Tap component

212. . . LV controller

214. . . Isolation block

216. . . Trimming block

218. . . Supply terminal / supply pin

220. . . Feedback terminal

222‧‧‧Programmable anti-fuse block

224‧‧‧Switch block

226‧‧‧Read block

230‧‧‧ PMOS transistor

232‧‧‧ Ground potential / NMOS level moving transistor

234‧‧‧bit moving resistor

236‧‧‧ nodes

238‧‧‧ nodes

266‧‧‧Calculator/Decoder

310‧‧‧Process block

320‧‧‧Process block

330‧‧‧Process block

340‧‧‧Process block

350‧‧‧Process Block

The present disclosure is to be understood by the following detailed description of the accompanying drawings.

Figure 1 illustrates a block diagram of an exemplary high voltage IC device.

2 is a schematic diagram showing an exemplary circuit of the trimming block of FIG. 1.

3 is an exemplary flow chart for successive steps of trimming a high voltage IC.

100. . . High voltage IC

102. . . High voltage switch

104. . . High voltage bungee terminal

106. . . Source terminal

108. . . Tap component

112. . . Low voltage controller

114. . . Isolation block

116. . . Trimming circuit block

118. . . Power supply terminal

120. . . Feedback terminal

122. . . Programmable antifuse block

124. . . Anti-fuse programming block

126. . . Read block

129. . . node

U _ADD . . . Address signal

U _CON . . . Connection signal

U _SENSE . . . Inductive signal

U _READ . . . Read signal

Claims (14)

A method for programming an anti-fuse memory block of a power integrated circuit (IC) device, the method comprising: applying a first voltage to a first pin of the power IC device, the first lead The foot is connected to a drain of a high voltage output field effect transistor and is also connected to a first terminal of a tap transistor device, when a potential of the first pin exceeds the tap transistor device Providing a substantially constant tap voltage at a second terminal of the tap transistor device at a clamping voltage, the first voltage being substantially less than the pinch voltage; conducting and the anti-fuse memory One of the blocks selects a trimming MOSFET associated with the antifuse, the selected antifuse comprising first and second capacitive plates separated by a dielectric layer, the first capacitive plate and the antifuse memory One of the body blocks is coupled to a common node, and the second capacitor plate is coupled to one of the trimming MOSFETs; a write signal is applied, which causes a source of the trimming MOSFET to be shorted to be grounded via a low impedance Coupling the second terminal of the tap transistor device a common node; applying a second voltage substantially higher than the first voltage to the first pin, such that a programming voltage is applied to the first capacitor plate of the selected anti-fuse, the programming voltage is sufficient High enough to cause a current to flow through the selected antifuse sufficient to break at least a portion of the dielectric layer to electrically short the first and second capacitive plates. The method of claim 1, wherein the second voltage system is greater than the pinch voltage and the programming voltage is substantially equal to the tap voltage. The method of claim 1, wherein the write signal is applied to a gate of a low voltage field effect transistor, the low voltage field effect transistor having a drain coupled to the source of the trim MOSFET The source of one of the low voltage field effect transistors is grounded. The method of claim 1, wherein the trimming MOSFET has a breakdown voltage that exceeds the tap voltage. The method of claim 1, further comprising turning off all other antifuse of the anti-fuse memory block except for the selection of the antifuse. The method of claim 1, further comprising clamping a programming voltage across the selected antifuse. A method for programming an anti-fuse memory block of a power integrated circuit (IC) device, the method comprising: applying a first voltage to a first pin of the power IC device, the first The pin is connected to a drain of a high voltage output field effect transistor (HVFET) and is also connected to a first terminal of a tap transistor device, when a potential of the first pin exceeds the tap a clamping voltage of the transistor device, providing a substantially constant tap voltage at a second terminal of the tap transistor device, the first voltage being substantially less than the pinch voltage; conducting an isolated battery a crystal element coupling the first voltage to the a selective anti-fuse element of the anti-fuse memory block, the selected anti-fuse comprising first and second capacitive plates separated by a dielectric layer, the first capacitive plate and the anti-fuse memory One of the body blocks is coupled to a common node; a read/write element coupled to the selected anti-fuse element is coupled to connect the second capacitive plate of the selected anti-fuse element to ground; the tap The second terminal of the transistor device is coupled to the common node; applying a pulse voltage substantially higher than the first voltage to the first pin, such that a programming voltage is applied to the selected anti-fuse element The first capacitor plate, the programming voltage is high enough to cause a current to flow through the selected anti-fuse element sufficient to break at least a portion of the dielectric layer to electrically short the first and second capacitive plates. The method of claim 7, wherein the pulse voltage is greater than the pinch voltage and the programming voltage is substantially equal to the tap voltage. The method of claim 7, wherein the read/write element comprises a low voltage field effect transistor having a drain coupled to the source of the trim MOSFET and the low voltage field effect One of the sources of the transistor is coupled to ground. The method of claim 7, further comprising turning off read/write elements associated with all other antifuse of the anti-fuse memory block, except for selecting the anti-fuse element. The method of claim 7, further comprising clamping a programming voltage across the selected anti-fuse element. A method for programming an anti-fuse memory block of a power integrated circuit (IC) device, the method comprising: initiating a switch coupled to one of the anti-fuse memory blocks for selecting an anti-fuse element The first anti-fuse element includes first and second capacitive plates separated by a dielectric layer, the first capacitive plate being coupled to an internal node of the power IC device, the switching element being coupled Up to the second capacitor plate of the anti-fuse element; generating an programming voltage at the internal node by an external voltage applied to a pin of the power IC device, the pin being connected to a high voltage output field One of the drain electrodes of the HVFET, the programming voltage is high enough to cause a current to flow through the selected anti-fuse element sufficient to destroy at least a portion of the dielectric layer, thereby electrically electrically The second capacitor plate is short-circuited; and the programming voltage generated therein includes: a tap voltage limiting the external voltage to be substantially constant, the tap voltage being provided to a second terminal of a tap transistor device, the Jointed crystal device a first terminal is coupled to the pin and the drain of the HVFET; and an isolation transistor element is coupled to couple the substantially constant tap voltage to the internal node, and the substantially constant tap voltage This programming voltage is included. The method of claim 12, wherein the programming voltage package Contains a pulse voltage. The method of claim 12, further comprising clamping the programming voltage across the selected anti-fuse element.