CN115034174A

CN115034174A - Method for checking chip bonding pad position and network in package

Info

Publication number: CN115034174A
Application number: CN202210746379.5A
Authority: CN
Inventors: 柯诗法; 王新
Original assignee: Hangzhou Microsilicon Tech Co ltd
Current assignee: Hangzhou Microsilicon Tech Co ltd
Priority date: 2022-06-29
Filing date: 2022-06-29
Publication date: 2022-09-09

Abstract

The invention discloses a method for checking a chip bonding pad position and a network in packaging, which comprises the following steps: A) establishing an actual information file and an initial information file in a text format (txt format); (B) opening the auxiliary software; (C) the auxiliary software loads the actual information file and the initial information file, runs and compares the actual information file and the initial information file; (D) and obtaining the information of all the pads with position errors or network errors. The invention aims to provide an inspection method capable of efficiently and accurately confirming the position of a chip bonding pad in a package and a network.

Description

Method for checking chip bonding pad position and network in package

Technical Field

The invention relates to a chip packaging process, in particular to a method for inspecting a chip bonding pad position and a network in packaging.

Background

Packaging (Package) is a process of assembling a plurality of integrated circuit components (such as chips and discrete devices) into a final product, and in detail, packaging is a process of placing a produced integrated circuit chip (Die) on a substrate which plays a bearing role and arranging pins in a circuit layout manner so as to Package the chip into a whole, and the quality of a packaging process determines the final quality of the integrated circuit product.

The fan-out wafer level package (FOWLP) can recombine and package chips and elements with different sizes together to form a standard-shaped package structure, and can conveniently complete high-density package wiring, so that the fan-out wafer level package (FOWLP) becomes a preferred technology for realizing system-level packaging. The wafer level fan-out package is processed and manufactured in a mode that the fan-out package structure is used as a unit to reconstruct a wafer, and batch production and manufacturing are facilitated due to the unique wafer reconstruction structure.

However, the wafer level fan-out package integrates a large-scale chip, so the scale of the formed bonding pad is also large, but the position and the connection network of the bonding pad are generally determined by the previous process, and because the workload is huge, the difference between the actual position and the connection network of the bonding pad and the design may exist after the previous process is completed, if the actual position and the connection network of the bonding pad are not determined, the wafer level fan-out package is performed only according to the designed position and the connection network of the bonding pad, the package failure may be caused, the construction period is delayed, and the cost of an enterprise is increased; however, if the actual location of the pads and the work of connecting the network is confirmed only manually, it is time consuming and labor consuming and may have omissions and errors.

Disclosure of Invention

The purpose of the invention is as follows: the invention aims to provide an inspection method capable of efficiently and accurately confirming the position of a chip bonding pad in a package and a network.

The technical scheme is as follows: the invention relates to a method for checking a chip bonding pad position and a network in a package, which comprises the following steps:

(A) establishing an actual information file and an initial information file in a text format (txt format), wherein the actual positions of the chip locating points, the actual positions of all the bonding pads, the actual bonding pad network names and the actual bonding pad types are recorded in the actual information file, and the design positions of the chip locating points, the design positions of all the bonding pads, the design bonding pad network names and the design bonding pad types are recorded in the initial information file;

(B) opening the auxiliary software;

(C) the auxiliary software loads the actual information file and the initial information file, runs and compares the actual information file and the initial information file;

(D) and obtaining the information of all the pads with position errors or network errors so that a package designer can check the design of the wrong pads.

Further, the auxiliary software is based on the SKILL language.

Further, the auxiliary software operates as follows:

(1) opening Cadence software, and loading an auxiliary software running script;

(2) loading an actual information file and an initial information file;

(3) and operating to obtain the information of all the pads with position errors or network errors.

Further, for better wafer level fan-out packaging. In the wafer level fan-out type packaging design process, a chip may be rotated or displaced, so that positioning points are arranged on the chip, auxiliary software firstly compares actual positions of the positioning points with design positions recorded in an initial information file, so as to obtain a relative rotation angle and a relative displacement between the actual positions and the design positions (if the actual positions and the design positions are not changed, the relative rotation angle and the relative displacement are both 0), then the relative rotation angle and the relative displacement are given to the pad design positions, correction is carried out, a correction result is obtained, and finally the actual positions of the pads are compared with the correction result.

Further, the actual position and the design position include an x-coordinate and a y-coordinate, respectively.

Has the advantages that: compared with the prior art, the invention has the following remarkable advantages: the SKILL language is a program language which is built in the Cadence software and is based on the C language and the LISP language, the Cadence software provides rich interactive functions for a SKILL tool, and the auxiliary software written in the SKILL language can greatly improve the calculation efficiency, so that whether the position of a chip bonding pad and a network in a package are accurate or not is confirmed, and errors in package design are prevented.

Drawings

FIG. 1 is a schematic flow diagram of the present invention;

FIG. 2 is a schematic diagram illustrating auxiliary software running scripts loaded in Cadence software;

FIG. 3 is a flow chart of the operation of the auxiliary software;

fig. 4 is a schematic diagram of information of a pad at a wrong position obtained in auxiliary software.

Detailed Description

The technical scheme of the invention is further explained by combining the attached drawings.

Referring to fig. 1 to 4, the method for inspecting the chip pad position and the network in the package according to the present invention includes the following steps:

(A) establishing an actual information file and an initial information file in a text format (txt format), wherein the actual position of a chip locating point, the actual x coordinate, the actual y coordinate, the actual pad network name and the actual pad type are recorded in the actual information file, and the design position of the chip locating point, the design x coordinate, the design y coordinate, the design pad network name and the design pad type are recorded in the initial information file;

(B) opening Cadence software, and loading an auxiliary software running script based on SKILL language;

(C) the auxiliary software loads an actual information file and an initial information file, the auxiliary software firstly compares the actual position of the positioning point with the design position recorded in the initial information file, so that a relative rotation angle and a relative displacement between the actual position and the design position are obtained (if the relative rotation angle and the relative displacement are not changed, the relative rotation angle and the relative displacement are both 0), then the relative rotation angle and the relative displacement are given to the design position of the bonding pad, correction is carried out, a correction result is obtained, and finally the actual position of the bonding pad is compared with the correction result;

(D) information is obtained for all pads at the wrong location for the package designer to check on the design of these wrong pads.

Claims

1. A method for checking the position of a chip bonding pad and a network in a package comprises the following steps:

(B) opening the auxiliary software;

(C) the auxiliary software loads an actual information file and an initial information file, runs and compares the actual information file and the initial information file;

(D) and obtaining the information of all the pads with position errors or network errors.

2. The method of claim 1, wherein the method further comprises the steps of: the auxiliary software is based on the SKILL language.

3. The method of claim 1 or 2, wherein the method comprises the steps of: the auxiliary software comprises the following operation steps:

(1) opening Cadence software, and loading an auxiliary software running script;

(2) loading an actual information file and an initial information file;

4. The method of claim 1, wherein the method further comprises the steps of: the auxiliary software firstly compares the actual position of the positioning point with the design position recorded in the initial information file so as to obtain a relative rotation angle and a relative displacement between the actual position and the design position, then gives the relative rotation angle and the relative displacement to the design position of the bonding pad, corrects the design position of the bonding pad so as to obtain a correction result, and finally compares the actual position of the bonding pad with the correction result.

5. The method of claim 1, wherein the method further comprises the steps of: the actual position and the design position respectively comprise an x coordinate and a y coordinate.