CN115032567B - Electrolytic capacitor short circuit detection system - Google Patents
Electrolytic capacitor short circuit detection system Download PDFInfo
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- CN115032567B CN115032567B CN202210972331.6A CN202210972331A CN115032567B CN 115032567 B CN115032567 B CN 115032567B CN 202210972331 A CN202210972331 A CN 202210972331A CN 115032567 B CN115032567 B CN 115032567B
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Abstract
The invention provides an electrolytic capacitor short circuit detection system.A negative input end of a first comparison circuit is also connected with the bottom of an electrolytic capacitor, a positive electrode of the electrolytic capacitor is connected with a first voltage source which outputs a third preset voltage, and the first comparison circuit outputs a high level signal when the positive electrode of the electrolytic capacitor is short-circuited with the bottom; the positive input end of the second comparison circuit is also connected with the negative electrode of the electrolytic capacitor, wherein the third preset voltage is greater than the fourth preset voltage, the fourth preset voltage is greater than the fifth preset voltage, and the second comparison circuit outputs a high-level signal when the positive electrode and the negative electrode of the electrolytic capacitor are short-circuited; and the logic processing circuit outputs a short circuit abnormal signal to the program controller after receiving the high level signal output by the first comparison circuit or the second comparison circuit. The short circuit detection is carried out through the operational amplifier and the logic circuit based on the NAND gate, so that the accuracy and reliability of the short circuit detection can be greatly improved.
Description
Technical Field
The invention relates to the technical field of short circuit detection, in particular to a short circuit detection system of an electrolytic capacitor.
Background
The electrolytic capacitor is widely applied to the fields of industrial control, power supply, new energy, white household appliances and the like, and is gradually developed towards miniaturization, large capacity, low impedance, high temperature and high reliability, and the material matching of a low impedance product is mainly the high conductivity of electrolyte and the low density of electrolytic paper. The low-density electrolytic paper is easy to cause invisible short circuit of the product, the invisible short circuit is sometimes called as false short circuit, and may be caused by foil burrs, falling oxide film particles, dust and the like, and sometimes the aluminum foil is not in the middle of the electrolytic paper when the core package is rolled, so that the aluminum foil touches the bottom of the aluminum shell, and the short circuit is also caused.
In the related art, a fixed voltage is applied to two ends of an electrolytic capacitor, a current value between two leads of the electrolytic capacitor is tested, and then the tested current value is compared according to a set current standard value to determine whether the electrolytic capacitor has a short circuit abnormal condition. However, when short-circuit detection is performed in this manner, it is necessary to search set value data of a product of a specific specification, and accuracy and reliability of short-circuit detection are low.
Disclosure of Invention
In order to solve the technical problems, the invention provides an electrolytic capacitor short circuit detection system, which can greatly improve the accuracy and reliability of short circuit detection by carrying out short circuit detection through an operational amplifier and a logic circuit based on a NAND gate.
The technical scheme adopted by the invention is as follows:
an electrolytic capacitor short circuit detection system comprising: the voltage regulator comprises a first voltage output circuit, a second voltage output circuit, a third voltage output circuit, a fourth voltage output circuit, a first comparison circuit, a second comparison circuit and a logic processing circuit, wherein the first voltage output circuit is connected with a positive input end of the first comparison circuit and is used for outputting a first preset voltage; the second voltage output circuit is connected with the negative input end of the first comparison circuit and is used for outputting a second preset voltage; the negative input end of the first comparison circuit is also connected with the bottom of the electrolytic capacitor, wherein the positive electrode of the electrolytic capacitor is connected with a first voltage source which outputs a third preset voltage, the second preset voltage is greater than the first preset voltage, the first preset voltage is greater than the third preset voltage, and the first comparison circuit is used for outputting a high-level signal when the positive electrode of the electrolytic capacitor is short-circuited with the bottom; the third voltage output circuit is connected with the negative input end of the second comparison circuit and is used for outputting a fourth preset voltage; the fourth voltage output circuit is connected with the positive input end of the second comparison circuit, and is used for outputting a fifth preset voltage; the positive input end of the second comparison circuit is further connected with the negative electrode of the electrolytic capacitor, wherein the third preset voltage is higher than the fourth preset voltage, the fourth preset voltage is higher than the fifth preset voltage, and the second comparison circuit is used for outputting a high-level signal when the positive electrode and the negative electrode of the electrolytic capacitor are short-circuited; the input end of the logic processing circuit is respectively connected with the output end of the first comparison circuit and the output end of the second comparison circuit, the output end of the logic processing circuit is connected with a program controller, and the logic processing circuit is used for outputting a short circuit abnormal signal to the program controller after receiving a high level signal output by the first comparison circuit or the second comparison circuit.
The first comparison circuit includes: a positive input pin of the first operational amplifier is connected with the first voltage output circuit, and a negative input pin of the operational amplifier is respectively connected with the second voltage output circuit and the bottom of the electrolytic capacitor; and the anode of the first diode is connected with the output end of the first operational amplifier, and the cathode of the first diode is connected with the input end of the logic processing circuit.
The second comparison circuit includes: a positive input pin of the second operational amplifier is connected with the fourth voltage output circuit and the negative electrode of the electrolytic capacitor respectively, and a negative input pin of the second operational amplifier is connected with the third voltage output circuit respectively; and the anode of the second diode is connected with the output end of the second operational amplifier, and the cathode of the second diode is connected with the input end of the logic processing circuit.
The first voltage output circuit includes: one end of the first resistor is connected with a second voltage source, and the other end of the first resistor is connected with a positive input pin of the first operational amplifier; and one end of the second resistor is connected with the third voltage source, and the other end of the second resistor is connected with the other end of the first resistor.
The third voltage output circuit includes: one end of the third resistor is connected with a fourth voltage source, and the other end of the third resistor is connected with a negative input pin of the second operational amplifier; and one end of the fourth resistor is connected with the fifth voltage source, and the other end of the fourth resistor is connected with the other end of the third resistor.
The first operational amplifier and the second operational amplifier are both LM358.
The first diode and the second diode are both IN4007 IN type.
The logic processing circuit comprises: a base electrode of the first triode is respectively connected with a negative electrode of the first diode and a negative electrode of the second diode, an emitting electrode of the first triode is grounded, and a collector electrode of the first triode is connected with a sixth voltage source through a fifth resistor; one end of the sixth resistor is connected with the base electrode of the first triode, and the other end of the sixth resistor is connected with the emitting electrode of the first triode; a first input end and a second input end of the first NAND gate are both connected with a collector electrode of the first triode; a first input end of the second NAND gate is connected with an output end of the first NAND gate, and a second input end of the second NAND gate is connected with a seventh voltage source through a seventh resistor; a first input end and a second input end of the third NAND gate are both connected with an output end of the second NAND gate; one end of the eighth resistor is connected with the output end of the third NAND gate; the anode of the third diode is connected with the other end of the eighth resistor; a first input end of the first photoelectric coupler is connected with the negative electrode of the third diode, a second input end of the first photoelectric coupler is grounded, and a first output end of the first photoelectric coupler is grounded; and one end of the ninth resistor is connected with the second output end of the first photoelectric coupler, and the other end of the ninth resistor is connected with the signal input end of the program controller.
The invention has the beneficial effects that:
the invention carries out short circuit detection through the operational amplifier and the logic circuit based on the NAND gate, and can greatly improve the accuracy and reliability of short circuit detection.
Drawings
Fig. 1 is a schematic structural diagram of an electrolytic capacitor short-circuit detection system according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic structural view of an electrolytic capacitor short-circuit detection system according to an embodiment of the present invention.
As shown in fig. 1, an electrolytic capacitor short circuit detection system according to an embodiment of the present invention may include: the circuit comprises a first voltage output circuit 100, a second voltage output circuit 200, a third voltage output circuit 300, a fourth voltage output circuit 400, a first comparison circuit 500, a second comparison circuit 600 and a logic processing circuit 700. The first voltage output circuit 100 is connected to a positive input end of the first comparator 500, and the first voltage output circuit 100 is configured to output a first preset voltage V1; the second voltage output circuit 200 is connected to the negative input terminal of the first comparison circuit 500, and the second voltage output circuit 200 is configured to output a second preset voltage V2; the negative input end of the first comparison circuit 500 is further connected to the bottom a of the electrolytic capacitor, wherein the positive electrode b of the electrolytic capacitor is connected to a first voltage source that outputs a third preset voltage V3, the second preset voltage V2 is greater than the first preset voltage V1, the first preset voltage V1 is greater than the third preset voltage V3, and the first comparison circuit 500 is configured to output a high level signal when the positive electrode b of the electrolytic capacitor is short-circuited with the bottom a; the third voltage output circuit 300 is connected to the negative input terminal of the second comparator circuit 600, and the third voltage output circuit 300 is configured to output a fourth preset voltage V4; the fourth voltage output circuit 400 is connected to the positive input end of the second comparator circuit 600, and the fourth voltage output circuit 400 is configured to output a fifth preset voltage V5; the positive input end of the second comparator circuit 600 is further connected to the negative electrode c of the electrolytic capacitor, wherein the third preset voltage V3 is greater than the fourth preset voltage V4, the fourth preset voltage V4 is greater than the fifth preset voltage V5, and the second comparator circuit 600 is configured to output a high level signal when the positive electrode b and the negative electrode c of the electrolytic capacitor are short-circuited; the input end of the logic processing circuit 700 is connected to the output end of the first comparing circuit 500 and the output end of the second comparing circuit 500, the output end of the logic processing circuit 700 is connected to the program controller, and the logic processing circuit 700 is configured to output a short-circuit abnormal signal to the program controller after receiving a high-level signal output by the first comparing circuit 500 or the second comparing circuit 600.
According to an embodiment of the present invention, as shown in fig. 1, the first comparison circuit 500 may include: a first operational amplifier U1A and a first diode D1.
A positive input pin of the first operational amplifier U1A is connected to the first voltage output circuit 100, and a negative input pin of the operational amplifier U1A is connected to the second voltage output circuit 200 and the bottom a of the electrolytic capacitor, respectively; the anode of the first diode D1 is connected to the output terminal of the first operational amplifier U1A, and the cathode of the first diode D1 is connected to the input terminal of the logic processing circuit 700. The positive input pin of the first operational amplifier U1A may be the positive input terminal of the first comparison circuit 500, the negative input pin of the first operational amplifier U1A may be the negative input terminal of the first comparison circuit 500, and the negative electrode of the first diode D1 may be the output terminal of the first comparison circuit 500.
The negative input pin of the first operational amplifier U1A may be connected to the bottom a of the electrolytic capacitor through a tenth resistor R10, the positive power pin of the first operational amplifier U1A is connected to a ninth voltage source (outputting a preset voltage V9, for example, 24V) and one end of a first capacitor C1, respectively, the other end of the first capacitor C1 is grounded, the negative power pin of the first operational amplifier U1A is grounded, and the negative electrode of the first diode D1 may be connected to the input end of the logic processing circuit 700 through an eleventh resistor R11.
In one embodiment of the present invention, as shown in fig. 1, the first voltage output circuit 100 may include: a first resistor R1 and a second resistor R2. One end of the first resistor R1 is connected with a second voltage source, and the other end of the first resistor R1 is connected with a positive input pin of the first operational amplifier U1A; one end of the second resistor R2 is connected with a third voltage source, and the other end of the second resistor R2 is connected with the other end of the first resistor R1.
The preset voltage V11 output by the second voltage source and the preset voltage V12 output by the third voltage source may enable the first voltage output circuit 100 to output the first preset voltage V1 under the voltage division effect of the first resistor R1 and the second resistor R2. For example, the resistances of the first resistor R1 and the second resistor R2 are the same, and are both 1K Ω, then V1= (V11 + V12)/2.
Specifically, when the bottom a of the electrolytic capacitor and the positive electrode b of the electrolytic capacitor are not short-circuited, the negative input pin of the first operational amplifier U1A inputs the second preset voltage V2, the positive input pin of the first operational amplifier U1A inputs the first preset voltage V1, and the second preset voltage V2 is greater than the first preset voltage V1, so that the output end of the first operational amplifier U1A outputs a low level signal, that is, the output end of the first comparison circuit 500 outputs a low level signal. When the bottom a of the electrolytic capacitor and the positive electrode b of the electrolytic capacitor are short-circuited, the voltage input by the negative input pin of the first operational amplifier U1A is reduced to the third preset voltage V3, and since the first preset voltage V1 is greater than the third preset voltage V3, the output terminal of the first operational amplifier U1A outputs a high level signal, that is, the output terminal of the first comparison circuit 500 outputs a high level signal.
According to an embodiment of the present invention, as shown in fig. 1, the second comparison circuit includes: a second operational amplifier U1B and a second diode D2.
A positive input pin of the second operational amplifier U1B is connected to the fourth voltage output circuit 400 and the negative electrode c of the electrolytic capacitor, respectively, and a negative input pin of the second operational amplifier is connected to the third voltage output circuit 300; the anode of the second diode D2 is connected to the output terminal of the second operational amplifier U1B, and the cathode of the second diode D2 is connected to the input terminal of the logic processing circuit 700. The positive input pin of the second operational amplifier U1B may be the positive input terminal of the second comparator 600, the negative input pin of the second operational amplifier U1B may be the negative input terminal of the second comparator 600, and the negative electrode of the second diode D2 may be the output terminal of the second comparator 600.
The positive input pin of the second operational amplifier U1B may be connected to the negative electrode C of the electrolytic capacitor through the twelfth resistor R12, the positive power pin of the second operational amplifier U1B is connected to the tenth voltage source (outputting the preset voltage V10, for example, 24V) and one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, and the negative power pin of the second operational amplifier U1B is grounded.
In one embodiment of the present invention, as shown in fig. 1, the third voltage output circuit 300 includes: a third resistor R3 and a fourth resistor R4. One end of the third resistor R3 is connected with a fourth voltage source, and the other end of the third resistor R3 is connected with a negative input pin of the second operational amplifier U1B; one end of the fourth resistor R4 is connected with a fifth voltage source, and the other end of the fourth resistor R4 is connected with the other end of the third resistor R3.
The preset voltage V41 output by the fourth voltage source and the preset voltage V42 output by the fifth voltage source can enable the third voltage output circuit 300 to output the fourth preset voltage V4 under the voltage division effect of the third resistor R3 and the fourth resistor R4. For example, the third resistor R3 and the fourth resistor R4 have the same resistance value, and are both 1K Ω, and V4= (V41 + V42)/2.
Specifically, when the negative electrode c of the electrolytic capacitor and the positive electrode B of the electrolytic capacitor are not short-circuited, the negative input pin of the second operational amplifier U1B inputs the fourth preset voltage V4, the positive input pin of the second operational amplifier U1B inputs the fifth preset voltage V5, and the fourth preset voltage V4 is greater than the fifth preset voltage V5, so the output end of the second operational amplifier U1B outputs a low level signal, that is, the output end of the second comparison circuit 600 outputs a low level signal. When the negative electrode c of the electrolytic capacitor is short-circuited with the positive electrode B of the electrolytic capacitor, the voltage input by the positive input pin of the second operational amplifier U1B is increased to the third preset voltage V3, and since the third preset voltage V3 is greater than the fourth preset voltage V4, the output end of the second operational amplifier U1B outputs a high level signal, that is, the output end of the second comparison circuit 600 outputs a high level signal.
It should be noted that, IN an embodiment of the present invention, the first operational amplifier U1A and the second operational amplifier U1B are both of the LM358 type, and both the first diode D1 and the second diode D2 are of the IN4007 type.
A third capacitor C3 and a fourth capacitor C4 which are connected in series can be arranged between the bottom a and the negative pole C of the electrolytic capacitor, and the connection point of the third capacitor C3 and the fourth capacitor C4 is grounded.
According to one embodiment of the invention, as shown in FIG. 1, the logic processing circuit 700 may comprise: the driving circuit comprises a first triode Q1, a sixth resistor R6, a first NAND gate U4A, a second NAND gate U4B, a third NAND gate U4C, an eighth resistor R8, a third diode D3, a first photoelectric coupler U1 and a ninth resistor R9.
The base electrode of the first triode Q1 is respectively connected with the cathode of the first diode D1 and the cathode of the second diode D2 (which can be respectively connected with the cathode of the first diode D1 and the cathode of the second diode D2 through an eleventh resistor R11), the emitter electrode of the first triode Q1 is grounded, and the collector electrode of the first triode Q1 is connected with a sixth voltage source (outputting a preset voltage V6, such as 5V) through a fifth resistor R5; one end of a sixth resistor R6 is connected with the base electrode of the first triode Q1, and the other end of the sixth resistor R6 is connected with the emitting electrode of the first triode Q1; a first input end and a second input end of the first NAND gate U4A are both connected with a collector electrode of the first triode Q1; a first input end of the second nand gate U4B is connected to the output end of the first nand gate U4A, and a second input end of the second nand gate U4B is connected to a seventh voltage source (outputting a preset voltage V7, for example, 4.5V) through a seventh resistor R7; the first input end and the second input end of the third NAND gate U4C are both connected with the output end of the second NAND gate U4B; one end of the eighth resistor R8 is connected with the output end of the third NAND gate U4B; the anode of the third diode D3 is connected to the other end of the eighth resistor R8; a first input end of the first photoelectric coupler U1 is connected with a negative electrode of the third diode D3, a second input end of the first photoelectric coupler U1 is grounded, and a first output end of the first photoelectric coupler U1 is grounded; one end of the ninth resistor R9 is connected with the second output end of the first photoelectric coupler, and the other end of the ninth resistor R9 is connected with the signal input end f of the program controller.
Specifically, when the output end of the first comparison circuit 500 outputs a low level signal and the output end of the second comparison circuit 600 outputs a low level signal, that is, the bottom a of the electrolytic capacitor is not short-circuited with the anode B of the electrolytic capacitor, and the cathode C of the electrolytic capacitor is not short-circuited with the anode B of the electrolytic capacitor, the first triode Q1 is turned off, and both input ends of the first nand gate U4A input a high level signal, so the output end of the first nand gate U4A outputs a low level signal, the output end of the second nand gate U4B outputs a high level signal, the output end of the third nand gate U4C outputs a low level signal, and the first photocoupler U1 does not work, so the signal input end f of the program controller cannot receive a signal; when the output end of the first comparing circuit 500 outputs a high level signal, or the output end of the second comparing circuit 600 outputs a high level signal, that is, the bottom a of the electrolytic capacitor and the anode B of the electrolytic capacitor are short-circuited, or the cathode C of the electrolytic capacitor and the anode B of the electrolytic capacitor are short-circuited, the first triode Q1 is turned on, at this time, both input ends of the first nand gate U4A input a low level signal, therefore, the first nand gate U4A outputs a high level signal, the output end of the second nand gate U4B outputs a low level signal, the output end of the third nand gate U4C outputs a high level signal, the first photocoupler U1 operates, and at this time, the signal input end f of the program controller can receive a corresponding signal, that is, a short circuit abnormal signal.
In one embodiment of the present invention, as shown in fig. 1, the electrolytic capacitor short detection system may further include a second photo coupler U2. The feedback end d of the program controller is connected to the first input end of the second photoelectric coupler U2 through the thirteenth resistor R13, the second input end of the second photoelectric coupler U2 is connected to the eighth voltage source (outputting a preset voltage V8, for example, 24V), the first output end of the second photoelectric coupler U2 is connected to the second input end of the second nand gate U4B, and the second output end of the second photoelectric coupler U2 is grounded.
Specifically, after the signal input end f of the program controller receives the short-circuit abnormal signal, the program controller can control the actuating mechanism to act to remove the short-circuit capacitor, meanwhile, the corresponding pulse signal can be fed back to the second photoelectric coupler U2 through the feedback end d, so that the second photoelectric coupler U2 works, and the second input end of the second NAND gate U4B inputs a low-level signal, so that the first photoelectric coupler U1 stops working and recovers to a normal state. After the actions are finished, the program controller feeds back a detection completion signal to the second photoelectric coupler U2 through the feedback end d, so that the second photoelectric coupler U2 stops working, and the second input end of the second NAND gate U4B inputs a high-level signal.
In summary, the electrolytic capacitor short circuit detection system according to the embodiment of the present invention includes: the voltage regulator comprises a first voltage output circuit, a second voltage output circuit, a third voltage output circuit, a fourth voltage output circuit, a first comparison circuit, a second comparison circuit and a logic processing circuit, wherein the first voltage output circuit is connected with the positive input end of the first comparison circuit and is used for outputting a first preset voltage; the second voltage output circuit is connected with the negative input end of the first comparison circuit and is used for outputting a second preset voltage; the negative input end of the first comparison circuit is also connected with the bottom of the electrolytic capacitor, wherein the positive electrode of the electrolytic capacitor is connected with a first voltage source which outputs a third preset voltage, the second preset voltage is greater than the first preset voltage, the first preset voltage is greater than the third preset voltage, and the first comparison circuit is used for outputting a high-level signal when the positive electrode of the electrolytic capacitor is short-circuited with the bottom; the third voltage output circuit is connected with the negative input end of the second comparison circuit and is used for outputting a fourth preset voltage; the fourth voltage output circuit is connected with the positive input end of the second comparison circuit and is used for outputting a fifth preset voltage; the positive input end of the second comparison circuit is also connected with the negative electrode of the electrolytic capacitor, wherein the third preset voltage is greater than the fourth preset voltage, the fourth preset voltage is greater than the fifth preset voltage, and the second comparison circuit is used for outputting a high-level signal when the positive electrode and the negative electrode of the electrolytic capacitor are short-circuited; the input end of the logic processing circuit is respectively connected with the output end of the first comparison circuit and the output end of the second comparison circuit, the output end of the logic processing circuit is connected with the program controller, and the logic processing circuit is used for outputting a short-circuit abnormal signal to the program controller after receiving a high-level signal output by the first comparison circuit or the second comparison circuit. Therefore, the short circuit detection is carried out through the operational amplifier and the logic circuit based on the NAND gate, and the accuracy and the reliability of the short circuit detection can be greatly improved.
In the description of the present invention, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or to imply that the number of technical features indicated is significant. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The meaning of "plurality" is two or more unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "above," and "over" a second feature may be directly on or obliquely above the second feature, or simply mean that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following technologies, which are well known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer-readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (8)
1. An electrolytic capacitor short circuit detection system, comprising: a first voltage output circuit, a second voltage output circuit, a third voltage output circuit, a fourth voltage output circuit, a first comparison circuit, a second comparison circuit and a logic processing circuit,
the first voltage output circuit is connected with the positive input end of the first comparison circuit and is used for outputting a first preset voltage;
the second voltage output circuit is connected with the negative input end of the first comparison circuit and is used for outputting a second preset voltage;
the negative input end of the first comparison circuit is also connected with the bottom of the electrolytic capacitor, wherein the positive electrode of the electrolytic capacitor is connected with a first voltage source which outputs a third preset voltage, the second preset voltage is greater than the first preset voltage, the first preset voltage is greater than the third preset voltage, and the first comparison circuit is used for outputting a high-level signal when the positive electrode of the electrolytic capacitor is short-circuited with the bottom;
the third voltage output circuit is connected with the negative input end of the second comparison circuit and is used for outputting a fourth preset voltage;
the fourth voltage output circuit is connected with the positive input end of the second comparison circuit, and is used for outputting a fifth preset voltage;
the positive input end of the second comparison circuit is further connected with the negative electrode of the electrolytic capacitor, wherein the third preset voltage is greater than the fourth preset voltage, the fourth preset voltage is greater than the fifth preset voltage, and the second comparison circuit is used for outputting a high-level signal when the positive electrode and the negative electrode of the electrolytic capacitor are short-circuited;
the input end of the logic processing circuit is respectively connected with the output end of the first comparison circuit and the output end of the second comparison circuit, the output end of the logic processing circuit is connected with a program controller, and the logic processing circuit is used for outputting a short circuit abnormal signal to the program controller after receiving a high level signal output by the first comparison circuit or the second comparison circuit.
2. The electrolytic capacitor short circuit detection system according to claim 1, wherein the first comparison circuit comprises:
a positive input pin of the first operational amplifier is connected with the first voltage output circuit, and a negative input pin of the operational amplifier is respectively connected with the second voltage output circuit and the bottom of the electrolytic capacitor;
and the anode of the first diode is connected with the output end of the first operational amplifier, and the cathode of the first diode is connected with the input end of the logic processing circuit.
3. The electrolytic capacitor short circuit detection system according to claim 2, wherein the second comparison circuit includes:
a positive input pin of the second operational amplifier is connected with the fourth voltage output circuit and the negative electrode of the electrolytic capacitor respectively, and a negative input pin of the second operational amplifier is connected with the third voltage output circuit;
and the anode of the second diode is connected with the output end of the second operational amplifier, and the cathode of the second diode is connected with the input end of the logic processing circuit.
4. The electrolytic capacitor short circuit detection system according to claim 3, wherein the first voltage output circuit includes:
one end of the first resistor is connected with a second voltage source, and the other end of the first resistor is connected with a positive input pin of the first operational amplifier;
and one end of the second resistor is connected with a third voltage source, and the other end of the second resistor is connected with the other end of the first resistor.
5. The electrolytic capacitor short-circuit detection system according to claim 3, wherein the third voltage output circuit includes:
one end of the third resistor is connected with a fourth voltage source, and the other end of the third resistor is connected with a negative input pin of the second operational amplifier;
and one end of the fourth resistor is connected with a fifth voltage source, and the other end of the fourth resistor is connected with the other end of the third resistor.
6. The electrolytic capacitor short circuit detection system according to claim 3, wherein the first operational amplifier and the second operational amplifier are each model LM358.
7. The electrolytic capacitor short-circuit detection system according to claim 3, wherein the first diode and the second diode are each IN4007 IN type.
8. The electrolytic capacitor short circuit detection system according to claim 3, wherein the logic processing circuit comprises:
a base electrode of the first triode is respectively connected with a negative electrode of the first diode and a negative electrode of the second diode, an emitting electrode of the first triode is grounded, and a collector electrode of the first triode is connected with a sixth voltage source through a fifth resistor;
one end of the sixth resistor is connected with the base electrode of the first triode, and the other end of the sixth resistor is connected with the emitting electrode of the first triode;
the first input end and the second input end of the first NAND gate are connected with the collector electrode of the first triode;
a first input end of the second NAND gate is connected with an output end of the first NAND gate, and a second input end of the second NAND gate is connected with a seventh voltage source through a seventh resistor;
the first input end and the second input end of the third NAND gate are connected with the output end of the second NAND gate;
one end of the eighth resistor is connected with the output end of the third NAND gate;
the anode of the third diode is connected with the other end of the eighth resistor;
a first input end of the first photoelectric coupler is connected with the negative electrode of the third diode, a second input end of the first photoelectric coupler is grounded, and a first output end of the first photoelectric coupler is grounded;
and one end of the ninth resistor is connected with the second output end of the first photoelectric coupler, and the other end of the ninth resistor is connected with the signal input end of the program controller.
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