CN115021756A - Analog-to-digital conversion circuit, chip, analog-to-digital conversion method and electronic device - Google Patents
Analog-to-digital conversion circuit, chip, analog-to-digital conversion method and electronic device Download PDFInfo
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- CN115021756A CN115021756A CN202210752692.XA CN202210752692A CN115021756A CN 115021756 A CN115021756 A CN 115021756A CN 202210752692 A CN202210752692 A CN 202210752692A CN 115021756 A CN115021756 A CN 115021756A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
The embodiment of the application provides an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method and electronic equipment, wherein the analog-to-digital conversion circuit comprises: a fully parallel analog-to-digital conversion module comprising: a K-bit resistor string; the N-bit successive approximation analog-to-digital conversion module comprises: the digital-to-analog conversion array comprises an M-bit capacitor digital-to-analog conversion array, a first comparator and a second comparator, wherein the M-bit capacitor digital-to-analog conversion array is used for carrying out N-bit analog-to-digital conversion on an analog input signal and obtaining an N-bit digital signal, the N-bit digital signal comprises a high K-bit digital signal and a low M-bit digital signal, N is K + M, and K, M and N are positive integers; wherein: the full-parallel analog-to-digital conversion module is configured to sample and convert the analog input signal to obtain a high-K-bit digital signal; the N-bit successive approximation analog-to-digital conversion module is configured to obtain a low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and the low M-bit digital signal is obtained in N-bit analog-to-digital conversion according to the high K-bit digital signal. According to the embodiment of the application, the area or the power consumption of the analog-to-digital conversion circuit can be reduced.
Description
Technical Field
The present disclosure relates to the field of signal processing technologies, and in particular, to an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method, and an electronic device.
Background
A combined analog-to-digital converter of a full parallel (Flash) analog-to-digital converter (ADC) and a Successive Approximation Register (SAR) ADC is a hybrid analog-to-digital converter, also known as Flash-SARADC.
The Flash-SAR ADC in the related technology has the technical problems of large circuit area and high power consumption.
Disclosure of Invention
In view of this, embodiments of the present application provide an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method, and an electronic device, so as to reduce a circuit area of the analog-to-digital conversion circuit and reduce power consumption.
According to an aspect of the present application, there is provided an analog-to-digital conversion circuit including:
a fully parallel analog-to-digital conversion module comprising: a K-bit resistor string;
the N-bit successive approximation analog-to-digital conversion module comprises: the digital-to-analog conversion array comprises an M-bit capacitor digital-to-analog conversion array, a first comparator and a second comparator, wherein the M-bit capacitor digital-to-analog conversion array is used for carrying out N-bit analog-to-digital conversion on an analog input signal and obtaining an N-bit digital signal, the N-bit digital signal comprises a high K-bit digital signal and a low M-bit digital signal, N is K + M, and K, M and N are positive integers;
wherein:
the full-parallel analog-to-digital conversion module is configured to sample and convert the analog input signal to obtain a high-K-bit digital signal;
the N-bit successive approximation analog-to-digital conversion module is configured to obtain a low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and the low M-bit digital signal is obtained in N-bit analog-to-digital conversion according to the high K-bit digital signal.
According to another aspect of the present application, there is provided an analog-to-digital conversion method of an analog-to-digital conversion circuit, the analog-to-digital conversion circuit including: a fully parallel analog-to-digital conversion module comprising: a K-bit resistor string; the N-bit successive approximation analog-to-digital conversion module comprises: the digital-to-analog conversion array comprises an M-bit capacitor digital-to-analog conversion array and an N-bit successive approximation analog-to-digital conversion module, wherein the N-bit successive approximation analog-to-digital conversion module is used for carrying out N-bit analog-to-digital conversion on an analog input signal and obtaining N-bit digital signals, and the N-bit digital signals comprise high-K-bit digital signals and low-M-bit digital signals; wherein N ═ K + M, and K, M and N are positive integers;
the analog-to-digital conversion method comprises the following steps:
the full parallel analog-to-digital conversion module samples and converts an analog input signal to obtain a high-K-bit digital signal;
the N-bit successive approximation analog-digital conversion module obtains a low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-analog conversion array, and the low M-bit digital signal is obtained in N-bit analog-digital conversion according to the high K-bit digital signal.
According to another aspect of the present application, a chip is provided, which includes the analog-to-digital conversion circuit of the embodiment of the present application.
According to yet another aspect of the present application, there is provided an electronic device including: the analog-to-digital conversion circuit of the embodiment of the application.
According to one or more technical schemes provided in the embodiment of the application, the number of capacitors of a capacitor digital-to-analog conversion array in a successive approximation analog-to-digital conversion module is reduced by multiplexing K-bit resistor strings in a full-parallel analog-to-digital conversion module, so that the circuit area can be reduced, and the power consumption can be reduced.
Drawings
Further details, features and advantages of the present application are disclosed in the following description of exemplary embodiments, which is to be read in connection with the accompanying drawings, in which:
FIG. 1 shows a schematic block diagram of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
FIG. 2 shows another schematic block diagram of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
FIG. 3 shows yet another schematic block diagram of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
FIG. 4 shows yet another schematic block diagram of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
FIG. 5 shows yet another schematic block diagram of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
FIG. 6 shows yet another schematic block diagram of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
FIG. 7 shows a schematic diagram of an example of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
fig. 8 shows a schematic structural diagram of another example of an analog-to-digital conversion circuit of an exemplary embodiment of the present application;
fig. 9 shows a flowchart of an analog-to-digital conversion method according to an exemplary embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present application. It should be understood that the drawings and embodiments of the present application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or in parallel. Moreover, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "include" and variations thereof as used herein are open-ended, i.e., "including but not limited to". The term "based on" is "based, at least in part, on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions for other terms will be given in the following description. It should be noted that the terms "first", "second", and the like in the present application are only used for distinguishing different devices, modules or units, and are not used for limiting the order or interdependence relationship of the functions performed by the devices, modules or units.
It is noted that references to "a", "an", and "the" modifications in this application are intended to be illustrative rather than limiting, and that those skilled in the art will recognize that reference to "one or more" unless the context clearly dictates otherwise.
The embodiment of the application provides an analog-digital conversion circuit.
Fig. 1 shows a schematic block diagram of an analog-to-digital conversion circuit of an exemplary embodiment of the present application, and as shown in fig. 1, the analog-to-digital conversion circuit 100 includes: a full parallel analog-to-digital conversion module 110 and an N-bit successive approximation analog-to-digital conversion module 120. The fully parallel analog-to-digital conversion module 110 includes a K-bit resistor string 111. The N-bit successive approximation analog-to-digital conversion module 120 includes an M-bit capacitance digital-to-analog conversion array 121. The N-bit successive approximation analog-to-digital conversion module 120 is configured to perform N-bit analog-to-digital conversion on the analog input signal and obtain an N-bit digital signal, where the N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal. N-K + M, and K, M and N are positive integers.
And the fully parallel analog-to-digital conversion module 110 is configured to sample and convert the analog input signal to obtain a high-K-bit digital signal in the N-bit digital signal. The N-bit successive approximation analog-to-digital conversion module 120 is configured to obtain a low M-bit digital signal of the N-bit digital signals through the K-bit resistor string 111 and the M-bit capacitor digital-to-analog conversion array 121, where the low M-bit digital signal is obtained in N-bit analog-to-digital conversion according to the high K-bit digital signal.
With the analog-to-digital conversion circuit 100 of this embodiment, a resistor-capacitor hybrid structure is formed by the K-bit resistor string 111 of the fully parallel analog-to-digital conversion module 110 and the M-bit capacitor digital-to-analog conversion array 121 of the N-bit successive approximation analog-to-digital conversion module 120, so as to implement N-bit digital-to-analog conversion. By multiplexing the K-bit resistor strings in the fully-parallel analog-to-digital conversion module, the number of capacitors of a capacitor digital-to-analog conversion array in the successive approximation analog-to-digital conversion module is reduced, the circuit area is reduced, and the power consumption is reduced.
It should be understood that although fig. 1 shows components included in the analog-to-digital conversion circuit 100 and a positional relationship between the components, the present embodiment does not limit this.
In this embodiment, the M-bit capacitance digital-to-analog conversion array 121 may be a binary weighted capacitor array or a segmented capacitor array (also referred to as a bridge capacitor array), which is not limited in this embodiment. One example of a segmented capacitor array is a binary weighted capacitor array separated by two independent binary capacitors (called Cs) to at least reduce the overall capacitance value.
In this embodiment, the K-bit resistor string 111 may be first used by the fully parallel analog-to-digital conversion module 110 to generate a high K-bit digital signal of the N-bit digital signals, and then used by the N-bit successive approximation analog-to-digital conversion module 120 to generate a low M-bit digital signal of the N-bit digital signals. A possible implementation of the multiplexed K-bit resistor string 111 is described below.
In a first mode
An N-bit successive approximation analog-to-digital conversion module 120 configured to: the high K-bit digital signal is subjected to digital-to-analog conversion through the K-bit resistor string 111, and a low M-bit digital signal among the N-bit digital signals is obtained through the M-bit capacitor digital-to-analog conversion array 121.
Fig. 2 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the application, and as shown in fig. 2, the analog-to-digital conversion circuit 100 further includes: a switch module 130 configured to encode temperature (including 2) according to the corresponding high-K digital signal k -1 bit), controls the K-bit resistor string 111 to output a reference voltage signal (V) REF ). A reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121, configured to receive the reference voltage signal (V) REF )。
As shown in fig. 2, the fully parallel analog-to-digital conversion module 110 includes: and a comparison module 112 connected to the K-bit resistor string 111, wherein the comparison module 112 is configured to generate a temperature code corresponding to the high K-bit digital signal. Further, a corresponding high-K digital signal may be obtained based on the temperature encoding.
As an example, the switch module 130 includes switches corresponding to the number of coded bits of the temperature code, each bit of the temperature code controlling a respective one of the switches. As an example, the K-bit resistor string 111 may include 2 K 1 equivalent resistances, the comparison module 112 comprising 2 K 1 comparators each receiving a resistor corresponding to a segment reference voltage, and correspondingly, the switching module 130 may include 2 K -1 switch, each switch corresponding to a resistor corresponding to a segment reference voltage.
The sampling and conversion are explained as an example. Illustratively, during sampling, the fully parallel analog-to-digital conversion module 110 samples the analog input signal simultaneously with the N-bit successive approximation analog-to-digital conversion module 120. During conversion of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates a high K-bit number corresponding to the analog input signalAnd (4) carrying out temperature coding on the word signal, and further coding the temperature coding to obtain a high-K-bit digital signal corresponding to the analog input signal. The comparison module 112 feeds back the temperature code to the switch module 130. The switching module 130 controls the K-bit resistor string 111 to output a reference voltage signal (V) according to the temperature code REF ) The reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121 receives a reference voltage signal (V) REF ). At this time, the K-bit resistor string 111 in the multiplexing full-parallel analog-to-digital conversion module is used as a high K-bit digital-to-analog conversion module of the N-bit successive approximation analog-to-digital conversion module 120, the M-bit capacitor digital-to-analog conversion array 121 is used as a low M-bit digital-to-analog conversion module of the N-bit successive approximation analog-to-digital conversion module 120, the N-bit successive approximation analog-to-digital conversion module 120 directly starts to compare from the M-1 th bit through the M-bit capacitor digital-to-analog conversion array, and the rest is only needed to compare M times until a low M-bit digital signal corresponding to the analog input signal is generated.
Fig. 3 shows a schematic block diagram of another analog-to-digital conversion circuit according to an exemplary embodiment of the present application, and as shown in fig. 3, the analog-to-digital conversion circuit 100 further includes: a switch module 130 configured to control the K-bit resistor string 111 to output a reference voltage signal (V) according to the high K-bit digital signal REF ). A reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121, configured to receive the reference voltage signal (V) REF )。
As shown in fig. 3, the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112 connected to the K-bit resistor string 111, the comparison module 112 configured to generate a temperature code of a high K-bit digital signal corresponding to the analog input signal; and an encoding module 113 connected to the comparing module 112 and configured to generate a high-K digital signal corresponding to the analog input signal by the temperature encoding.
As an example, the switch module 130 may include K control signal terminals, each corresponding to one bit of the high K-bit digital signal. As an example, the switch module 130 may be a switch tree having K control signal terminals.
The sampling and conversion are explained as an example. Illustratively, during sampling, the fully parallel analog-to-digital conversion module 110 is in parallel with N bitsSuccessive approximation analog to digital conversion module 120 samples the analog input signal simultaneously. During the conversion period of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates a temperature code of the high-K digital signal corresponding to the analog input signal, and the encoding module 113 further encodes the temperature code to obtain the high-K digital signal corresponding to the analog input signal. The encoding module 113 feeds back the high K-bit digital signal to the switching module 130. The switch module 130 controls the K-bit resistor string 111 to output a reference voltage signal (V) according to the high K-bit digital signal REF ) The reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array 121 receives a reference voltage signal (V) REF ). At this time, the K-bit resistor string 111 in the multiplexing fully parallel analog-to-digital conversion module is used as a high K-bit digital-to-analog conversion module of the N-bit successive approximation analog-to-digital conversion module 120, the M-bit capacitor digital-to-analog conversion array 121 is used as a low M-bit digital-to-analog conversion module of the N-bit successive approximation analog-to-digital conversion module 120, the N-bit successive approximation analog-to-digital conversion module 120 directly compares the M-1 th bit through the M-bit capacitor digital-to-analog conversion array, and the remainder only needs to compare M times until a low M-bit digital signal corresponding to the analog input signal is generated.
Fig. 4 shows a schematic block diagram of another analog-to-digital conversion circuit according to an exemplary embodiment of the present application, and as shown in fig. 4, the analog-to-digital conversion circuit 100 further includes: a switch module 130.
As shown in fig. 4, the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112 connected to the K-bit resistor string 111, the comparison module 112 configured to generate a temperature code of a high K-bit digital signal corresponding to the analog input signal; and an encoding module 113 connected to the comparing module 112 and configured to generate a high-K digital signal corresponding to the analog input signal by the temperature encoding.
As shown in fig. 4, the N-bit successive approximation analog-to-digital conversion module 120 further includes: m-bit successive comparison logic 122 and a comparison unit 124. And the M-bit successive comparison logic 122 is configured to control the M-bit capacitance digital-to-analog conversion array 121 to perform low M-bit analog-to-digital conversion in the N-bit analog-to-digital conversion, so as to obtain a low M-bit digital signal corresponding to the analog input signal.
As shown in fig. 4, the analog-to-digital conversion circuit 100 further includes: a comparison unit 124. One input terminal of the comparing unit 124 is connected to the analog voltage output terminal of the M-bit capacitance digital-to-analog conversion array 121. The M-bit successive compare logic 122 listens for the compare output of the compare unit 124.
It should be noted that, in fig. 4, one dotted line is used to connect the coding circuit 113 and the switch module 130, and another dotted line is used to connect the comparison module 112 and the switch module 130, which is intended to illustrate that a signal of one of the coding circuit 113 or the comparison module 112 is used to control the switch module 130, and is not a limitation of the connection relationship.
Mode two
An N-bit successive approximation analog-to-digital conversion module 120 configured to: and controlling the M-bit capacitance digital-to-analog conversion array to perform digital-to-analog conversion according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, and obtaining a low-M-bit digital signal in the N-bit digital signal through the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string.
Fig. 5 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the present application, and further includes a switch module 130, as shown in fig. 5.
As shown in fig. 5, the N-bit successive approximation analog-to-digital conversion module 120 further includes: m-bit successive approximation logic 122 configured to output an M-bit control signal. The M-bit capacitance digital-to-analog conversion array 121 includes: the high-K-bit capacitor digital-to-analog conversion array, the low-M-K-bit capacitor digital-to-analog conversion array and the compensation capacitor.
The M-bit control signal is used for controlling the low M-K bit capacitor digital-to-analog conversion array and the K-bit resistor string to obtain a low M-bit digital signal. Specifically, the M-bit control signal includes a first control signal and a second control signal.
A switch module 130 connected to the M-bit successive approximation logic 122 and configured to control the K-bit resistor string to output a reference voltage signal (V) according to a first control signal REF ). A compensation capacitor configured to receive the reference voltage signal (V) REF ). And the low M-K bit capacitance digital-to-analog conversion array is configured to receive a second control signal for digital-to-analog conversion.
As shown in fig. 5, the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112 connected to the K-bit resistor string 111, the comparison module 112 configured to generate a temperature code of a high K-bit digital signal corresponding to the analog input signal; and an encoding module 113 connected to the comparing module 112 and configured to generate a high-K digital signal corresponding to the analog input signal by the temperature encoding. The high-K-bit capacitance digital-to-analog conversion array is configured to receive a temperature code corresponding to an analog input signal.
As an example, the switch module 130 includes K control signal terminals, each corresponding to one bit of the first control signal. As an example, the switch module 130 may be a switch tree with K control signals.
The sampling and conversion are described as an example. Illustratively, during sampling, the fully parallel analog-to-digital conversion module 110 samples the analog input signal simultaneously with the N-bit successive approximation analog-to-digital conversion module 120. During the conversion period of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates a bit temperature code of the high-K digital signal corresponding to the analog input signal, and the encoding module 113 further encodes the temperature code to obtain the high-K digital signal corresponding to the analog input signal. The coding module 113 feeds back the high-K bit digital signal to the high-K bit capacitance digital-to-analog conversion array of the M-bit capacitance digital-to-analog conversion array 121, so that the high-K bit capacitance digital-to-analog conversion array is turned over according to the high-K bit digital signal, and the N-bit successive approximation analog-to-digital conversion module 120 only needs to start conversion from the remaining low M-K bit capacitance digital-to-analog conversion array in the M-bit capacitance digital-to-analog conversion array until a low M-bit digital signal corresponding to the analog input signal is generated.
Specifically, in the process of converting to obtain the low M-bit digital signal, the second control signal of the M-bit control signal output by the M-bit successive approximation logic 122 controls the low M-K-bit capacitor digital-to-analog conversion array to perform the conversion, and the first control signal of the M-bit control signal controls the switch module 130, so that the switch module 130 controls the K-bit resistor string 111 to output the reference voltage signal (V) to the switch module 130 REF ) (ii) a The reference signal terminal of the compensation capacitor in the M-bit capacitor dac array 121 receives the reference voltage signal (V) REF ). That is, in the process, the conversion of the low M-bit digital signal is performed by the low M-K bit capacitor digital-to-analog conversion array in the M-bit capacitor digital-to-analog conversion arrayAnd the K-bit resistor string 111 in the fully parallel analog-to-digital conversion array.
Fig. 6 shows a schematic block diagram of another analog-to-digital conversion circuit according to an exemplary embodiment of the present application, as shown in fig. 6, further including a switch module 130.
As shown in fig. 6, the N-bit successive approximation analog-to-digital conversion module 120 further includes: m-bit successive approximation logic 122 configured to output an M-bit control signal. The M-bit capacitance digital-to-analog conversion array 121 includes: the high-K-bit capacitor digital-to-analog conversion array, the low-M-K-bit capacitor digital-to-analog conversion array and the compensation capacitor.
The M-bit control signal is used for controlling the low M-K bit capacitor digital-to-analog conversion array and the K-bit resistor string to obtain a low M-bit digital signal. Specifically, the M-bit control signal includes a first control signal and a second control signal.
The N-bit successive approximation analog-to-digital conversion module 120 further includes: and the encoding module 123 is configured to generate a temperature code corresponding to the first control signal.
A switch module 130 connected to the encoding module 123 and configured to control the K-bit resistor string to output a reference voltage signal (V) according to a temperature code corresponding to the first control signal REF ). A compensation capacitor configured to receive the reference voltage signal (V) REF ). And the low M-K bit capacitance digital-to-analog conversion array is configured to receive a second control signal for digital-to-analog conversion.
As an example, the switch module 130 includes a corresponding number of switches corresponding to the number of encoded bits of the temperature code, each switch corresponding to a segmented reference voltage corresponding to a resistance of the K-bit resistor string 111.
As shown in fig. 6, the fully parallel analog-to-digital conversion module 110 includes: a comparison module 112 connected to the K-bit resistor string 111, the comparison module 112 configured to generate a temperature code of a high K-bit digital signal corresponding to the analog input signal; and an encoding module 113 connected to the comparing module 112 and configured to generate a high-K digital signal corresponding to the analog input signal by the temperature encoding. The high-K bit capacitance digital-to-analog conversion array is configured to receive a high-K bit digital signal corresponding to the analog input signal.
The sampling and conversion are explained as an example. Illustratively, during sampling, the fully parallel analog-to-digital conversion module 110 samples the analog input signal simultaneously with the N-bit successive approximation analog-to-digital conversion module 120. During the conversion period of the fully parallel analog-to-digital conversion module 110, the comparison module 112 generates a temperature code of the high-K digital signal corresponding to the analog input signal, and the encoding module 113 further encodes the temperature code to obtain the high-K digital signal corresponding to the analog input signal. The coding module 113 feeds back the high-K bit digital signal to the high-K bit capacitance digital-to-analog conversion array of the M-bit capacitance digital-to-analog conversion array 121, so that the high-K bit capacitance digital-to-analog conversion array is inverted according to the high-K bit digital signal, and the N-bit successive approximation analog-to-digital conversion module 120 only needs to start conversion from the remaining low M-K bit capacitance digital-to-analog conversion array in the M-bit capacitance digital-to-analog conversion array until a low M-bit digital signal corresponding to the analog input signal is generated.
Specifically, in the process of obtaining a low M-bit digital signal through conversion, a second control signal of M-bit control signals output by the M-bit successive approximation logic 122 controls the low M-K-bit capacitance digital-to-analog conversion array to perform conversion, and a first control signal of the M-bit control signals controls the switch module 130, so that the switch module 130 controls the K-bit resistor string 111 to output a reference voltage signal (VREF); the reference signal terminal of the compensation capacitor in the M-bit capacitor dac array 121 receives a reference voltage signal (VREF). That is, in the process, the conversion of the low M-bit digital signal is completed by the low M-K bit capacitor digital-to-analog conversion array in the M-bit capacitor digital-to-analog conversion array and the K-bit resistor string 111 in the fully parallel analog-to-digital conversion array.
As shown in fig. 5 and 6, the analog-to-digital conversion circuit 100 further includes: a comparison unit 124. One input terminal of the comparison unit 124 is connected to the analog voltage output terminal of the M-bit capacitor digital-to-analog conversion array 121. The M-bit successive compare logic 122 listens for the compare output of the compare unit 124.
Some examples of the present embodiment are described below.
Fig. 7 shows a schematic structural diagram of an example of an analog-to-digital conversion circuit of the exemplary embodiment of the present application, which is an N-bit Flash SAR hybrid ADC, as shown in fig. 7, and includes a K-bit Flash ADC, an M-bit DAC differential capacitor array, a comparator COMP, an M-bit SAR logic, an encoding circuit 1, and an encoding circuit 2.
The K-bit Flash ADC comprises sampling capacitors CS1 and CS2, a K-bit resistor string, and a voltage value of 2 × (2) K -1) comparators. In the ADC sampling stage, the Flash ADC and the SAR ADC are simultaneously sampled. After sampling is completed, a temperature code result TP 2 corresponding to the differential signal can be obtained in one clock cycle K -1:0]And TP 2 K -1:0]Then, the encoding circuit 1 obtains the K bit binary code result T [ K-1:0]]. And the comparison result of the K-bit Flash ADC is fed back to the K-bit resistor string (as a high K-bit resistor array in the SAR ADC) through the coding circuit 1.
The N-bit SAR ADC comprises a K-bit resistor string, an M-bit DAC differential capacitor array, a comparator COMP, M-bit SAR logic and the like, wherein the M-bit DAC differential capacitor array comprises an M-bit capacitor array, and the DAC differential capacitor array comprises but is not limited to a binary weight DAC differential capacitor array and a bridge DAC differential capacitor array. After the coding circuit 1 feeds back the comparison result of the K-bit Flash ADC to the high K bit in the SAR ADC, the SAR ADC starts the comparison of the M-1 th bit, and the M times of comparison are remained. The high K bits of the SAR ADC are directly multiplexed with the K bit resistor string in the Flash ADC and are controlled by two groups of switches SW1 and SW 2. The DAC differential capacitor array comprises an M-bit capacitor array, and the M-bit capacitor array is controlled through M-bit SAR logic. The number of bits of the resistor string which can be reused by the SAR ADC is less than or equal to K bits, the DAC array comprises an M-bit capacitor array, and the total number of capacitors is 2 x 2 M Compared with the traditional mode, 2 is reduced N -2 M ) A capacitor. For example, for a SAR ADC with N-12, K-4, and M-8, the number of capacitors that can be saved is 2 (2) 12 -2 8 ) 7680, the saved capacitance portion accounts for about 94% of the capacitance of the traditional structure.
The coding circuit 2 accumulates K-bit binary code result T [ K-1:0] of the Flash ADC and M-bit binary code result D [ M-1:0] of the SAR ADC to obtain N-bit binary code result D [ N-1:0 ].
Fig. 8 shows a schematic structural diagram of another example of an analog-to-digital conversion circuit of the exemplary embodiment of the present application, which is an N-bit Flash SAR hybrid ADC, and the circuit includes a K-bit Flash ADC, an M-bit DAC differential capacitor array, a comparator COMP, an M-bit SAR logic, an encoding circuit 1, and an encoding circuit 2.
The K-bit Flash ADC comprises sampling capacitors CS1 and CS2, a K-bit resistor string, and a voltage value of 2 × (2) K -1) comparators. In ADC sampling stage, Flash ADC and SAR ADC are sampled simultaneously, after sampling is completed, temperature code result TP 2 corresponding to differential signal can be obtained in one clock period K -1:0]And TP 2 K -1:0]Then, a K-bit binary code result T [ K-1:0] can be obtained by the coding circuit 1]. And the comparison result of the K-bit Flash ADC is fed back to a high-K-bit capacitor array in the SAR ADC through the coding circuit 1.
The N-bit SAR ADC comprises a K-bit resistor string, an M-bit DAC differential capacitor array, a comparator COMP, M-bit SAR logic and the like, wherein the M-bit DAC differential capacitor array comprises a high K-bit capacitor array and a low M-K-bit capacitor array. Wherein the DAC differential capacitor array is not limited to a binary weighted DAC differential capacitor array and a bridged DAC differential capacitor array. After the coding circuit 1 feeds back the comparison result of the K-bit Flash ADC to the high K-bit capacitor array in the SAR ADC, the SAR ADC starts the M-1 th bit comparison, and the M times of comparison are remained. The lowest bit capacitance CPT (0) in the high K bits of the DAC differential capacitance array is 2 times the highest bit capacitance CP (M-K-1) in the low M-K bits. The low M bit of the SAR ADC comprises an M-K bit capacitor array and a K bit resistor string, wherein the K bit resistor string is multiplexed with the resistor string in the Flash ADC and passes through two groups of switches SW1 and SW 2. And controlling the M-K bit capacitor array and the K bit resistor string through M bit SAR logic. The bit number of the resistor string which can be reused by the SAR ADC is less than or equal to K bits, the DAC array only needs an M-bit capacitor array, and the total capacitor number is 2 x 2 M Compared with the traditional mode, 2 is reduced N -2 M ) A capacitor. For example, for a SAR ADC with N-12, K-4, and M-8, the number of capacitors that can be saved is 2 (21) 2 -2 8 ) 7680, the saved capacitance portion accounts for about 94% of the capacitance of the traditional structure.
The coding circuit 2 accumulates K-bit binary code result T [ K-1:0] of the Flash ADC and M-bit binary code result D [ M-1:0] of the SAR ADC to obtain N-bit binary code result D [ N-1:0 ].
The embodiment also provides an analog-to-digital conversion method of the analog-to-digital conversion circuit, which is applied to the analog-to-digital conversion circuit in the embodiment of the application.
Fig. 9 shows a flowchart of an analog-to-digital conversion method according to an exemplary embodiment of the present application, and as shown in fig. 9, the method includes steps S901 to S902.
Step S901, the full parallel analog-to-digital conversion module samples and converts the analog input signal to obtain a high K-bit digital signal corresponding to the analog input signal.
Wherein, the module of full parallel analog-to-digital conversion includes: a K-bit resistor string; the N-bit successive approximation analog-to-digital conversion module comprises: an M-bit capacitance digital-to-analog conversion array, where N ═ K + M, and K, M and N are positive integers.
Step S902, the N-bit successive approximation analog-to-digital conversion module obtains a low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and the low M-bit digital signal is obtained in the N-bit analog-to-digital conversion according to the high K-bit digital signal.
By the analog-to-digital conversion method of the embodiment, a resistor-capacitor hybrid structure is formed by the K-bit resistor string of the full-parallel analog-to-digital conversion module and the M-bit capacitor digital-to-analog conversion array of the N-bit successive approximation analog-to-digital conversion module, so that N-bit digital-to-analog conversion is realized. By multiplexing the K-bit resistor strings in the fully-parallel analog-to-digital conversion module, the number of capacitors of a capacitor digital-to-analog conversion array in the successive approximation analog-to-digital conversion module is reduced, the circuit area is reduced, and the power consumption is reduced.
As an embodiment, the step S902 includes:
and D/A conversion is carried out on the high K-bit digital signal through the K-bit resistor string, and a low M-bit digital signal is obtained through the M-bit capacitor D/A conversion array.
As an example, performing digital-to-analog conversion on a high K-bit digital signal through a K-bit resistor string, and obtaining a low M-bit digital signal through an M-bit capacitor digital-to-analog conversion array includes:
and controlling the K-bit resistor string to output a first reference voltage signal according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, wherein the reference signal end corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array receives the first reference voltage signal.
As another embodiment, the obtaining, by the N-bit successive approximation analog-to-digital conversion module, a low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array includes:
and controlling the M-bit capacitance digital-to-analog conversion array to perform digital-to-analog conversion according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, and obtaining the low-M-bit digital signal through the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string.
As an example, an M-bit capacitance digital-to-analog conversion array includes: the high-K-bit capacitor digital-to-analog conversion array, the low-M-K-bit capacitor digital-to-analog conversion array and the compensation capacitor are arranged in the array;
wherein, obtain low M bit digital signal through M bit electric capacity digital-to-analog conversion array and K bit resistance string, include:
outputting an M-bit control signal, wherein the M-bit control signal is used for controlling the low M-K-bit capacitor digital-to-analog conversion array and the K-bit resistor string to obtain a low M-bit digital signal; and the M-bit control signal comprises a first control signal and a second control signal;
controlling the K-bit resistor string to output a second reference voltage signal according to the first control signal, wherein a reference signal end corresponding to the compensation capacitor is configured to receive the second reference voltage signal;
and controlling the low M-K bit capacitor digital-to-analog conversion array according to the second control signal to perform digital-to-analog conversion.
The embodiment of the application also provides a chip, and the chip comprises the analog-to-digital conversion circuit. A Chip (Integrated Circuit, IC) is also called a Chip, and the Chip may be, but is not limited to, an SOC (System on Chip) Chip or an SIP (System in package) Chip. The chip adopts a resistor-capacitor hybrid structure formed by a K-bit resistor string of a full-parallel analog-to-digital conversion module and an M-bit capacitor digital-to-analog conversion array of an N-bit successive approximation analog-to-digital conversion module, so as to realize N-bit digital-to-analog conversion. By multiplexing the K-bit resistor strings in the fully-parallel analog-to-digital conversion module, the number of capacitors of a capacitor digital-to-analog conversion array in the successive approximation analog-to-digital conversion module is reduced, the circuit area is reduced, and the power consumption is reduced.
The embodiment of the application also provides electronic equipment, which comprises an equipment main body and the chip arranged in the equipment theme. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a quick charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus pen, a true wireless headset, a screen in an automobile, an intelligent wearable device, a mobile terminal, and an intelligent home device. The intelligent wearable device comprises but is not limited to an intelligent watch, an intelligent bracelet and a cervical vertebra massager. Mobile terminals include, but are not limited to, smart phones, laptops, tablets, point of sale (POS) machines. The intelligent household equipment comprises but is not limited to an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp. The electronic equipment realizes N-bit digital-to-analog conversion by forming a resistor-capacitor mixed structure by using a K-bit resistor string of a full-parallel analog-to-digital conversion module and an M-bit capacitor digital-to-analog conversion array of an N-bit successive approximation analog-to-digital conversion module. By multiplexing the K-bit resistor strings in the fully-parallel analog-to-digital conversion module, the number of capacitors of a capacitor digital-to-analog conversion array in the successive approximation analog-to-digital conversion module is reduced, the circuit area is reduced, and the power consumption is reduced.
Although the present application has been described with reference to the preferred embodiments, it is to be understood that the present application is not limited to the disclosed embodiments, but rather, the present application is intended to cover various modifications, equivalents and alternatives falling within the spirit and scope of the present application.
Claims (13)
1. An analog-to-digital conversion circuit, comprising:
a fully parallel analog-to-digital conversion module comprising: a K-bit resistor string;
the N-bit successive approximation analog-to-digital conversion module comprises: the digital-to-analog conversion array comprises an M-bit capacitor digital-to-analog conversion array, a comparator and a comparator, wherein the M-bit capacitor digital-to-analog conversion array is used for carrying out N-bit analog-to-digital conversion on an analog input signal and obtaining an N-bit digital signal, the N-bit digital signal comprises a high K-bit digital signal and a low M-bit digital signal, N is K + M, and K, M and N are positive integers;
wherein:
the fully parallel analog-to-digital conversion module is configured to sample and convert the analog input signal to obtain the high-K-bit digital signal;
the N-bit successive approximation analog-to-digital conversion module is configured to obtain the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and the low M-bit digital signal is obtained in N-bit analog-to-digital conversion according to the high K-bit digital signal.
2. The analog-to-digital conversion circuit of claim 1, wherein the N-bit successive approximation analog-to-digital conversion module is configured to: and performing digital-to-analog conversion on the high K-bit digital signal through the K-bit resistor string, and obtaining the low M-bit digital signal through the M-bit capacitor digital-to-analog conversion array.
3. The analog-to-digital conversion circuit of claim 2, further comprising:
a first switch module configured to control the K-bit resistor string to output a first reference voltage signal according to the high-K-bit digital signal or a temperature code corresponding to the high-K-bit digital signal;
the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array is configured to receive the first reference voltage signal.
4. The analog-to-digital conversion circuit of claim 1, wherein the N-bit successive approximation analog-to-digital conversion module is configured to: and controlling the M-bit capacitance digital-to-analog conversion array to perform digital-to-analog conversion according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, and obtaining the low-M-bit digital signal through the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string.
5. The analog-to-digital conversion circuit of claim 4, wherein the M-bit capacitive digital-to-analog conversion array comprises: the high-K-bit capacitor digital-to-analog conversion array, the low-M-K-bit capacitor digital-to-analog conversion array and the compensation capacitor are arranged in the array;
the fully parallel analog-to-digital conversion module is configured to control the high-K bit capacitance digital-to-analog conversion array according to the high-K bit digital signal or a temperature code corresponding to the high-K bit digital signal;
the N-bit successive approximation analog-to-digital conversion module includes: an M-bit successive approximation logic unit configured to output an M-bit control signal for controlling the low M-K bit capacitive digital-to-analog conversion array and the K-bit resistor string to obtain the low M-bit digital signal.
6. The analog-to-digital conversion circuit of claim 5, wherein the M-bit control signal comprises a first control signal and a second control signal; the analog-to-digital conversion circuit further includes:
a second switch module configured to control the K-bit resistor string according to the first control signal to output a second reference voltage signal, wherein a reference signal terminal corresponding to the compensation capacitor is configured to receive the second reference voltage signal;
the low M-K bit capacitance digital-to-analog conversion array is configured to receive the second control signal for digital-to-analog conversion.
7. An analog-to-digital conversion method of an analog-to-digital conversion circuit, the analog-to-digital conversion circuit comprising: a fully parallel analog-to-digital conversion module comprising: a K-bit resistor string; the N-bit successive approximation analog-to-digital conversion module comprises: the digital-to-analog conversion array comprises an M-bit capacitance digital-to-analog conversion array and an N-bit successive approximation analog-to-digital conversion module, wherein the N-bit successive approximation analog-to-digital conversion module is used for carrying out N-bit analog-to-digital conversion on an analog input signal and obtaining N-bit digital signals, and the N-bit digital signals comprise high-K-bit digital signals and low-M-bit digital signals; wherein N is K + M, and K, M and N are positive integers;
the analog-to-digital conversion method comprises the following steps:
the full parallel analog-to-digital conversion module samples and converts an analog input signal to obtain the high-K-bit digital signal;
the N-bit successive approximation analog-digital conversion module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-analog conversion array, and the low M-bit digital signal is obtained in N-bit analog-digital conversion according to the high K-bit digital signal.
8. The analog-to-digital conversion method according to claim 7, wherein the N-bit successive approximation analog-to-digital conversion module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and includes:
and performing digital-to-analog conversion on the high-K-bit digital signal through the K-bit resistor string, and obtaining the low-M-bit digital signal through the M-bit capacitor digital-to-analog conversion array.
9. The analog-to-digital conversion method according to claim 8, wherein the performing digital-to-analog conversion on the high K-bit digital signal through the K-bit resistor string and obtaining the low M-bit digital signal through the M-bit capacitor digital-to-analog conversion array comprises:
and controlling the K-bit resistor string to output a first reference voltage signal according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, wherein the reference signal end corresponding to each capacitor in the M-bit capacitor digital-to-analog conversion array receives the first reference voltage signal.
10. The analog-to-digital conversion method according to claim 7, wherein the N-bit successive approximation analog-to-digital conversion module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog conversion array, and includes:
and controlling the M-bit capacitance digital-to-analog conversion array to perform digital-to-analog conversion according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal, and obtaining the low-M-bit digital signal through the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string.
11. The analog-to-digital conversion method according to claim 10, wherein the M-bit capacitance digital-to-analog conversion array comprises: the high-K-bit capacitor digital-to-analog conversion array, the low-M-K-bit capacitor digital-to-analog conversion array and the compensation capacitor are arranged in the array;
wherein the obtaining of the low M-bit digital signal through the M-bit capacitance digital-to-analog conversion array and the K-bit resistor string comprises:
outputting an M-bit control signal, wherein the M-bit control signal is used for controlling the low M-K-bit capacitor digital-to-analog conversion array and the K-bit resistor string to obtain the low M-bit digital signal; and the M-bit control signals comprise a first control signal and a second control signal;
controlling the K-bit resistor string to output a second reference voltage signal according to the first control signal, wherein a reference signal end corresponding to the compensation capacitor is configured to receive the second reference voltage signal;
and controlling the low M-K bit capacitor digital-to-analog conversion array according to the second control signal to perform digital-to-analog conversion.
12. A chip comprising an analog-to-digital conversion circuit according to any one of claims 1 to 6.
13. An electronic device, comprising: an analog to digital conversion circuit as claimed in any of claims 1 to 6.
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| CN116318154B (en) * | 2023-05-17 | 2023-09-15 | 南方电网数字电网研究院有限公司 | Analog-to-digital conversion device and signal conversion equipment |
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