CN115021744B - Programmable wiring nano relay array, and optimized wiring method and system - Google Patents
Programmable wiring nano relay array, and optimized wiring method and system Download PDFInfo
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- CN115021744B CN115021744B CN202210952751.8A CN202210952751A CN115021744B CN 115021744 B CN115021744 B CN 115021744B CN 202210952751 A CN202210952751 A CN 202210952751A CN 115021744 B CN115021744 B CN 115021744B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
- H02H3/02—Details
- H02H3/021—Details concerning the disconnection itself, e.g. at a particular instant, particularly at zero value of current, disconnection in a predetermined order
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to a programmable wiring nano relay array, an optimized wiring method and a system, relating to the field of nano relays, wherein the array comprises a switch array control unit and a plurality of nano relay units connected in array; the nano relay unit comprises a nano relay, a plurality of channel switches and a gating switch; the plurality of channel switches and the plurality of gate switches form a rectangle; the channel switches are all arranged at the vertex of the rectangle; each gating switch is arranged between the two channel switches; each channel switch is connected with the adjacent gating switch; the nanometer relay is arranged in the rectangle; each gating switch is connected with the nano relay; the switch array control unit is connected with each channel switch; the rectangles between two adjacent nanometer relay units share two channel switches and one gating switch. The invention can improve the flexibility of wiring, thereby improving the flexibility of power chip service processing and the service efficiency of the nano relay.
Description
Technical Field
The invention relates to the technical field of relays, in particular to a programmable wiring nano relay array, and an optimized wiring method and system.
Background
The existing electric power industrial control device generally adopts a general CPU chip, has the characteristics of millisecond-level data acquisition, megawatt-level message flow and ten-megawatt-level communication bandwidth, and cannot meet the requirements of microsecond-level dynamic response, hundred-megawatt-level network storm flow and kilomega-level service data transmission of a novel electric power system.
The nano relay is a special integrated circuit unit specially used for processing power service data in a power chip, and aims to provide high real-time and high-performance computing power for a novel power system through a hardware circuit special for service. At present, the research and application of the nano relay technology are still in the beginning stage. The existing invention aiming at the nano-relay completes fixed service processing in a mode of hard connection of a plurality of combinational logic circuits, and each nano-relay is only responsible for completing fixed steps in fixed power service and cannot be called by other service processes. Therefore, the service processing of the power chip lacks flexibility, and the usage efficiency of the nano-relay is low.
Disclosure of Invention
The invention aims to provide a programmable wiring nano relay array, an optimized wiring method and a system, which are used for improving the flexibility of wiring, thereby improving the flexibility of power chip service processing and the use efficiency of nano relays.
In order to achieve the purpose, the invention provides the following scheme:
a programmable wiring nano relay array comprises a switch array control unit and a plurality of nano relay units connected in an array; the nano relay unit comprises a nano relay, a plurality of channel switches and a plurality of gating switches;
a plurality of the channel switches and a plurality of the gate switches form a rectangle; the channel switches are all arranged at the vertex of the rectangle; one of the vertices corresponds to one of the channel switches; different vertexes correspond to different channel switches; each gating switch is arranged between two channel switches; each channel switch is connected with the adjacent gating switch; the nano relay is arranged in the rectangle; each gating switch is connected with the nano relay;
the switch array control unit is connected with each channel switch; the switch array control unit is used for controlling the conduction state of the channel switch according to the power service; the channel switch is used for communicating any two gating switches connected with the channel switch; the rectangles between two adjacent nanometer relay units share two channel switches and one gating switch.
Optionally, the programmable wiring nano-relay array further comprises wiring channels, and each channel switch is connected with the adjacent gating switch through the wiring channel; each gating switch is connected with the nano relay through the wiring channel.
Optionally, the nano-relay includes a combinational logic circuit and an input-output circuit connected to the combinational logic circuit; the input and output circuit is connected with the gating switch.
Optionally, the programmable wiring nanorelay array further comprises a selector; the selector is used for connecting the switch array control unit and the channel switch.
An optimized wiring method of a programmable wiring nano-relay array is applied to any one of the programmable wiring nano-relay arrays, and comprises the following steps:
acquiring a power service and determining a nanometer relay sequence according to the power service;
determining a starting nano relay and an end point nano relay according to the nano relay sequence and the wiring cost; the wiring cost is the number of channel switches or the length of a wiring channel;
traversing the wiring cost of two adjacent stages of nano relays from the initial nano relay to the end nano relay to obtain a nano relay number sequence and a wiring cost sequence;
determining a wiring cost sum according to the wiring cost sequence;
and selecting the nanometer relay number sequence corresponding to the wiring cost sequence with the minimum sum of the wiring costs as a wiring scheme by utilizing a sequencing method.
Optionally, after the selecting, by using a sorting method, a nano-relay number sequence corresponding to the wiring cost sequence with the smallest wiring cost as a wiring scheme, the method further includes:
if a plurality of nano relay number sequences corresponding to the wiring cost sequence with the minimum wiring cost sum exist, calculating the variance of the wiring cost sequence according to the wiring cost sequence;
and selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum variance of the wiring cost sequence as a wiring scheme.
An optimized wiring system of a programmable wiring nano-relay array, the optimized wiring system of the programmable wiring nano-relay array being applied to any one of the programmable wiring nano-relay arrays, the optimized wiring system of the programmable wiring nano-relay array comprising:
the acquisition module is used for acquiring a power service and determining a nano relay sequence according to the power service;
the starting nano relay and end point nano relay determining module is used for determining a starting nano relay and an end point nano relay according to the nano relay sequence and the wiring cost; the wiring cost is the number of channel switches or the length of a wiring channel;
the nanometer relay number sequence and wiring cost sequence determining module is used for traversing the wiring cost of the adjacent two-stage nanometer relay from the initial nanometer relay to the terminal nanometer relay to obtain a nanometer relay number sequence and a wiring cost sequence;
the summing module is used for determining the sum of the wiring costs according to the wiring cost sequence;
and the sequencing module is used for selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum wiring cost sum as a wiring scheme by utilizing a sequencing method.
Optionally, the routing optimization system for the programmable routing nanorelay array further comprises:
a variance calculating module, configured to calculate a variance of the wiring cost sequence according to the wiring cost sequence if there are multiple nano-relay number sequences corresponding to the wiring cost sequence with the minimum sum of the wiring costs;
and the variance selection module is used for selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum variance as a wiring scheme.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a programmable wiring nano relay array, which comprises a switch array control unit and a plurality of nano relay units connected with the array; the nano relay unit comprises a nano relay, a plurality of channel switches and a plurality of gating switches; a plurality of the channel switches and a plurality of the gate switches form a rectangle; a plurality of the channel switches are all arranged at the vertex of the rectangle; one of the vertices corresponds to one of the channel switches; different vertexes correspond to different channel switches; each gating switch is arranged between two channel switches; each channel switch is connected with the adjacent gating switch; the nano relay is arranged in the rectangle; each gating switch is connected with the nano relay; the switch array control unit is connected with each channel switch; the switch array control unit is used for controlling the conduction state of the channel switch according to the power service; the channel switch is used for communicating any two gating switches connected with the channel switch; the rectangles between two adjacent nanometer relay units share two channel switches and one gating switch. Different wiring schemes are selected through the communication of the channel switches and the gating switches, so that the wiring flexibility is improved, and the flexibility of power chip service processing and the use efficiency of the nano relay are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a programmable wired nanorelay array structure provided by the present invention;
FIG. 2 is a schematic diagram of a connection relationship between switch array control units according to the present invention;
FIG. 3 is a connection diagram of a switch array control unit according to the present invention;
FIG. 4 is a schematic diagram of the minimum routing calculation for the wiring cost of the nano-relay array provided by the present invention;
FIG. 5 is a flow chart of a method for optimizing wiring of a programmable wiring nanorelay array provided by the present invention;
fig. 6 is a schematic diagram of a specific work flow of the method for optimizing the wiring of the programmable wiring nanorelay array provided by the invention.
Description of the symbols:
10-programmable channel switch, 20-wiring channel, 30-gating switch, 40-nanometer relay, 50-combinational logic circuit, 60-switch control channel, 70-switch array control unit and 80-selector.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a programmable wiring nano relay array, an optimized wiring method and a system, which are used for improving the flexibility of wiring, thereby improving the flexibility of power chip service processing and the use efficiency of a nano relay.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, the programmable wired nano-relay array provided by the present invention includes a switch array control unit 70 and a plurality of nano-relay units connected in an array; the nano-relay unit includes a nano-relay 40, a plurality of channel switches, and a plurality of gate switches 30.
A plurality of the channel switches and a plurality of the gate switches 30 form a rectangle; a plurality of the channel switches are all arranged at the vertex of the rectangle; one of the vertices corresponds to one of the channel switches; different vertexes correspond to different channel switches; each of the gate switches 30 is disposed between two of the channel switches; each of the channel switches is connected to the adjacent gate switch 30; the nano-relay 40 is arranged in the rectangle; each of the gate switches 30 is connected to the nano-relay 40. In practice, the gating switches 30 are arranged on the sides of the rectangle.
As shown in fig. 2 and 3, the switch array control unit 70 is connected to each of the channel switches; the switch array control unit 70 is configured to control the on state of the channel switch according to the power service; the channel switch is used for communicating any two gating switches 30 connected with the channel switch; the rectangles between two adjacent nano-relay units share two of the channel switches and one of the gate switches 30. For example, one nanorelay unit in the present invention includes four channel switches and four gate switches 30, and when one programmable wired nanorelay array includes two nanorelay units, there are six channel switches and seven gate switches 30, and the two nanorelay units share the central channel switch and gate switches 30.
The I/O interface in fig. 1 is mainly a data sampling signal, in the relay protection device, current and voltage are converted into digital sampling signals through PT sampling, CT sampling, and ADC, and input to the nano relay array, and the nano relay array performs calculation through the input sampling signal, so that power services such as judgment (protection) of relay protection, power quality monitoring (monitoring), and power metering (metering) can be realized, and the sampling signal data enters the nano relay array from the I/O interface through a data transmission bus. In particular the I/O interface, is connected to the gate switch 30.
In practical application, the programmable wiring nano-relay array further comprises wiring channels 20, and each channel switch is connected with the adjacent gating switch 30 through the wiring channel 20; each of the gate switches 30 is connected to the nano-relay through the wiring channel 20. The wiring channel 20 of the nano relay unit forms a rectangle through connection with other devices, and the wiring channel 20 provides a connection function among the nano relay 40, the gating switch 30 and the programmable channel switch 10. The wiring channel 20 also has a function of transmitting data and control instructions.
The programmable wiring nanorelay array also includes a selector 80; the selector 80 is used to connect the switch array control unit 70 and the channel switch. The selector 80 essentially performs the selection range multiplication by the cascade expansion of the selector 80. Whether implemented by cascading extensions or by directly designing selectors to meet the requirements, this portion functions to "select", i.e., select, the target programmable channel switch 10.
In practical applications, as shown in fig. 3, the channel switches are programmable channel switches 10, which provide the wiring function of the matrix-type wiring channels 20, and are controlled by the switch array control unit 70, and each programmable channel switch 10 has 6 bidirectional connection states, i.e., a left upper connection, a left lower connection, a left right connection, a top and bottom connection, a right upper connection, and a right lower connection. Each channel switch is composed of 6 internal switches, each internal switch is a bidirectional switch, and the 6 internal switches are respectively connected with the upper left, the lower left, the left and the right, the upper and the lower right, and the upper and the lower right of the wiring channel 20. The internal switches are normally closed, and the on/off of the internal switches is controlled by the switch array control unit 70 through the selector 80, specifically, the on/off state of each internal switch of the programmable channel switch 10 is uniformly controlled by the switch array control unit 70 through the switch control channel 60.
The gate switch 30 provides a connection function of the nano-relay 40 with the wiring channel 20, the nano-relay 40 can input and output data when the gate switch 30 is turned on, and the nano-relay 40 cannot input and output data when the gate switch 30 is turned off. The gating switch 30 is controlled by the on-off state of the programmable channel switch 10 connected to both ends thereof, and if and only if the programmable channel switches at both ends thereof are in the on state, the gating switch 30 is on. Each of the nano-relays 40 is connected to the wiring channel 20 through four gate switches 30 of up, down, left, and right.
In practical application, the nano relay comprises a combinational logic circuit and an input/output circuit connected with the combinational logic circuit; the input-output circuit is connected to the gate switch 30. When the gate switch 30 is turned on, the input-output circuit operates, and when the gate switch 30 is turned off, the input-output circuit is turned off. The essence of the combinational logic circuit is a hardware circuit module formed by a layout formed by a front-end design (code design) and a back-end design (converted into an integrated circuit layout) of a power algorithm and a tape-out manufacturing. It takes the form of a combinational logic circuit that implements the function of a power service algorithm. The combinational logic circuit comprises at least one circuit of a feature extraction circuit, a numerical value comparison circuit, a logic judgment circuit, a signal conditioning circuit, a band-limited filter circuit, a sample-and-hold circuit, an analog/digital conversion circuit, a message decoding circuit, a time synchronization circuit, a low-pass filter circuit and an interpolation circuit.
The nano relay 40 is composed of a combinational logic circuit unit containing different power hardware algorithms and an input/output circuit, and completes specific power business process calculation. The input/output circuit has four channels connected to the four gate switches 30, respectively.
Wherein, the nano-relay 40 is at least one nano-relay selected from a storm suppressing nano-relay, a sampling value synchronous nano-relay, a data filtering nano-relay, an SV message receiving and filtering nano-relay, an SV message sending nano-relay, a Goose message receiving and filtering nano-relay, a Goose message sending nano-relay, an MMS message receiving and filtering nano-relay, an MMS sending nano-relay, a GOOSE/SV/MMS three-in-one sending nano-relay, an HDLC coding nano-relay, an HSR algorithm nano-relay, a B code time synchronization nano-relay, a data compression nano-relay, a cycle wave calculation nano-relay, a direct current component calculation nano-relay, a root mean square calculation nano-relay, an FFT calculation nano-relay, a differential calculation nano-relay, a phase/sequence amount calculation nano-relay, a frequency measurement nano-relay, a frequency tracking nano-relay, a characteristic extraction nano-relay, a numerical value comparison nano-relay, a logic judgment nano-relay, a signal conditioning nano-relay, a band-limited filtering nano-relay, a sampling hold relay and an analog/digital conversion nano-relay.
The programmable wiring nano relay array is a matrix array, the wiring channels 20 are distributed horizontally and longitudinally, the parts of the horizontal wiring channels 20 intersected with the longitudinal wiring channels are connected by a programmable channel switch 10, and the programmable channel switch 10 can control 6 communication modes of the horizontal wiring channels 20 and the longitudinal wiring channels 20; the gating switch 30 is connected with 2 adjacent programmable channel switches 10 through the wiring channel 20, four programmable channel switches 10 form a minimum rectangle, the inside of the minimum rectangle is provided with a nano-relay 40, and the nano-relay 40 is connected with 4 gating switches 30 existing between the four programmable switches forming the minimum rectangle. The connection relationship between the switch array controller and the programmable channel switch 10 is shown in fig. 3, and the switch array control unit 70 is connected to the programmable channel switch 10 through the switch control channel 60 to control 6 communication modes of the programmable channel switch 10.
The switch array control unit 70 inputs the power service type requirement, the position list and state of the nano-relay 40, and the on-off state of the programmable switch, performs power service optimization wiring calculation, forms a combined switching scheme of the programmable channel switches 10, and controls the internal switch gating of the corresponding programmable channel switches 10 through the selector 80. The nano-relay 40 performs calculation of specific power service through calculation and control loop formed by the matrix type wiring channel 20, the gating switch 30 and the programmable channel switch 10. The power service types comprise power protection, power quality monitoring and the like.
As shown in fig. 5, the present invention provides an optimized wiring method for a programmable wiring nano-relay array, which is applied to the programmable wiring nano-relay array, and the optimized wiring method for the programmable wiring nano-relay array includes:
step 501: and acquiring power service and determining a nanometer relay sequence according to the power service.
Step 502: determining a starting nano relay and an end point nano relay according to the nano relay sequence and the wiring cost; the wiring penalty is the number of channel switches or the length of the wiring channels.
Step 503: and traversing the wiring cost of the adjacent two stages of nano relays from the starting nano relay to the end nano relay to obtain a nano relay number sequence and a wiring cost sequence.
Step 504: and determining a wiring cost sum according to the wiring cost sequence.
Step 505: and selecting the nanometer relay number sequence corresponding to the wiring cost sequence with the minimum sum of the wiring costs as a wiring scheme by utilizing a sequencing method.
As an optional implementation manner, after the selecting, by using a sorting method, a nano relay number sequence corresponding to the wiring cost sequence with the minimum wiring cost as a wiring scheme, the method further includes:
and if a plurality of nano relay number sequences corresponding to the wiring cost sequence with the minimum wiring cost sum exist, calculating the variance of the wiring cost sequence according to the wiring cost sequence.
And selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum variance of the wiring cost sequence as a wiring scheme.
As shown in fig. 6, the present invention further provides a specific flow of the method for optimizing wiring of the programmable wiring nanorelay array in practical application, wherein the target of optimization is the minimum wiring cost, and the wiring cost is selectable, including 2 options of the number of programmable channel switches or the length of the wiring channel; without loss of generality, the execution steps of an electric power service are [ a, B, C, D, E ] in sequence, the sequence of the corresponding nano-relay types is [ a, B, C, D, E ], wherein a, B, C, D, E are the nano-relay types capable of realizing five steps of a, B, C, D, E of the electric power service, specifically 5 types of nano-relays, which are etched in a nano-relay array during chip design, and the specific steps of optimizing wiring are as follows:
and step one, defining the wiring cost, for example, defining the least programmable channel switch number passing between the upper-level nano relay and the lower-level nano relay as the wiring cost.
And step two, inputting a nano relay sequence [ A, B, C, D, E ] required for completing electric power service calculation, determining the A-type nano relay with the minimum wiring cost from the electric power service data input port as a wiring starting nano relay, and determining the E-type nano relay with the minimum wiring cost from the electric power service data output port as a wiring terminal nano relay.
Step three, as shown in fig. 4, starting from the initial nano-relay, searching 3 subordinate nano-relays which have the minimum wiring cost from the superior nano-relay, marking the subordinate nano-relays as to-be-selected nano-relays, and if the number of the subordinate nano-relays of the same kind is less than 3, determining the number of the subordinate nano-relays as the standard; traversing and calculating the wiring cost from the superior nanometer relay to the inferior nanometer relay to form each wiring scheme and a wiring cost sequence thereof (a nanometer relay number sequence and a wiring cost sequence), such as { [ A, B1, C1, D1], [3,2, 3] }; the method comprises the information of the number of the nanometer relay and the information of the wiring cost.
And step four, summing the wiring cost sequences in sequence, calculating the wiring cost sequence with the minimum value by using a sorting method, selecting the corresponding nano relay number sequence, and if the nano relay number sequences with the same wiring cost sum exist, performing a scheme of secondarily selecting the wiring cost sequence with the minimum variance.
Inputting the serial number sequence of the nano relays into a switch array control unit, and sequentially controlling programmable wiring switches among the serial numbers of the nano relays through a switch control channel; the switch array control unit gates programmable wiring switches among the nanometer relay sequences through the switch control channel to form a complete power service hardware processing chain.
The invention also provides an optimized wiring system of the programmable wiring nano relay array, which is applied to the programmable wiring nano relay array and comprises the following components:
and the acquisition module is used for acquiring the power service and determining the sequence of the nano relay according to the power service.
The starting nano-relay and end nano-relay determining module is used for determining a starting nano-relay and an end nano-relay according to the nano-relay sequence and the wiring cost; the wiring penalty is the number of channel switches or the length of the wiring channels.
And the nanometer relay number sequence and wiring cost sequence determining module is used for traversing the wiring costs of the adjacent two levels of nanometer relays from the initial nanometer relay to the terminal nanometer relay to obtain a nanometer relay number sequence and a wiring cost sequence.
And the summation module is used for determining the sum of the wiring costs according to the wiring cost sequence.
And the sequencing module is used for selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum wiring cost sum as a wiring scheme by utilizing a sequencing method.
As an alternative embodiment, the routing optimization system for the programmable routing nanorelay array further comprises:
and the variance calculating module is used for calculating the variance of the wiring cost sequence according to the wiring cost sequence if a plurality of nano relay number sequences corresponding to the wiring cost sequence with the minimum wiring cost sum exist.
And the variance selection module is used for selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum variance as a wiring scheme.
The programmable combination of the nanometer relay is realized through the programmable channel switch, the gating switch, the matrix type wiring channel and the switch array control unit, and the use flexibility and the use efficiency of the nanometer relay circuit are improved.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (8)
1. A programmable wiring nano relay array is characterized by comprising a switch array control unit and a plurality of nano relay units connected in an array manner; the nano relay unit comprises a nano relay, a plurality of channel switches and a plurality of gating switches;
a plurality of the channel switches and a plurality of the gate switches form a rectangle; a plurality of the channel switches are all arranged at the vertex of the rectangle; one of the vertices corresponds to one of the channel switches; different vertexes correspond to different channel switches; each gating switch is arranged between two channel switches; each channel switch is connected with the adjacent gating switch; the nano relay is arranged in the rectangle; each gating switch is connected with the nano relay; the gating switch is arranged on the side of the rectangle;
the switch array control unit is connected with each channel switch; the switch array control unit is used for controlling the conduction state of the channel switch according to the power service; the channel switch is used for communicating any two gating switches connected with the channel switch; the rectangles between two adjacent nanometer relay units share two channel switches and one gating switch.
2. The programmable wiring nanorelay array of claim 1, further comprising wiring channels, each of the channel switches being connected to an adjacent of the gating switches through the wiring channels; each gating switch is connected with the nano relay through the wiring channel.
3. The programmable wired nanorelay array of claim 1, wherein the nanorelay comprises a combinational logic circuit and an input-output circuit connected to the combinational logic circuit; the input and output circuit is connected with the gating switch.
4. The programmable wired nanorelay array of claim 1, further comprising a selector; the selector is used for connecting the switch array control unit and the channel switch.
5. An optimized wiring method for a programmable wiring nano-relay array, which is applied to the programmable wiring nano-relay array of any one of claims 1 to 4, and comprises the following steps:
acquiring a power service and determining a nano relay sequence according to the power service;
determining a starting nano relay and an end point nano relay according to the nano relay sequence and the wiring cost; the wiring cost is the number of channel switches or the length of a wiring channel;
traversing the wiring cost of the adjacent two-stage nano relays from the starting nano relay to the end nano relay to obtain a nano relay number sequence and a wiring cost sequence;
determining a wiring cost sum according to the wiring cost sequence;
and selecting the nanometer relay number sequence corresponding to the wiring cost sequence with the minimum sum of the wiring costs as a wiring scheme by utilizing a sequencing method.
6. The method for optimizing routing of a programmable routing nanorelay array according to claim 5, wherein after the selecting, as the routing scheme, the nanorelay number sequence corresponding to the routing cost sequence with the lowest routing cost by using the sorting method, the method further comprises:
if a plurality of nanometer relay number sequences corresponding to the wiring cost sequence with the minimum wiring cost sum exist, calculating the variance of the wiring cost sequence according to the wiring cost sequence;
and selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum variance of the wiring cost sequence as a wiring scheme.
7. An optimized wiring system of a programmable wiring nano-relay array, which is applied to the programmable wiring nano-relay array of any one of claims 1 to 4, and comprises:
the acquisition module is used for acquiring power services and determining a nanometer relay sequence according to the power services;
the starting nano-relay and end nano-relay determining module is used for determining a starting nano-relay and an end nano-relay according to the nano-relay sequence and the wiring cost; the wiring cost is the number of channel switches or the length of wiring channels;
the nanometer relay number sequence and wiring cost sequence determining module is used for traversing the wiring cost of the adjacent two-stage nanometer relay from the starting nanometer relay to the end-point nanometer relay to obtain a nanometer relay number sequence and a wiring cost sequence;
the summing module is used for determining the sum of the wiring costs according to the wiring cost sequence;
and the sequencing module is used for selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum wiring cost sum as a wiring scheme by utilizing a sequencing method.
8. The optimized routing system for programmable routed nanorelay arrays according to claim 7, further comprising:
the variance calculation module is used for calculating the variance of the wiring cost sequence according to the wiring cost sequence if a plurality of nano relay number sequences corresponding to the wiring cost sequence with the minimum wiring cost sum exist;
and the variance selection module is used for selecting the nano relay number sequence corresponding to the wiring cost sequence with the minimum variance as a wiring scheme.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210952751.8A CN115021744B (en) | 2022-08-09 | 2022-08-09 | Programmable wiring nano relay array, and optimized wiring method and system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210952751.8A CN115021744B (en) | 2022-08-09 | 2022-08-09 | Programmable wiring nano relay array, and optimized wiring method and system |
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| Publication Number | Publication Date |
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| CN115021744A CN115021744A (en) | 2022-09-06 |
| CN115021744B true CN115021744B (en) | 2022-12-27 |
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| CN202210952751.8A Active CN115021744B (en) | 2022-08-09 | 2022-08-09 | Programmable wiring nano relay array, and optimized wiring method and system |
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| CN115021744A (en) | 2022-09-06 |
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