CN115021528A

CN115021528A - Control device and control method for bootstrap drive

Info

Publication number: CN115021528A
Application number: CN202210422538.6A
Authority: CN
Inventors: 杨锡旺; 付瑜
Original assignee: Changzhou Shiwei Electronics Co ltd
Current assignee: Changzhou Shiwei Electronics Co ltd
Priority date: 2022-04-21
Filing date: 2022-04-21
Publication date: 2022-09-06

Abstract

The application provides a control device and a control method of bootstrap drive, which comprise a full-bridge circuit and a bootstrap drive circuit; the full-bridge circuit comprises first to fourth MOS transistors and first to fourth diodes. The bootstrap driving circuit comprises a bootstrap driving module, a first bootstrap capacitor, a second bootstrap capacitor and a fifth diode. The bootstrap driving module is used for loading the voltages of the first bootstrap capacitor and the second bootstrap capacitor to the grid electrode of the second MOS transistor when the first MOS transistor is changed from on to off and the fourth MOS transistor is changed from on to off; the first MOS transistor is used for converting the first power supply voltage into a first bootstrap capacitor voltage and converting the second power supply voltage into a second bootstrap capacitor voltage; the bootstrap drive circuit respectively controls the third MOS transistor and the fourth MOS transistor to be continuously conducted in respective working half period to realize the sufficient charging of the bootstrap capacitor, so that the first MOS transistor and the second MOS transistor are smoothly conducted when the full-bridge circuit enters a light load mode.

Description

Control device and control method for bootstrap drive

Technical Field

The present application relates to the field of electronic power technologies, and in particular, to a bootstrap drive control device and a control method.

Background

An LLC boost circuit is a circuit structure commonly used in the art, as shown in fig. 1. The primary circuit of the LLC boost circuit can adopt a half-bridge structure or a full-bridge structure. For example, the MOS transistors PWM2A, PWM2B, PWM32A, and PWM3B shown in fig. 1 constitute a full bridge configuration.

For a MOS transistor to be conductive, its gate voltage must be greater than its threshold voltage (Vth). In the primary full bridge circuit of the LLC boost circuit shown in fig. 1, the gate voltage of the upper MOS transistors PWM2A and PWM3B, which are upper transistors, needs to be greater than the sum of the drain voltage and the threshold voltage thereof in order to turn on the transistors.

In order to meet the requirement of switching on the upper tube, the prior art adopts a bootstrap circuit mode to realize. FIG. 2 shows a typical bootstrap circuit of the prior art with a top-up tube enabled application. For convenience of illustration, a half-bridge configuration is shown in fig. 2, and a full-bridge configuration is similar. The driving module controls the successive turning on and off of the MOS transistors M1 and M2. In order to satisfy the conduction of M1, a bootstrap capacitor C needs to be applied. The VCC is loaded to the gate of M1 by the driving module in the process that M2 is changed from on to off. VCC is actually the drain voltage of M1, and as mentioned above, in order to turn on M1, the gate voltage of M1 is greater than the sum of its drain voltage and the threshold voltage (Vth), i.e., the gate voltage Vgm1 > VCC + Vth of M1. In fig. 2, when M1 is turned off and M2 is turned on, the drain and source of M2 are equivalent to a conducting line, and VDD passes through diode D, bootstrap capacitor C, M2 and ground to form a loop, i.e., VDD charges bootstrap capacitor C. When M1 needs to be changed from off to on, M2 is off, VCC is loaded to the grid electrode of M1 by the driving circuit, and since M2 is off, bootstrap capacitor C discharges, so that diode D is turned off in the reverse direction, the voltage discharged by bootstrap capacitor C is also loaded to the grid electrode of M1 by the driving circuit, and therefore the voltage loaded on the grid electrode of M1 is formed to be VCC + V _{Bootstrap capacitor} As long as V _{Bootstrap capacitor} Greater than the threshold voltage Vth, M1 can be made conductive.

Therefore, the voltage of the bootstrap capacitor C determines whether M1 can be turned on, and if the bootstrap capacitor C is not sufficiently charged, the turn-on of M1 may not be achieved. When the LLC primary circuit enters the light-load mode as shown in fig. 3, the gain characteristic must allow the LLC primary circuit to drive into the small duty cycle mode, i.e., drive for a period of time, and then stop for a period of time. For example, in fig. 3, the conduction time of M2 is the same as that of M1, the conduction time of M2 in one period is very short, and even there is a possibility that there is no drive for a long time, and the conduction time period of M2 will cause the time for VDD to charge the bootstrap capacitor C through the diode D to be very short, so that the charge capacity of the bootstrap capacitor C is insufficient, and the conduction cannot be performed due to the insufficient voltage applied to the gate when the upper tube M1 is turned on again.

Disclosure of Invention

In order to solve the problem that the charging capacity of the bootstrap capacitor is insufficient in the prior art, the application provides a control device and a control method of bootstrap drive. The present application provides a bootstrap-driven control device, comprising:

a full bridge circuit and a bootstrap drive circuit; the full-bridge circuit comprises a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4; the source electrode of the first MOS transistor Q1 is connected with the drain electrode of the third MOS transistor Q3 to serve as a first bridge arm A of the full bridge circuit, and the source electrode of the second MOS transistor Q2 is connected with the drain electrode of the fourth MOS transistor Q4 to serve as a second bridge arm B of the full bridge circuit; the first bridge arm A and the second bridge arm B are used for connecting a load; the drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2 are connected to the first power supply voltage VCC, and the drain of the third MOS transistor Q3 and the drain of the fourth MOS transistor Q4 are connected in parallel to ground; the full-bridge capacitor (C10) has its terminals connected between the first supply voltage VCC and ground.

The bootstrap driving circuit includes a bootstrap driving module 10, a first bootstrap capacitor C1, a second bootstrap capacitor C2, and a fifth diode D5. The first end of the first bootstrap capacitor C1, the first end of the second bootstrap capacitor C2, and the bootstrap driving module 10 are connected to each other and to the cathode of the fifth diode; the anode of the fifth diode D5 is connected to the first power supply voltage VCC; a second end of the first bootstrap capacitor C1 is connected to the source of the first MOS transistor Q1 and serves as a first leg a, and a second end of the second bootstrap capacitor C2 is connected to the source of the second MOS transistor Q2 and serves as a second leg B.

The bootstrap driving module 10 is configured to load the first power voltage VCC and the voltage V2 of the second bootstrap capacitor C2 to the gate of the second MOS transistor Q2 when the first MOS transistor Q1 is turned from on to off and the fourth MOS transistor Q4 is turned from on to off; the bootstrap driving module 10 is further configured to load the first power voltage VCC and the voltage V1 of the first bootstrap capacitor C1 to the gate of the first MOS transistor Q1 when the second MOS transistor Q2 is turned from on to off and the third MOS transistor Q3 is turned from on to off.

Optionally, the bootstrap driving module 10 includes a first driving transistor T1, a second driving transistor T2, a third driving transistor T3, a fourth driving transistor T4 and a resistor R. Wherein, the gates of the first driving transistor T1, the second driving transistor T2, the third driving transistor T3 and the fourth driving transistor T4 are respectively connected to the first driving signal IN1, the second driving signal IN2, the third driving signal IN3 and the fourth driving signal IN 4; the drain and source of the first driving transistor T1 are connected to the first power voltage VCC and ground, respectively, and the gate of the first MOS transistor Q1 is connected to the source of the first driving transistor T1; the drain and the source of the second driving transistor T2 are respectively connected to the first power supply voltage VCC and ground, and the gate of the second MOS transistor Q2 is connected to the source of the second driving transistor T2; the drain and the source of the third driving transistor T3 are respectively connected to the first power supply voltage VCC and ground, and the gate of the third MOS transistor Q3 is connected to the source of the third driving transistor T3; the drain and the source of the fourth driving transistor T4 are respectively connected to the first power voltage VCC and the ground, and the gate of the fourth MOS transistor Q4 is connected to the source of the fourth driving transistor T4; a first terminal of the resistor R is connected to the first terminal of the first bootstrap capacitor C1 and the first terminal of the second bootstrap capacitor C2, and a second terminal of the resistor R is connected to the drain of the first driving transistor T1 and the drain of the second driving transistor T2.

The present application also provides a control method of a bootstrap-driven control device, including the steps of:

the method comprises the following steps: in the first half of a complete working cycle of the full-bridge circuit, the bootstrap drive circuit sets the second MOS transistor Q2 and the third MOS transistor Q3 to an off state; in a period from a first time point to a second time point, which is a start time point in the upper half cycle, the bootstrap drive circuit sets the first MOS transistor Q1 to a conductive state, and in the entire upper half cycle, the bootstrap drive circuit sets the fourth MOS transistor Q4 to a conductive state.

Step two: in the next half cycle of one complete duty cycle of the full-bridge circuit, the bootstrap drive circuit sets the first MOS transistor Q1 and the fourth MOS transistor Q4 to the off state; the bootstrap drive circuit sets the second MOS transistor Q2 to the conductive state during a period from a third time point to a fourth time point, which is a start time point, in the next half-cycle, and sets the third MOS transistor Q3 to the conductive state throughout the next half-cycle.

Preferably, IN the first half cycle of one full duty cycle of the full bridge circuit, the second driving signal IN2 and the third driving signal IN3 IN the bootstrap driving circuit are set to a low level, so that the second MOS transistor Q2 and the third MOS transistor Q3 are turned off; setting the first driving signal IN1 to a high level during a period from a first time point to a second time point, which is a start time point, IN the upper half cycle; throughout this upper half period, the fourth drive signal IN4 is set to a high level.

Preferably, IN the next half cycle of one full duty cycle of the full bridge circuit, the first driving signal IN1 and the fourth driving signal IN4 IN the bootstrap driving circuit are set to a low level, so that the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned off; setting the second driving signal IN2 to a high level during a period from a third time point to a fourth time point, which is a start time point, IN the next half period; throughout this half-down period, the third drive signal IN3 is set to a high level.

Drawings

Fig. 1 is a circuit schematic of an LLC boost circuit.

Fig. 2 is a schematic diagram of a conventional bootstrap driving circuit.

Fig. 3 is a timing diagram of a conventional bootstrap driving circuit.

Fig. 4 is a circuit diagram of a control device for bootstrap driving of the present invention.

Fig. 5 is a schematic circuit diagram of a preferred control device for bootstrap driving according to the present invention.

Fig. 6 is a timing chart of the control device of bootstrap driving of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of implementation in many different ways than those herein set forth and of similar import by those skilled in the art without departing from the spirit of this application and is therefore not limited to the specific implementations disclosed below.

The present invention provides a bootstrap driving control device, referring to fig. 4, including: a full bridge circuit and a bootstrap drive circuit; the full-bridge circuit comprises a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4; the source of the first MOS transistor Q1 is connected with the drain of the third MOS transistor Q3 to form a first bridge arm A of the full bridge circuit, and the source of the second MOS transistor Q2 is connected with the drain of the fourth MOS transistor Q4 to form a second bridge arm B of the full bridge circuit; the first bridge arm A and the second bridge arm B are used for connecting a load; the drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2 are connected to the first power supply voltage VCC, and the drain of the third MOS transistor Q3 and the drain of the fourth MOS transistor Q4 are connected in parallel to ground; the full-bridge capacitor (C10) has its terminals connected between the first supply voltage VCC and ground.

The bootstrap driving circuit includes a bootstrap driving module 10, a first bootstrap capacitor C1, a second bootstrap capacitor C2, and a fifth diode D5. The first end of the first bootstrap capacitor C1, the first end of the second bootstrap capacitor C2, and the bootstrap driving module 10 are connected to each other and to the cathode of the fifth diode; the anode of the fifth diode D5 is connected to the second power supply voltage VDD; a second end of the first bootstrap capacitor C1 is connected to the source of the first MOS transistor Q1 and serves as a first leg a, and a second end of the second bootstrap capacitor C2 is connected to the source of the second MOS transistor Q2 and serves as a second leg B.

The bootstrap driving module 10 is configured to load the first power voltage VCC and the voltage V2 of the second bootstrap capacitor C2 to the gate of the second MOS transistor Q2 when the first MOS transistor Q1 is turned from on to off and the fourth MOS transistor Q4 is turned from on to off; the bootstrap driving module 10 is further configured to load the first power voltage VCC and the voltage V1 of the first bootstrap capacitor C1 to the gate of the first MOS transistor Q1 when the second MOS transistor Q2 is changed from on to off and the third MOS transistor Q3 is changed from on to off.

Alternatively, referring to fig. 5, the bootstrap driving module 10 includes a first driving transistor T1, a second driving transistor T2, a third driving transistor T3, a fourth driving transistor T4, and a resistor R. Wherein, the gates of the first driving transistor T1, the second driving transistor T2, the third driving transistor T3 and the fourth driving transistor T4 are respectively connected to the first driving signal IN1, the second driving signal IN2, the third driving signal IN3 and the fourth driving signal IN 4; the drain and source of the first driving transistor T1 are connected to the first power voltage VCC and ground, respectively, and the gate of the first MOS transistor Q1 is connected to the source of the first driving transistor T1; the drain and the source of the second driving transistor T2 are respectively connected to the first power supply voltage VCC and ground, and the gate of the second MOS transistor Q2 is connected to the source of the second driving transistor T2; the drain and the source of the third driving transistor T3 are respectively connected to the first power voltage VCC and the ground, and the gate of the third MOS transistor Q3 is connected to the source of the third driving transistor T3; the drain and the source of the fourth driving transistor T4 are respectively connected to the first power voltage VCC and the ground, and the gate of the fourth MOS transistor Q4 is connected to the source of the fourth driving transistor T4; a first terminal of the resistor R is connected to the first terminal of the first bootstrap capacitor C1 and the first terminal of the second bootstrap capacitor C2, and a second terminal of the resistor R is connected to the drain of the first driving transistor T1 and the drain of the second driving transistor T2.

The present application also provides a control method of a bootstrap-driven control device, see fig. 4 and 6, including the following steps:

the method comprises the following steps: in the first half period t1 to t3 of one full duty cycle t1 to t5 of the full bridge circuit, the bootstrap drive circuit sets the second MOS transistor Q2 and the third MOS transistor Q3 to the off state; in a period from a first time point t1 to a second time point t2 as a starting time point in the upper half cycle, the bootstrap driving circuit sets the first MOS transistor Q1 to a conducting state, and in the entire upper half cycle t1 to t3, the bootstrap driving circuit sets the fourth MOS transistor Q4 to a conducting state; as can be seen from fig. 6, in the time period from t1 to t2 of the last half cycle, the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned on, the second power supply voltage VDD forms a loop with the ground through the fifth diode D5, the second bootstrap capacitor C2, the second bridge arm B, and the fourth MOS transistor Q4, and the second bootstrap capacitor C2 is charged by the second power supply voltage VDD; during the time period from t2 to t3 of the last half cycle, the first MOS transistor Q1 is turned off, the fourth MOS transistor Q4 is still turned on, and the second bootstrap capacitor C2 continues to be charged by the second power supply voltage VDD.

Step two: in the next half cycle t3 to t5 of one full duty cycle of the full bridge circuit, the bootstrap drive circuit sets the first MOS transistor Q1 and the fourth MOS transistor Q4 to an off state; the bootstrap drive circuit sets the second MOS transistor Q2 to a conductive state during a period from a third time point t3 to a fourth time point t4 as a start time point in the next half-cycle, and sets the third MOS transistor Q3 to a conductive state throughout the next half-cycle t3 to t 5. Referring to fig. 6, when the next half-cycle arrives, that is, at time t3, the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned off, the second bootstrap capacitor C2 loads the second voltage V2 to the gate of the second MOS transistor Q2 through the bootstrap driving module 10, and at the same time, the fifth diode D5 is turned off in the reverse direction, the second power voltage VDD is disconnected from the bootstrap driving module 10, and the bootstrap driving module 10 also loads the first power voltage VCC to the gate of the second MOS transistor Q2. At this time, the voltage VgQ2 applied to the gate of the second MOS transistor Q2 is the sum of the first power supply voltage VCC (also the drain voltage VdQ2 of the second MOS transistor Q2) and the voltage V2 of the second bootstrap capacitor C2, that is, VgQ1 is VCC + V2; as long as the charging time of the second bootstrap capacitor C2 is long enough to make V2 > VthQ2, VCC + V2 > VdQ2+ VthQ2 can be achieved, so that the turned-off second MOS transistor Q2 is turned on.

With reference to fig. 6, in a time period from t3 to t4 of the next half cycle, the second MOS transistor Q2 and the third MOS transistor Q3 are turned on, the second power supply voltage VDD forms a loop with the ground through the fifth diode D5, the first bootstrap capacitor C1, the first bridge arm a, and the third MOS transistor Q3, and the second power supply voltage VDD charges the first bootstrap capacitor C1; in a time period from t4 to t5 of the next half cycle, the second MOS transistor Q2 is turned off, the third MOS transistor Q3 is still turned on, and the second power supply voltage VDD continues to charge the first bootstrap capacitor C1;

when the next complete cycle arrives, that is, at time t5, the second MOS transistor Q2 and the third MOS transistor Q3 are turned off, the first bootstrap capacitor C1 loads the first voltage V1 to the gate of the first MOS transistor Q1 through the bootstrap driving module 10, meanwhile, the fifth diode D5 is turned off in the reverse direction, the second power voltage VDD is disconnected from the bootstrap driving module 10, and the bootstrap driving module 10 also loads the first power voltage VCC to the gate of the first MOS transistor Q1, similar to the foregoing, the common loading of the first voltage V1 and the first power voltage VCC makes the gate voltage of the first MOS transistor Q1 greater than the sum of the drain voltage and the threshold voltage thereof, so as to make the turned-off first MOS transistor Q1 turned on again.

As a preferred embodiment of the present invention, referring to fig. 5 and 6, IN the first half period t1 to t3 of one complete duty cycle of the full-bridge circuit, the second driving signal IN2 and the third driving signal IN3 IN the bootstrap driving circuit are set to a low level, thereby turning off the second MOS transistor Q2 and the third MOS transistor Q3; setting the first driving signal IN1 to a high level during a period from a first time point t1 to a second time point t2 as a start time point IN the upper half cycle; throughout the upper half period t1 to t3, the fourth drive signal IN4 is set to a high level. Specifically, referring to fig. 5 and 6, at time T1, the first driving signal IN1 and the fourth driving signal IN4 are at a high level, at which the first driving transistor T1 and the fourth driving transistor T4 are turned on, and the voltages loaded on the gate of the first MOS transistor Q1 and the gate of the fourth MOS transistor Q4 are the sum of the first power supply voltage VCC, the voltage of the first bootstrap capacitor C1, and the voltage of the second bootstrap capacitor C2, and the sum of the voltages triggers the first MOS transistor Q1 and the fourth MOS transistor Q4 to be turned on; during the time t2-t3, the first driving signal IN1 is turned off at a low level, so that the voltage of the gate of the first MOS transistor Q1 drops to 0, and the first MOS transistor Q1 turns from on to off; the fourth driving signal IN4 is still at a high level, so that the fourth driving transistor T4 is maintained to be turned on, the fourth MOS transistor Q4 is further maintained to be turned on, the second power voltage VDD forms a loop through the fifth diode D5, the second bootstrap capacitor C2, the second bridge arm B, the fourth MOS transistor Q4, and ground, and the second bootstrap capacitor C2 is charged by the second power voltage VDD.

IN the next half period t3 to t5 of one full duty cycle of the full bridge circuit, the first drive signal IN1 and the fourth drive signal IN4 IN the bootstrap drive circuit are set to a low level, thereby turning off the first MOS transistor Q1 and the fourth MOS transistor Q4; setting the second driving signal IN2 to a high level during a period from a third time point t3 to a fourth time point t4 as a start time point IN the lower half period; the third drive signal IN3 is set to the high level throughout the half-down period t3 to t 5. Specifically, at time t3, the fourth driving signal IN4 is turned off from high level to low level, so that the gate voltage of the fourth MOS transistor Q4 becomes 0 and is turned off, and the second bootstrap capacitor C2 stops charging; at this time, the second and third driving signals IN2 and IN3 change from low level to high level, and the second and third driving transistors T2 and T3 are turned on; the voltage of the second bootstrap capacitor C2 is applied to the gate of the second MOS transistor Q2, and at the same time, the first power supply voltage VCC and the second power supply voltage VDD are also applied to the gate of the second MOS transistor Q2, and the voltage applied to the gate of the second MOS transistor Q2 is superimposed to trigger the second MOS transistor Q2 to turn on; similarly, the third MOS transistor Q3 is also turned on; in the time period from t3 to t4, on one hand, the full bridge circuit normally works due to the conduction of the second MOS transistor Q2 and the third MOS transistor Q3 which are diagonally arranged, and on the other hand, the conduction of the third MOS transistor Q3 enables the second power supply voltage VDD to form a loop through the fifth diode D5, the first bootstrap capacitor C1, the first bridge arm a, the third MOS transistor Q3 and the ground, so that the first bootstrap capacitor C1 is charged; IN the time period from T4 to T5, the second driving signal IN2 is low, so that the second driving transistor T2 is turned off, and further the second MOS transistor Q2 is turned off, but since the third driving signal IN3 is still high, the third MOS transistor Q3 remains IN a conducting state, so that the first bootstrap capacitor C1 continues to be charged; thus, at time t5, the first MOS transistor Q1 and the fourth MOS transistor Q4 are turned on and enter the next duty cycle, similarly to the above.

Therefore, the bootstrap drive circuit is applied, so that when the full-bridge circuit enters a light load mode, the problem that the upper tube cannot be conducted due to insufficient capacitance of the bootstrap drive circuit is solved through continuous conduction of the lower tube.

While the foregoing is directed to the embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A bootstrap-drive control apparatus, comprising: a full bridge circuit and a bootstrap drive circuit;

the full-bridge circuit comprises a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first diode D1, a second diode D2, a third diode D3 and a fourth diode D4; the source electrode of the first MOS transistor Q1 is connected with the drain electrode of the third MOS transistor Q3 to serve as a first bridge arm A of the full bridge circuit, and the source electrode of the second MOS transistor Q2 is connected with the drain electrode of the fourth MOS transistor Q4 to serve as a second bridge arm B of the full bridge circuit; the first bridge arm A and the second bridge arm B are used for connecting a load; the drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2 are connected to the first power supply voltage VCC, and the drain of the third MOS transistor Q3 and the drain of the fourth MOS transistor Q4 are connected in parallel to ground; both ends of the full-bridge capacitor (C10) are connected between a first power supply voltage VCC and the ground;

2. The bootstrap-driven control device of claim 1,

3. The bootstrap-driven control device of claim 2,

the bootstrap driving module 10 includes a first driving transistor T1, a second driving transistor T2, a third driving transistor T3, a fourth driving transistor T4, and a resistor R; wherein, the gates of the first driving transistor T1, the second driving transistor T2, the third driving transistor T3 and the fourth driving transistor T4 are respectively connected to the first driving signal IN1, the second driving signal IN2, the third driving signal IN3 and the fourth driving signal IN 4; the drain and source of the first driving transistor T1 are connected to the first power voltage VCC and ground, respectively, and the gate of the first MOS transistor Q1 is connected to the source of the first driving transistor T1; the drain and source of the second driving transistor T2 are connected to the first power voltage VCC and ground, respectively, and the gate of the second MOS transistor Q2 is connected to the source of the second driving transistor T2; the drain and the source of the third driving transistor T3 are respectively connected to the first power voltage VCC and the ground, and the gate of the third MOS transistor Q3 is connected to the source of the third driving transistor T3; the drain and the source of the fourth driving transistor T4 are respectively connected to the first power voltage VCC and the ground, and the gate of the fourth MOS transistor Q4 is connected to the source of the fourth driving transistor T4; a first terminal of the resistor R is connected to the first terminal of the first bootstrap capacitor C1 and the first terminal of the second bootstrap capacitor C2, and a second terminal of the resistor R is connected to the drain of the first driving transistor T1 and the drain of the second driving transistor T2.

4. A control method of a bootstrap-driven control device, characterized by comprising the bootstrap-driven control device as claimed in any one of claims 1 to 3, said control method comprising the steps of:

the method comprises the following steps: in the first half of a complete working cycle of the full-bridge circuit, the bootstrap drive circuit sets the second MOS transistor Q2 and the third MOS transistor Q3 to an off state; in a period from a first time point to a second time point, which is a starting time point in the upper half cycle, the bootstrap drive circuit sets the first MOS transistor Q1 to be in a conducting state, and in the entire upper half cycle, the bootstrap drive circuit sets the fourth MOS transistor Q4 to be in a conducting state;

step two: in the next half cycle of one complete duty cycle of the full-bridge circuit, the bootstrap drive circuit sets the first MOS transistor Q1 and the fourth MOS transistor Q4 to the off state; the bootstrap drive circuit sets the second MOS transistor Q2 to the conductive state during a period from a third time point to a fourth time point as a start time point in the next half cycle, and sets the third MOS transistor Q3 to the conductive state throughout the next half cycle.

5. The control method of the bootstrap driving control device according to claim 4, characterized IN that IN the upper half period of one complete duty cycle of the full bridge circuit, the second driving signal IN2 and the third driving signal IN3 IN the bootstrap driving circuit are set to low level, so as to turn off the second MOS transistor Q2 and the third MOS transistor Q3; setting the first driving signal IN1 to a high level during a period from a first time point to a second time point, which is a start time point, IN the upper half cycle; throughout this upper half period, the fourth drive signal IN4 is set to a high level.

6. The control method of the bootstrap driving control device according to claim 4, characterized IN that IN the next half period of one complete duty cycle of the full-bridge circuit, the first driving signal IN1 and the fourth driving signal IN4 IN the bootstrap driving circuit are set to low level, so as to turn off the first MOS transistor Q1 and the fourth MOS transistor Q4; setting the second driving signal IN2 to a high level during a period from a third time point to a fourth time point, which is a start time point, IN the next half period; throughout this half-down period, the third drive signal IN3 is set to a high level.