CN115020351A

CN115020351A - Method for forming semiconductor device

Info

Publication number: CN115020351A
Application number: CN202210803755.XA
Authority: CN
Inventors: 黄娟娟; 白卫平; 肖德元; 郁梦康
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-07-07
Filing date: 2022-07-07
Publication date: 2022-09-06

Abstract

The embodiment of the disclosure discloses a method for forming a semiconductor device, which comprises the following steps: providing a substrate, and forming a stacked structure on the substrate, wherein the substrate comprises a first area for forming a transistor and a second area for forming a capacitor, and the stacked structure comprises a supporting layer and a dielectric layer which are alternately stacked; forming an isolation layer in a direction vertical to the substrate, wherein the isolation layer penetrates through each dielectric layer and divides each dielectric layer into a first part and a second part, the first part is positioned in the first area, and the second part is positioned in the second area; removing the second part of the dielectric layer to form a gap, wherein the gap exposes the first surface of the supporting layer and the second surface of the isolation layer in the direction vertical to the substrate; forming a first film covering the first surface and a second film covering the second surface; and providing plasma and applying an electric field to remove the second film after the plasma reacts with the second film on the second surface, wherein the direction of electric field lines of the electric field is parallel to the first surface and points to the second surface.

Description

Method for forming semiconductor device

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device.

Background

Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in computers. The memory cell includes a transistor and a capacitor. The electrical property of the capacitor has an important influence on the storage performance of the storage unit, so that the improvement of the electrical property of the capacitor is an important way for improving the performance of the storage unit, but the film deposition method in the capacitor has the problems of complex manufacturing process and high cost.

Disclosure of Invention

According to a first aspect of the embodiments of the present disclosure, there is provided a method of forming a semiconductor device, the method including:

providing a substrate, and forming a stacked structure on the substrate; the substrate comprises a first area for forming a transistor and a second area for forming a capacitor, and the stacked structure comprises a support layer and a dielectric layer which are alternately stacked;

forming an isolation layer in a direction perpendicular to the substrate; the isolation layer penetrates through each dielectric layer and divides each dielectric layer into a first part and a second part, the first part is located in the first area, and the second part is located in the second area;

removing the second portion of the dielectric layer to form a gap; wherein the gap reveals a first surface of the support layer and a second surface of the release layer in a direction perpendicular to the substrate;

forming a first film covering the first surface and a second film covering the second surface;

providing plasma and applying an electric field to remove a second film on the second surface after the plasma reacts with the second film; wherein the direction of the electric field lines of the electric field is parallel to the first surface and directed towards the second surface.

In some embodiments, the forming a first film covering the first surface and a second film covering the second surface comprises:

providing a precursor; wherein at least a portion of the precursor adsorbs to the first surface and the second surface;

and providing the plasma so that the precursor of the first surface reacts with the plasma to form the first thin film, and the precursor of the second surface reacts with the plasma to form the second thin film.

and forming a first film and a second film on the first surface and the second surface by utilizing an atomic layer deposition process.

In some embodiments, the plasma includes oxygen radicals.

In some embodiments, the providing a plasma and applying an electric field to remove a second film of the second surface after reacting the plasma with the second film comprises:

the plasma reacts with the second thin film of the second surface to generate a gaseous compound.

In some embodiments, the gaseous compound comprises ruthenium tetroxide.

In some embodiments, after the providing the plasma and the applying the electric field to react the plasma with the second film of the second surface and to remove the second film, the method further comprises:

removing the gaseous compound generated by the reaction of the plasma and the second thin film.

In some embodiments, before the providing the plasma to react the precursor of the first surface with the plasma to form the first thin film and the precursor of the second surface with the plasma to form the second thin film, the method further comprises:

removing the precursor that is not adsorbed by the first surface and the second surface.

In some embodiments, the precursor comprises an organic coordination compound of ruthenium.

In some embodiments, the organic coordination compound of ruthenium comprises bis-ethylcyclopentadienyl-ruthenium.

In some embodiments, the constituent materials of the first and second thin films include ruthenium dioxide.

In some embodiments, after the providing the plasma and applying the electric field to react the plasma with the second thin film of the second surface and removing the second thin film, the method further comprises:

forming an interpolar dielectric layer in the gap covering the first thin film and the second surface;

and forming an electrode layer covering the interelectrode dielectric layer.

In some embodiments, the semiconductor device includes a capacitor including the first thin film, the interpoly dielectric layer, and the electrode layer; wherein the first film is electrically conductive.

In some embodiments, the forming method further comprises:

forming a transistor coupled to the capacitor in the first region; wherein a source of the transistor is in contact with the first thin film.

In some embodiments, the forming a transistor coupled to the capacitor in the first region includes:

forming a channel; wherein the support layer of the first region is used to form the channel;

forming a gate surrounding the channel;

the source and the drain of the transistor are formed at both ends in the extending direction of the channel, respectively.

In the embodiment of the disclosure, after the first film covering the first surface and the second film covering the second surface are formed, by providing the plasma and applying the electric field, the direction of the electric field line of the electric field is parallel to the first surface and is directed to the second surface, therefore, the plasma moves and gathers towards the second surface, and the second film is removed after the plasma reacts with the second film of the second surface, thereby exposing the second surface. The embodiment of the disclosure provides a directional selectivity deposition method, which can remove a second film on a second surface without etching by providing plasma and applying an electric field, so as to form a film on a first surface of a support layer, and the process of not forming a film on a second surface of an isolation layer in a direction perpendicular to a substrate does not need etching, so that the flatness of a first film formed on the first surface can be improved without etching, and the good performance of a memory device is ensured. Furthermore, the second surface of the isolation layer can be exposed while the first film is formed without a complex process of alternating deposition and etching, so that the process can be simplified and the cost can be reduced.

Drawings

FIG. 1 is a schematic diagram illustrating a perspective structure of a memory according to an exemplary embodiment;

fig. 2 is a cross-sectional view of a semiconductor device according to an exemplary embodiment;

FIG. 3 is a cross-sectional view of another semiconductor device shown in accordance with an exemplary embodiment;

fig. 4 is a flow chart illustrating a method of forming a semiconductor device according to an embodiment of the present disclosure;

FIG. 5 is a cross-sectional view of a semiconductor device shown in accordance with an embodiment of the present disclosure;

fig. 6 is a second area cross-sectional view of a semiconductor device shown in accordance with an embodiment of the present disclosure;

FIG. 7 is another cross-sectional view of a semiconductor device shown in accordance with an embodiment of the present disclosure;

FIG. 8 is a first schematic illustration of a surface reaction of a semiconductor device in accordance with an embodiment of the present disclosure;

fig. 9 is a second schematic diagram illustrating a surface reaction of a semiconductor device in accordance with an embodiment of the present disclosure.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is to be understood that the meaning of "on … …," "over … …," and "over … …" of the present disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

In the embodiments of the present disclosure, the terms "first," "second," "third," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers.

The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.

As the size of Dynamic Random Access Memory (DRAM) is continuously reduced, the structure of the Memory array of the DRAM is also developed from a buried Gate structure to a Gate All Around (GAA) structure with a smaller occupied area. However, as the feature size is continuously reduced, the electrode plate of the capacitor in the dram may be deformed, resulting in a reduction in the performance of the capacitor. Therefore, in order to reduce the size and keep the capacitance performance as low as possible, the dram is developed from a two-dimensional (2D) structure to a three-dimensional (3D) structure, and the 3D structure can fully utilize the space in the vertical direction, thereby greatly saving the wafer area and reducing the cost.

Referring to fig. 1, fig. 1 illustrates a superlattice (superlattice) structure of a 3D dram according to an exemplary embodiment, where the 3D dram includes a transistor surrounded by a ring-shaped gate structure, a step-shaped bit line (BL shown in fig. 1) contacting a drain of the transistor, and a capacitor (capacitor C shown in fig. 1) contacting a source of the transistor. Illustratively, the capacitor C comprises a lower electrode, an interelectrode dielectric layer and an upper electrode, wherein the lower electrode may be made of ruthenium (Ru) or ruthenium oxide (RuO) ₂ )。

In one implementation of forming the capacitor C, referring to fig. 2, after depositing the ruthenium oxide film 201 by using an atomic layer deposition process, the ruthenium oxide film 201 on the sidewall 20 and the plane 20' may be cut off by etching to form the lower electrode 202.

In another implementation of forming the capacitor C, referring to fig. 3, a ruthenium oxide film 301 is deposited by a selective atomic layer deposition process, as shown in fig. 3, the ruthenium oxide film 301 is deposited on the silicon pillar 303 and the silicon nitride layer 304, and then the ruthenium oxide film 301 on the silicon nitride layer 304 is removed by etching, so as to obtain a ruthenium oxide film 302, such that the ruthenium oxide film 302 is deposited only on the silicon pillar 303. The selective atomic layer deposition process utilizes the influence difference of the silicon column 303 on the deposition rate, and adopts an alternate deposition and etching mode to keep the ruthenium oxide film 301 on the silicon column 303 with a high deposition rate, so as to achieve the effect of selective growth.

In view of the above, the embodiments of the present disclosure also provide a method for forming a semiconductor device.

Fig. 4 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present disclosure, and the method for forming a semiconductor device according to the embodiment of the present disclosure includes, as shown in fig. 4:

s10: providing a substrate, and forming a stacked structure on the substrate; the substrate comprises a first area for forming a transistor and a second area for forming a capacitor, and the stacked structure comprises a supporting layer and a dielectric layer which are alternately stacked;

s20: forming an isolation layer in a direction perpendicular to the substrate; the isolation layer penetrates through each dielectric layer and divides each dielectric layer into a first part and a second part, the first part is located in the first area, and the second part is located in the second area;

s30: removing the second part of the dielectric layer to form a gap; the gap exposes the first surface of the support layer and the second surface of the isolation layer in the direction vertical to the substrate;

s40: forming a first film covering the first surface and a second film covering the second surface;

s50: providing plasma and applying an electric field to remove the second film after the plasma reacts with the second film on the second surface; wherein, the direction of the electric field lines of the electric field is parallel to the first surface and points to the second surface.

Referring to fig. 4 and 5, performing step S10, the substrate 50 may be made of a semiconductor material, such as one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound. The substrate 50 includes a first region a1 and a second region a2, and here, the first region a1 is illustrated as being used to form a transistor and the second region a2 is illustrated as being used to form a capacitor.

Referring to fig. 5, a stack structure is formed on a substrate 50; the stacked structure includes a support layer 501 and a dielectric layer 502 stacked alternately. Illustratively, the material of the dielectric layer 502 may include silicon oxide or silicon germanium (SiGe), and the like, and the material of the support layer 501 may include silicon (Si), germanium (Ge), and the like. The supporting layer 501 may be doped with a certain amount of impurity ions as required, and the impurity ions may be N-type impurity ions or P-type impurity ions.

The dielectric layer 502 and the support layer 501 may be alternately deposited on the substrate 50 in sequence by an epitaxial growth process. Dielectric layer 502 and support layer 501 may also be alternately deposited on substrate 50 in sequence by one or more deposition processes including, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or any combination thereof.

Referring to fig. 4 and 5, step S20 is performed, and in practical applications, an etching hole may be formed in the stacked structure by an etching process, and the etching hole is filled with an insulating material to form the isolation layer 503. Illustratively, the insulating material comprises silicon nitride.

In practical applications, the isolation layer 503 may serve to isolate the first region a1 from the second region a2, and may also serve as a support for the capacitor located in the second region a 2.

It should be noted that, referring to fig. 5, the first region a1 further includes an isolation structure 504, and illustratively, a constituent material of the isolation structure 504 includes silicon nitride, and the isolation structure 504 is used to protect a transistor. Other isolation structures may be disposed in the first area a1 according to practical situations, and the present embodiment is not limited thereto.

Referring to fig. 4 and 5, in step S30, the second portion of the dielectric layer 502 in the second region a2 may be removed by etching to form the gap 505. In practice, the gap 505 may be formed by dry etching, such as ion milling, plasma etching, reactive ion etching, laser ablation, or the like. A second portion of dielectric layer 502 in second region a2 may also be removed by a wet etch process, wherein an etchant from the wet etch process etches the second portion of dielectric layer 502 in second region a2 to form gap 505.

Referring to fig. 4 and 5, step S40 is performed to form a first film 506 covering the first surface and a second film covering the second surface after the gap 505 is formed. The first and second

thin films

506 and 506 may be deposited on the first and second surfaces by one or more deposition processes including, but not limited to, a radical enhanced atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or any combination thereof.

It should be noted that after etching the second portion of the dielectric layer 502 located in the second region a2 to form the gap 505, the first surface and the second surface may be exposed simultaneously, and thus, the first thin film 506 and the second thin film may be deposited on the first surface and the second surface simultaneously.

In practical applications, the first thin film and the second thin film are made of the same material, and the material of the first thin film and the second thin film may be a metal material or a semiconductor conductive material, such as copper, cobalt, tungsten, molybdenum, doped silicon, polysilicon, or any combination thereof. The metal includes, but is not limited to, ruthenium (Ru), tungsten (W), cobalt (Co), rhodium (Rh), iridium (Ir), molybdenum (Mo), and the constituent materials of the first and second films may further include metal oxides, such as ruthenium oxide (RuO) ₂ )。

Referring to fig. 4, step S50 is performed, and plasma may be generated by a steady state Direct Current (DC) or Radio Frequency (RF) plasma generator. In one example, the plasma (e.g., oxygen radicals) may be obtained by exciting an oxygen-containing gas, which may include a gas containing oxygen molecules. In another example, at least one of oxygen ions, oxygen radicals, oxygen molecular ions, oxygen molecular radicals, and ozone may be generated by exciting oxygen molecules.

In practical applications, an electric field is applied, the direction of the electric field lines of the electric field is parallel to the first surface and directed to the second surface, so that plasma (such as oxygen radicals) moves towards the second surface along the direction of the electric field lines, and the oxygen radicals react with the second film on the second surface to remove the second film.

Illustratively, the constituent material of the first film and the second film includes ruthenium oxide, and oxygen radicals move along the direction of the electric field lines according to the chemical reaction formula (RuO) ₂ )ads+2O ^* →RuO ₄ (g) It can be seen that the second thin film RuO of the second surface ₂ Reaction with oxygen radicals to gaseous RuO ₄ I.e. second film RuO with second surface removed ₂ Wherein (RuO) ₂ ) ads denotes second film RuO ₂ Adsorbed on a second surface, O ^* Is expressed as oxygen radical, RuO ₄ (g) Denotes gaseous RuO ₄ . Chemical reaction formula (RuO) ₂ )ads+2O ^* →RuO ₄ (g) It can be carried out, for example, in an environment having a reaction temperature of 30 ℃ to 300 ℃, for example, 50 ℃, 100 ℃, 250 ℃, 260 ℃, 280 ℃.

In the embodiment of the disclosure, after forming the first thin film covering the first surface and the second thin film covering the second surface, by providing plasma and applying an electric field, the direction of the electric field line of the electric field is parallel to the first surface and is directed to the second surface, the oxygen radical applies kinetic energy to promote the growth of the thin film in one direction while inhibiting the growth in the other direction, and has no dependence on the substrate on which the thin film is grown, so that the plasma moves and gathers towards the second surface, and the plasma reacts with the second thin film on the second surface to remove the second thin film, thereby exposing the second surface. In the embodiment of the disclosure, a method for forming a thin film is provided, which has directional selectivity, and can remove a second thin film on a second surface without etching by providing plasma and applying an electric field, so that the thin film is formed on a first surface of a support layer, and etching is not needed in a process that the thin film is not formed on a second surface of an isolation layer in a direction perpendicular to a substrate, so that damage to the thin film on the first surface can be reduced, flatness of a first thin film formed on the first surface can be improved, and a memory device can have good performance. Furthermore, the second surface of the isolation layer can be exposed while the first film is formed without a complex process of alternating deposition and etching, so that the process can be simplified and the cost can be reduced.

In one embodiment, step S40 includes:

and providing plasma to enable the precursor on the first surface to react with the plasma to form a first thin film, and enabling the precursor on the second surface to react with the plasma to form a second thin film.

In practical applications, the first and second films may be formed by a radical enhanced atomic layer deposition (real) process, which deposits the first and second films by sequentially exposing the first and second surfaces to a precursor and a plasma. Specifically, the description is made with the constituent materials of the first thin film and the second thin film including ruthenium oxide.

For example, according to the chemical reaction formula (Ru (EtCp)2) ads + O ^* →(Ru)ads+CO ₂ (g)+H ₂ O(g)，(Ru)ads+2O ^* →(RuO ₂ ) ads indicates that the precursor gas is provided by the radical enhanced atomic layer deposition process and adsorbed to the first surface and the second surface. The precursor comprises an organic coordination compound of ruthenium, such as bis-ethylcyclopentadienyl-ruthenium. Providing a plasma O ^* Reacting with bis-ethylcyclopentadienyl-ruthenium (Ru (EtCp)2) to obtain ruthenium oxide film, wherein (Ru (EtCp)2) ads shows that precursor Ru (EtCp)2 is adsorbed on the first surface and the second surface, and O ^* Represents an oxygen radical, (RuO) ₂ ) ads indicates that the formed ruthenium oxide film is adsorbed on the first surface and the second surface, CO ₂ (g) Denotes gaseous carbon dioxide, H ₂ O (g) represents gaseous water.

It should be noted that the isolation layer can be chemically reacted (Ru (EtCp)2) ads + O on the second surface in the direction perpendicular to the substrate ^* →(Ru)ads+CO ₂ (g)+H ₂ O(g)，(Ru)ads+2O ^* →(RuO ₂ ) ads, and chemical reactions (RuO) ₂ )ads+2O ^* →RuO ₄ (g) It is understood that the ruthenium oxide formed is decomposed to form gaseous ruthenium tetroxide over a period of time, i.e., no film is deposited on the second surface after a period of time.

In order to facilitate the intuitive description of the process in which the first chemical reaction and the second chemical reaction are almost simultaneously performed on the first surface and the second surface, fig. 7 is a sectional view showing the positional relationship of the first surface B1 and the second surface B2 after other structures are omitted, and fig. 8 is an enlarged schematic view of the structures in the dotted circle in fig. 7.

Specifically, a precursor is provided, and referring to fig. 8, the precursor ru (etcp)2 is adsorbed to the first surface B1 and the second surface B2, wherein at least a part of the precursor is adsorbed to the first surface and the second surface. Referring to fig. 8, a plasma (O) is provided ^* ) And applying an electric field to make the precursor Ru (EtCp)2 and the plasma (O) on the first surface B1 ^* ) The precursor Ru (EtCp)2 and the plasma (O) react to form the first film 506 and the second surface B2 ^* ) Reacting to form ruthenium oxide while the ruthenium oxide reacts with plasma (O) ^* ) Reacting to generate gaseous ruthenium tetroxide; wherein the direction of the electric field lines of the electric field (shown as ee' in fig. 8) is parallel to the first surface B1 and directed to the second surface B2.

On the second surface, chemical reaction (Ru (EtCp)2) ads + O ^* →(Ru)ads+CO ₂ (g)+H ₂ O(g)，(Ru)ads+2O ^* →(RuO ₂ ) ads, and reaction with chemistry (RuO) ₂ )ads+2O ^* →RuO ₄ (g) Almost simultaneously, to form gaseous ruthenium tetroxide RuO ₄ I.e., no film is deposited on the second surface B2, resulting in a high quality first film 506 on the first surface B1.

In the embodiment of the disclosure, a free radical enhanced atomic layer deposition (real) process is used to form the thin film, and the deposition mode has the advantages of precise and controllable thickness, good surface uniformity, excellent conformality, capability of depositing in a high aspect ratio groove and a channel, and the like, so that the first thin film formed on the first surface with high quality can be obtained, the performance of the formed semiconductor device is improved, and the performance of the memory device is further improved. In addition, a free Radical Enhanced Atomic Layer Deposition (REALD) process is adopted to deposit the first film on the first surface, and the first chemical reaction and the second chemical reaction can be almost simultaneously carried out on the second surface, so that the film is not deposited on the second surface, the preparation time is saved, the preparation cost is reduced, and the selective direction deposition is realized, namely the oxygen radicals are provided and the electric field is applied to promote the growth of the film in one direction and inhibit the growth of the film in the other direction.

In one embodiment, step S40 includes:

Illustratively, the first and second thin films may be formed using an atomic layer deposition process (ALD) that deposits the first and second thin films by sequentially exposing the first and second surfaces to a precursor and a plasma. The description is made with the constituent materials of the first thin film and the second thin film including ruthenium oxide.

Specifically, placing the first surface and the second surface in an atomic layer deposition reactor may provide for adsorption of a precursor (e.g., ru (cp)2) to the first surface and the second surface, and oxygen (O) gas ₂ ) And depositing to form a ruthenium oxide film on the first surface and the second surface.

It should be noted that, in order to intuitively describe a process of removing a thin film on the second surface after the thin film is formed on the first surface and the second surface by the Atomic Layer Deposition (ALD), fig. 9 is another enlarged schematic diagram of the structure in the dotted circle in fig. 7.

Specifically, referring to fig. 9, first and second thin films are formed on the first and second surfaces B1 and B2 using an atomic layer deposition process (ALD). Referring to fig. 9, after forming the first thin film and the second thin film, plasma (O) is provided ^* ) And applying an electric field to make the second film on the second surface B2 and plasma (O) ^* ) Reacting to remove the second film; wherein the direction of the electric field lines of the electric field (shown as ee' in fig. 9) is parallel to the first surface B1 and directed to the second surface B2. I.e. on the second surface B2, a chemical reaction (RuO) takes place ₂ )ads+2O ^* →RuO ₄ (g) Formation of gaseous ruthenium tetroxide RuO ₄ And finally the first film 506 on the first surface B1 with high quality is obtained.

In the embodiment of the disclosure, an Atomic Layer Deposition (ALD) process is adopted to form the thin film, and the deposition mode has the advantages of accurate and controllable thickness, good surface uniformity, excellent conformality, capability of depositing in a high-aspect-ratio groove and a channel, and the like, so that the first thin film formed on the first surface with high quality can be obtained, the performance of the formed semiconductor device is improved, and the performance of the memory device is further improved.

In one embodiment, the plasma includes oxygen radicals.

In practice, the plasma may be generated by a plasma generator, and specifically, at least one of oxygen ions, oxygen radicals, oxygen molecular ions, oxygen molecular radicals, and ozone may be generated by exciting oxygen molecules.

In the disclosed embodiments, oxygen radical (O) ^* ) The plasma reactant can enhance the deposition rate of the first film and the second film. In addition, oxygen free radical (O) ^* ) The second surface of the second film can be removed without etching, and the flatness of the first film formed on the first surface can be improved.

In one embodiment, step S50 includes:

the plasma reacts with the second thin film of the second surface to produce a gaseous compound.

Illustratively, the plasma includes oxygen radicals (O) ^* ) The composition material of the first film and the second film includes ruthenium oxide according to the chemical reaction formula (RuO) ₂ )ads+2O ^* →RuO ₄ (g) It can be seen that the second thin film RuO of the second surface ₂ Reaction with oxygen radicals to gaseous RuO ₄ I.e. second film RuO with second surface removed ₂ Wherein (RuO) ₂ ) ads denotes second film RuO ₂ Adsorbed on a second surface, O ^* Representing oxygen radicals, RuO ₄ (g) Denotes gaseous RuO ₄ 。

Specifically, the chemical reaction formula (RuO) ₂ )ads+2O ^* →RuO ₄ (g) The reaction can be carried out in an environment with a reaction temperature of 30 ℃ to 300 ℃.

In embodiments of the disclosure, the plasma (e.g., oxygen radical O) ^* ) Can react with the second film (such as ruthenium oxide) on the second surface to remove the second film on the second surface without etching, thereby improving the flatness of the first film formed on the first surface. In addition, a complex process of alternating deposition and etching is not needed, so that the process can be simplified and the cost can be reduced.

In one embodiment, the gaseous compound comprises ruthenium tetroxide.

In embodiments of the disclosure, the plasma (e.g., oxygen radical O) ^* ) Can react with the second film (e.g. ruthenium oxide) of the second surface according to the chemical reaction formula (RuO) ₂ )ads+2O ^* →RuO ₄ (g) It is known that the gaseous compound produced comprises ruthenium tetroxide (RuO) ₄ )。

In an embodiment, after step S50, the forming method further includes:

and removing gaseous compounds generated by the reaction of the plasma and the second film.

In one example, the gaseous compound includes ruthenium tetroxide (RuO) ₄ ) An inert gas purge operation may be performed to remove the ruthenium tetroxide (RuO) produced ₄ ). Specifically, an inert gas such as nitrogen (N) ₂ ) Purging nitrogen (N) of gaseous compounds ₂ ) May be set at 40ml/min, purged with nitrogen to remove ruthenium tetroxide (RuO) ₄ ). The specific type, flow rate and purge time of the purge gas may be set according to practical circumstances, and the present disclosure is not limited thereto.

In another example, the pumping operation may be performed by a pump (e.g., a vacuum pump) to remove the generated gaseous compound ruthenium tetroxide (RuO) ₄ )。

In an embodiment, the forming method further comprises:

and removing the precursor which is not adsorbed by the first surface and the second surface.

In one example, an inert gas purging operation is performed to remove precursor that is not adsorbed by the first and second surfaces prior to providing the plasma to react the precursor of the first surface with the plasma to form the first thin film and the precursor of the second surface with the plasma to form the second thin film.

Specifically, an inert gas such as nitrogen (N) ₂ ) Purging Nitrogen (N) of the precursor ₂ ) May be set to 40ml/min, and the precursor that is not adsorbed by the first and second surfaces is removed by a nitrogen purge. Particular classes of purge gasesThe type, flow rate and purge time may be set according to practical circumstances, and the disclosure is not limited thereto.

In another example, an inert gas such as nitrogen (N) is used ₂ ) As the carrier gas of the precursor, when the inert gas purging operation is performed, the flow rate of the carrier gas can be set to be 80ml/min, the precursor for growing the ruthenium oxide film is bis-ethylcyclopentadienyl-ruthenium (Ru (EtCp)2), and the carrier gas (N) is used for passing through ₂ ) The precursor bis-ethylcyclopentadienyl-ruthenium (ru (etcp)) 2 was brought into the deposition reactor to adsorb the precursor on the first and second surfaces.

In one embodiment, the precursor comprises an organic coordination compound of ruthenium.

The precursor is one existing form before the target product (ruthenium oxide) is obtained, and the existing form of the precursor includes but is not limited to organic-inorganic complexes, mixture solids or sols.

In one example, the constituent material of the first and second thin films includes ruthenium oxide (RuO) ₂ ) The precursor for forming the first thin film and the second thin film includes an organic complex compound of ruthenium.

In another example, a constituent material of the first thin film and the second thin film includes aluminum oxide (Al) ₂ O ₃ ) The precursor for forming the first thin film and the second thin film includes trimethylaluminum (Al (CH) ₃ )3)。

It is understood that the precursor may comprise organic coordination compounds of different metals, including but not limited to ruthenium (Ru), tungsten (W), cobalt (Co), rhodium (Rh), iridium (Ir), or molybdenum (Mo), and the disclosure does not limit the kind of precursor.

In one embodiment, the organic coordination compound of ruthenium comprises bis-ethylcyclopentadienyl-ruthenium.

In practical applications, the first thin film and the second thin film are made of ruthenium oxide (RuO) ₂ ) The precursor for forming the first thin film and the second thin film includes an organic complex compound of ruthenium.

In one example, the organic coordination compound of ruthenium is bis-ethylcyclopentadienyl-ruthenium (ru (etcp) 2). In another example, the organic coordination compound of ruthenium is bis-cyclopentadienyl-ruthenium (ru (cp) 2).

Since bis-ethylcyclopentadienyl-ruthenium (ru (etcp)) 2 exists in a liquid form at around room temperature, the reaction can be carried out by using an existing film forming apparatus, and the flow rate can be controlled by using an existing mass flow rate controller, which has an advantage of stabilizing the supply. While bis-cyclopentadienyl-ruthenium (ru (cp)2) exists in a solid form at around room temperature and is hardly soluble in an organic solvent, bis-ethylcyclopentadienyl-ruthenium is selected as a precursor in the embodiments of the present disclosure.

In one embodiment, the constituent material of the first and second thin films includes ruthenium dioxide.

In the embodiment of the present disclosure, the dielectric characteristics of the inter-electrode dielectric layer of the capacitor may be improved by directionally selectively depositing the ruthenium oxide lower electrode of the 3D DRAM lying capacitor, and then depositing a high dielectric material on the bottom electrode formed of metal or metal oxide as the inter-electrode dielectric layer of the capacitor, so that the bottom electrode is formed using metal such as ruthenium (Ru), tungsten (W), cobalt (Co), rhodium (Rh), iridium (Ir), or molybdenum (Mo). For example, the constituent material of the first thin film and the second thin film is provided to include ruthenium dioxide.

In an embodiment, after step S50, the forming method further includes:

forming an inter-electrode dielectric layer 601 in the gap covering the first thin film 506 and the second surface;

an electrode layer 602 is formed overlying the inter-electrode dielectric layer.

It should be noted that, in order to facilitate visual description of the positional relationship among the first film 506, the inter-electrode dielectric layer 601, and the electrode layer 602, fig. 6 is a cross-sectional view showing the positional relationship among the first film 506, the inter-electrode dielectric layer 601, and the electrode layer 602, with other structures omitted.

In practice, the inter-electrode dielectric layer 601 covering the first thin film 506 and the second surface may be formed by one or more deposition processes including, but not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or any combination thereof. For example, the inter-electrode dielectric layer 601 may be formed by an atomic layer deposition process.

Here, the material of the inter-electrode dielectric layer 601 may be a dielectric material such as silicon dioxide, aluminum oxide, or the like.

In practice, the process for forming the electrode layer 602 includes, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or any combination thereof. For example, the electrode layer may be formed by an atomic layer deposition process. In practical applications, the material of the electrode layer 602 may be a metal material or a semiconductor conductive material, such as copper, cobalt, tungsten, molybdenum, doped silicon, polysilicon, or any combination thereof.

In one embodiment, the semiconductor device includes a capacitor including a first thin film 506, an inter-electrode dielectric layer 601, and an electrode layer 602; wherein the first film 506 is electrically conductive.

In this embodiment, a dynamic random access memory is taken as an example for description. In general, a memory cell of a DRAM includes a memory cell architecture of 1 transistor T and 1 capacitor C (1T1C) for storing written data. Referring to fig. 6, the material of the support layer 501 includes silicon (Si), and the support layer 501 of the second region a2 is used as a support column of the capacitor formed by the second region a 2.

Illustratively, the capacitor includes a first thin film 506, an interpoly dielectric layer 601, and an electrode layer 602; the first film 506 serves as a lower electrode of the capacitor, and the electrode layer 602 serves as an upper electrode of the capacitor. In one example, the upper electrode contacts the source of the transistor, the inter-electrode dielectric layer 601 electrically isolates the upper electrode from the lower electrode, and the lower electrode is coupled to a reference voltage terminal, which may be a ground voltage, or may include other voltages. In another example, the lower electrode is in contact with the source of the transistor, and the inter-electrode dielectric layer 601 electrically isolates the upper electrode from the lower electrode, and the upper electrode is coupled to a reference voltage terminal.

It should be noted that, common memories are listed here by way of example only, the scope of the disclosure is not limited thereto, and any memory including the semiconductor device provided by the embodiment of the disclosure belongs to the scope of the disclosure.

In an embodiment, the forming method further comprises:

forming a transistor coupled to the capacitor in the first region; wherein the source of the transistor is in contact with the first thin film.

In practical applications, referring to fig. 5, the first region a1 of the substrate 50 is used to form a transistor, which may include: the source electrode, the channel and the drain electrode are arranged in parallel; a gate covering at least one sidewall of the channel; and the gate dielectric layer is positioned between the gate and the channel. The transistor can be formed by a conventional method, and is not described herein.

It will be appreciated that in the architecture of 1T1C, the source and drain locations may be interchanged, and if the first film of capacitor C in the memory cell is connected to the source of transistor T, the bit line is connected to the drain of transistor T; alternatively, if the first thin film of the capacitor C in the memory cell is connected to the drain of the transistor T, the bit line is connected to the source of the transistor T, which is not limited by the present disclosure.

In one embodiment, forming a transistor coupled to a capacitor in a first region includes:

forming a channel; wherein the support layer of the first region is used for forming a channel;

forming a gate surrounding the channel;

a source and a drain of the transistor are formed at both ends in the extending direction of the channel, respectively.

In practical applications, referring to fig. 5, a first region a1 of the substrate 50 is used to form a transistor, and a stacked structure including a support layer 501 and a dielectric layer 502 alternately stacked is formed on the substrate 50. Illustratively, the material of the dielectric layer 502 may include silicon oxide or silicon germanium (SiGe), and the like, and the material of the support layer 501 may include silicon (Si), germanium (Ge), and the like. The support layer 501 of the first area a1 is used to form a channel.

The gate is disposed around the channel, that is, the transistor in the embodiment of the present disclosure may specifically be a full-surround type gate transistor. It should be noted that the transistors in the embodiments of the present disclosure are not limited to the full-wrap gate transistors, and may also include other types of transistors, such as half-wrap gate transistors, column gate transistors, and the like. In practical application, a gate dielectric layer is also formed between the gate and the channel.

In one example, a source and a drain (not shown) are formed at opposite ends of the channel, respectively. In one example, the source and drain are doped P-type and the channel is doped N-type. In another example, the source and drain are doped N-type and the channel is doped P-type. Here, the doping type of the source and the drain are the same, and the doping concentration of the source and the drain may be the same or different, and the disclosure is not limited thereto.

It should be understood that the operations shown in the steps in the above-described method for forming a semiconductor device are not necessarily performed in a precise order, and instead, the steps may be processed in any order or simultaneously. In addition, other operational steps may also be added to these processes.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present disclosure, and shall cover the scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising:

removing the second portion of the dielectric layer to form a gap; wherein the gap reveals a first surface of the support layer and a second surface of the isolation layer in a direction perpendicular to the substrate;

2. The method according to claim 1, wherein the forming a first film covering the first surface and a second film covering the second surface comprises:

3. The method according to claim 1, wherein the forming a first film covering the first surface and a second film covering the second surface comprises:

4. The method according to claim 1 or 2, wherein the plasma includes oxygen radicals.

5. The method of claim 1, wherein the providing the plasma and applying the electric field to remove the second film after the plasma reacts with the second film on the second surface comprises:

6. The method according to claim 5, wherein the gaseous compound comprises ruthenium tetroxide.

7. The method of claim 5, wherein after providing the plasma and applying the electric field to remove the second film after reacting the plasma with the second film of the second surface, the method further comprises:

8. The method of claim 2, wherein said providing said plasma to react said first surface precursor with said plasma to form said first thin film and said second surface precursor with said plasma to form said second thin film further comprises:

9. The method according to claim 2, wherein the precursor comprises an organic complex compound of ruthenium.

10. The method of claim 8, wherein the organic coordination compound of ruthenium comprises bis-ethylcyclopentadienyl-ruthenium.

11. The method according to claim 1, wherein a constituent material of the first thin film and the second thin film comprises ruthenium dioxide.

12. The method of claim 1, wherein after providing the plasma and applying the electric field to remove the second film after reacting the plasma with the second film of the second surface, the method further comprises:

forming an inter-electrode dielectric layer in the gap to cover the first thin film and the second surface;

and forming an electrode layer covering the interelectrode dielectric layer.

13. The method according to claim 12, wherein the semiconductor device comprises a capacitor including the first thin film, the inter-electrode dielectric layer, and the electrode layer; wherein the first film is electrically conductive.

14. The method of forming a semiconductor device according to claim 13, further comprising:

15. The method of claim 14, wherein the forming a transistor coupled to the capacitor in the first region comprises:

forming a gate surrounding the channel;