CN115020323A

CN115020323A - Pattern forming method, data line contact forming method and device manufacturing method

Info

Publication number: CN115020323A
Application number: CN202110245925.2A
Authority: CN
Inventors: 崔栽荣; 贺晓彬; 杨涛; 刘金彪; 李亭亭
Original assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Current assignee: Institute of Microelectronics of CAS; Zhenxin Beijing Semiconductor Co Ltd
Priority date: 2021-03-05
Filing date: 2021-03-05
Publication date: 2022-09-06

Abstract

The present disclosure provides a pattern forming method, a data line contact forming method, and a method of manufacturing a device, and the pattern forming method may include the following steps. The method includes providing a semiconductor substrate, forming a first film on the semiconductor substrate, and forming a first pattern on the first film along a first direction. A second film layer is formed on the first film layer, and a second pattern is formed on the second film layer along a second direction. Wherein, the second direction is intersected with the first direction. The first film layer with the first pattern and the second film layer with the second pattern are used as masks, and the semiconductor substrate is etched to form the stripe-shaped groove pattern, so that the plurality of stripe-shaped grooves can be formed at the designated positions on the semiconductor substrate. Compared with the data line contact part in the form of a conventional circular pattern, the technical scheme of the disclosure can provide the data line contact part in the form of a line/gap pattern, and has the advantages of smaller structure size, larger pattern allowance, reduction of processing difficulty of a semiconductor device and the like.

Description

Pattern forming method, data line contact forming method and device manufacturing method

Technical Field

The present disclosure relates to the field of semiconductor device processing technology, and more particularly, to a pattern forming method, a data line contact forming method, and a device manufacturing method.

Background

As the integration of semiconductor devices becomes higher and smaller, the critical dimension of the target pattern becomes smaller and smaller, and a problem of insufficient pattern margin (PatternMargin) often occurs. Although the basic process for processing semiconductor devices is mature, the semiconductor device manufacturing difficulty is increased significantly due to the drastic reduction in the size of the semiconductor device (Scale Down). In particular, a Data Line Contact (DLC) of a semiconductor memory for electrical connection is taken as an example. Due to the limitations of the prior art, conventional data line contacts tend to be in a circular pattern. The size of the contact portion of the data line in the circular pattern form is often large, and thus the design size requirement of a highly integrated semiconductor device Layout (Layout) cannot be met, and the yield of the semiconductor device manufactured based on the contact portion in the circular pattern form is low.

Disclosure of Invention

In order to solve the problem of insufficient pattern margin frequently occurring in the prior art, the present disclosure can provide a pattern forming method, a data line contact forming method, and a device manufacturing method, so as to achieve at least one technical purpose of effectively improving the pattern margin and reducing the pattern size of a semiconductor device.

To achieve the above technical object, the present disclosure provides a method of forming a pattern of a semiconductor device; the pattern forming method may include, but is not limited to, at least one of the following steps.

The method includes providing a semiconductor substrate, forming a first film on the semiconductor substrate, and forming a first pattern on the first film along a first direction. A second film layer is formed on the first film layer, and a second pattern is formed on the second film layer along a second direction. Wherein, the second direction is intersected with the first direction. The semiconductor substrate is etched one or more times using the first film layer having the first pattern and the second film layer having the second pattern as masks to form a stripe-shaped groove pattern on the semiconductor substrate, and it can be seen that the present disclosure can form a plurality of stripe-shaped grooves at designated positions on the semiconductor substrate, and the stripe-shaped grooves can be used as contact holes.

To achieve the above technical objects, the present disclosure may also provide a method for forming a data line contact of a semiconductor memory. The contact forming method may include the semiconductor device pattern forming method in any embodiment of the present disclosure, and further includes: after a plurality of strip-shaped grooves are formed in the semiconductor substrate, the first film layer and the second film layer are removed; then, a material for forming a contact portion, such as polysilicon or the like, is filled into the stripe-shaped groove serving as the contact hole to form a stripe-shaped semiconductor memory data line contact portion. Which may be, for example, a dynamic random access memory.

To achieve the above technical object, the present disclosure can also provide a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device may include, but is not limited to, the method of patterning the semiconductor device in any of the embodiments of the present disclosure.

The beneficial effect of this disclosure does:

the present disclosure provides a novel method for processing a semiconductor device pattern, which can significantly improve the yield of a semiconductor device and is particularly suitable for manufacturing a data line contact in a semiconductor memory structure. Compared with the conventional data line contact part in the form of a circular pattern, the technical scheme of the disclosure can provide the data line contact part in the form of a line/space (line/space) pattern, and has the outstanding advantages of smaller structure size, larger pattern margin, reduction of processing difficulty of a semiconductor device and the like. This is disclosed forms the data line contact part based on line/space pattern, has greatly improved pattern resolution, obtains the line pattern that key dimension is littleer, finer to satisfy semiconductor device's design requirement.

Drawings

Fig. 1 shows a schematic top view of a semiconductor substrate after forming a buried channel array transistor and a shallow trench isolation pattern thereon in one or more embodiments of the present disclosure.

Fig. 2 illustrates a schematic top view structure after a first pattern is formed on a first film layer over a semiconductor substrate in one or more embodiments of the disclosure.

Fig. 3 illustrates a schematic top view structure of a second film layer over a first film layer after a second pattern is formed thereon in one or more embodiments of the present disclosure.

Fig. 4 shows a schematic top view structure diagram after etching a semiconductor substrate based on a combined pattern obtained by superimposing the first pattern and the second pattern in one or more embodiments of the present disclosure.

Fig. 5 is a schematic top view illustrating a contact portion formed by filling polysilicon in a strip-shaped via according to one or more embodiments of the present disclosure.

Fig. 6 illustrates a schematic top view structure after removing a first film layer having a first pattern and a second film layer having a second pattern in one or more embodiments of the disclosure.

Fig. 7 shows an enlarged schematic view of the wire area at a in fig. 4 (the pattern is illustrated in a perspective state).

Fig. 8 shows an enlarged schematic view of the wire area at B in fig. 5 (the pattern is illustrated in a perspective state).

In the figure, the position of the upper end of the main shaft,

100. a semiconductor substrate.

200. A buried channel array transistor.

300. Shallow trench isolation patterns.

301. A strip-shaped groove.

400. A first pattern.

500. A second pattern.

600. A contact portion.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions, layers and their relative sizes, positional relationships are shown in the drawings as examples only, and in practice deviations due to manufacturing tolerances or technical limitations are possible, and a person skilled in the art may additionally design regions/layers with different shapes, sizes, relative positions according to the actual needs.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

One or more embodiments of the present disclosure can provide a semiconductor device pattern forming method capable of forming finer patterns and improving an Overlay Margin (Overlay Margin). The semiconductor device patterning method may include, but is not limited to, at least one of the following steps.

As shown in fig. 1, a semiconductor substrate 100 is provided, and a Buried Channel Array Transistor 200 (BCAT) may be formed on the semiconductor substrate 100 in a third direction. Then, a Shallow Trench Isolation (STI) pattern 300 is formed on the semiconductor substrate 100 in a first direction, and lines in the STI pattern are arranged in parallel. Wherein, the first direction and the third direction are intersected. The process of forming the transistor in the present disclosure can be reasonably selected as needed, and the details of the present disclosure are not repeated. The semiconductor substrate 100 may be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG), among others. It is to be understood that the detailed structures of the gate, the source/drain, and the like included in the buried channel array transistor 200 are not repeated in this embodiment.

As shown in fig. 2, a first film layer is formed on a semiconductor substrate 100, and a first pattern 400 is formed on the first film layer along a first direction. The first pattern 400 extends in a first direction. Forming the first pattern 400 on the first film layer along the first direction in some embodiments of the present disclosure includes: a first pattern 400 having the same extension direction as the shallow trench isolation pattern 300 is formed on the first film layer, and the shallow trench isolation pattern 300 can be exposed. Wherein the first pattern 400 and the shallow trench isolation pattern 300 may be formed to have the same Critical Dimension (CD). In a plan view, it is equivalent to form the first pattern 400 around the shallow trench isolation pattern 300, or the lines of the shallow trench isolation pattern 300 are arranged alternately with the lines of the first pattern 400. In the embodiment of the present disclosure, the first film Layer may be, for example, a Spin-On hard mask (SOH) or an Atomic Layer deposition oxide (ald oxide) film, and the oxide may be, for example, an oxide of silicon or a metal oxide, and the disclosure is not limited thereto.

Specifically, when one or more embodiments of the present disclosure processes the first film layer as described above, the first Pattern 400 may be formed using a Double Patterning Technology (DPT) manner, wherein the first Pattern 400 is a Bar Pattern (Bar Pattern). More specifically, the dual imaging in the present disclosure may be Self-Aligned dual imaging (SADP) or Self-Aligned reversed imaging (SARP). It should be understood that atomic layer deposition is one method by which a substance may be deposited as a single atomic film layer by layer on a substrate surface. In addition, for the process details such as photoetching and etching involved in the self-aligned dual imaging or the self-aligned reverse imaging, the details can be selected according to the actual processing condition, and the details are not repeated in the disclosure.

As shown in fig. 3, a second film layer is formed on the first film layer; a second pattern 500 is formed on the second film layer along a second direction. The second patterns 500 extend in the second direction, wherein gaps between the second patterns 500 may be the same as or different from gaps between the first patterns 400. The second direction is intersected with the first direction; the second direction is intersected with the third direction. It can be understood that the specific inclination angles of the first direction, the second direction and the third direction can be reasonably set according to actual conditions. For example, the third direction is a vertical extending direction as shown, the first direction may be an extending direction of the third direction rotated counterclockwise by 15 degrees, and the second direction may be an extending direction of the third direction rotated counterclockwise by 40 degrees. Additionally, the second film layer in some embodiments of the present disclosure is a spin-on hard mask or an atomic layer deposited oxide film. More specifically, the present disclosure is also capable of forming the second Pattern 500 using a dual imaging mode, which is a self-aligned dual imaging or a self-aligned reverse imaging, and the second Pattern 500 in some embodiments of the present disclosure is a Bar Pattern (Bar Pattern).

It is understood that some embodiments of the present disclosure can use a Dipole (Dipole) light source in the particular photolithography process involved in forming the first pattern 400 or the second pattern 500. Based on the dipole light source, the present disclosure can further improve semiconductor device pattern Resolution (Resolution).

As shown in fig. 4, and may be combined with fig. 7, the semiconductor substrate 100 is etched using the first film layer having the first pattern 400 and the second film layer having the second pattern 500 as masks at the same time to form a stripe-shaped groove 301 pattern on the semiconductor substrate 100. The strip-shaped groove 301 can be used as a contact hole, and it can be seen that the strip-shaped contact hole can be processed by the present disclosure. The strip-shaped contact hole is completely different from a conventional circular contact hole, and has the advantages of smaller size, higher resolution and the like. The etching manner may include, for example, but not limited to, dry etching, so as to achieve the stripe-shaped groove 301 required by the present disclosure.

As shown in fig. 5, and may be combined with fig. 8, in one or more embodiments of the present disclosure, a method for forming a data line contact of a semiconductor memory can also be provided. The data line Contact may include, for example, a word line Contact (wordline Contact) and a bit line Contact (BitLine Contact).

The semiconductor memory data line contact portion forming method comprises a semiconductor device pattern forming method in any one of the embodiments of the present disclosure.

As shown in fig. 6, after the stripe-shaped groove 301 is obtained by using the semiconductor device pattern forming method, the semiconductor memory data line contact forming method further includes: removing the first film layer and the second film layer; the stripe-shaped groove 301 serving as a contact hole (contact hole) is filled with a material for forming the contact portion 600, for example, a polycrystalline material (Polysilicon) such as Polysilicon or other material suitable for forming the data line contact portion, thereby forming the stripe-shaped semiconductor memory data line contact portion 600. Specifically, some embodiments of the present disclosure may deposit a layer of polysilicon on the semiconductor substrate 100, and then may make the upper surface of the polysilicon flush with the upper surface of the semiconductor substrate 100 by chemical mechanical planarization, thereby achieving the purpose of obtaining the data line contact portion of the semiconductor memory by filling the polysilicon in the strip-shaped contact hole.

The present disclosure can also provide a method of manufacturing a semiconductor device, which may include, but is not limited to, a semiconductor device pattern forming method in any embodiment of the present disclosure. The semiconductor device to which the present disclosure relates may be, for example, but not limited to, a Dynamic Random Access Memory (DRAM). A dynamic random access memory is a semiconductor memory device commonly used in computers, and includes a plurality of memory cells arranged in a matrix structure. Each memory cell mainly comprises a transistor and a capacitor controlled by the transistor, and the memory cells are electrically connected through word lines and bit lines. Data is input from the bit line and transferred to the capacitor through the transistor, or data stored in the capacitor is output through the transistor and the bit line. The semiconductor memory data line contacts formed in some embodiments of the present disclosure can be used for electrical connection of word lines and/or bit lines to other device layers. The dynamic random access memory may have a buried channel array transistor.

The semiconductor device manufactured based on the technical scheme of the disclosure can be used in electronic equipment. The electronic device may include, for example, but is not limited to, a smart phone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source, and the like.

In the above description, details of the techniques such as patterning and etching of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, the person skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims

1. A method for forming a pattern of a semiconductor device, comprising:

providing a semiconductor substrate;

forming a first film layer on the semiconductor substrate;

forming a first pattern on the first film layer along a first direction;

forming a second film layer on the first film layer;

forming a second pattern on the second film layer along a second direction; wherein the second direction intersects the first direction;

and simultaneously taking the first film layer with the first pattern and the second film layer with the second pattern as masks, and etching the semiconductor substrate to form a strip-shaped groove pattern on the semiconductor substrate.

2. The semiconductor device pattern forming method according to claim 1,

the method further comprises the following steps of before forming a first film layer on the semiconductor substrate: forming a shallow trench isolation pattern arranged along a first direction on the semiconductor substrate;

the forming a first pattern on the first film layer along a first direction comprises: and forming a first pattern which has the same extension direction with the shallow trench isolation pattern on the first film layer, and exposing the shallow trench isolation pattern.

3. The method of claim 2, wherein before forming the shallow trench isolation pattern disposed in the first direction, further comprising:

forming a buried channel array transistor on the semiconductor substrate along a third direction;

the first direction and the third direction are arranged in an intersecting mode, and the second direction and the third direction are arranged in an intersecting mode.

4. The method of claim 2 or 3,

the first pattern and the shallow trench isolation pattern have the same critical dimension.

5. The semiconductor device pattern forming method according to claim 1,

the first film layer is a spin-on hard mask or an atomic layer deposition oxide film;

the second film layer is a spin-on hard mask or an atomic layer deposition oxide film.

6. The semiconductor device pattern forming method according to claim 1,

forming the first pattern and/or the second pattern using a dual imaging method;

the dual imaging is self-aligned dual imaging or self-aligned reverse imaging.

7. The method of claim 1, wherein the step of forming the pattern comprises,

the first pattern is a bar pattern;

the second pattern is a stripe pattern.

8. A method for forming a data line contact of a semiconductor memory, comprising the method for forming a pattern of a semiconductor device according to any one of claims 1 to 7.

9. The method of claim 8, further comprising:

removing the first and second membrane layers;

and filling a material for forming the contact portion into the strip-shaped groove serving as the contact hole to form a strip-shaped semiconductor memory data line contact portion.

10. A method for manufacturing a semiconductor device, characterized by comprising the method for forming a pattern of a semiconductor device according to any one of claims 1 to 7.