CN115020264A - Method for detecting deep energy level defect state in large-size wafer - Google Patents
Method for detecting deep energy level defect state in large-size wafer Download PDFInfo
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Abstract
The invention provides a method for detecting deep energy level defect states in a large-size wafer, which comprises the following steps: providing a wafer to be detected; etching the bottom surface of the wafer to be detected to form a plurality of etching areas which are not connected with each other, wherein the area, which is not etched, of the bottom surface of the wafer to be detected is divided into a plurality of non-etching areas by the etching areas; forming a bottom metal layer on the bottom surface of the wafer to be detected; forming a patterned top metal layer on the top surface of the wafer to be detected; and measuring the deep energy level transient capacitance spectrum curve of the wafer to be detected, and drawing an Arrhenius curve by using the deep energy level transient capacitance spectrum curve to obtain the energy level position and concentration information of the deep energy level defect of the wafer to be detected. The method for detecting the defect state of the deep energy level in the large-size wafer can solve the problems that the defect state of the deep energy level in the large-size wafer cannot be accurately detected by the existing measuring technology, and meanwhile, the concentration and the energy level position of the defect state are difficult to detect.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for detecting a deep energy level defect state in a large-size wafer.
Background
Silicon is the main material of integrated circuits, and with the continuous shrinkage of semiconductor manufacturing processes, increasingly higher requirements are placed on the quality and size of silicon. Wafers have predominantly 2 inch (50mm), 3 inch (75mm), 4 inch (100mm), 6 inch (150mm), 8 inch (200mm), and 12 inch (300mm) gauges. The larger the size (diameter) of the wafer, the greater the number of chips that can be fabricated on each wafer, and the lower the cost per chip.
Silicon inevitably introduces impurities or defects during the crystal pulling process, which form defect state energy levels in the forbidden band. These deep level defect states have important effects on the performance of materials and devices, for example, the reliability of silicon devices is seriously affected by the fact that the deep level defect states in the forbidden band cannot release electrons in time after trapping the electrons; therefore, the defect states in the wafer production process need to be sampled and detected, but the larger the size of the wafer is, the more difficult the defect state detection of the deep energy level is.
Taking a 300mm large-size wafer as an example, the defect characterization method comprises the following steps: methods such as SEM detection after HCl etching, etching development after copper modification, appearance characterization after thermal oxidation, transient capacitance detection and the like, but the characterization methods cannot accurately detect defect states with deeper energy levels and are difficult to measure the concentration and the position of the energy levels.
Taking a traditional transient capacitance detection mode as an example, a Schottky junction is formed on one surface of a wafer to be detected during measurement, an ohmic junction is formed on the other surface of the wafer to be detected, a Schottky diode structure is formed, the leakage current of the Schottky diode is large, transient capacitance voltage can be rapidly released through the leakage current, and a transient capacitance spectrum curve with complete form cannot be formed; and the large leakage current also influences the magnitude of the measurement voltage during measurement and the temperature range during measurement, so that the defect of a deeper energy level cannot be accurately detected.
Therefore, how to accurately detect the energy level position and the concentration of the deep energy level defect through an effective measurement method has important significance for researching the influence of the deep energy level defect on 300mm large-size wafer materials and devices.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for detecting a deep level defect state in a large-sized wafer, which is used to solve the problems that the existing energy level defect state measurement technology for the large-sized wafer cannot accurately detect the deep level defect state in the wafer, and at the same time, the concentration and the energy level position of the defect state are difficult to detect.
In order to achieve the above and other related objects, the present invention provides a method for detecting deep level defect states in a large-sized wafer, the method comprising the steps of:
the detection method comprises the following steps:
providing a wafer to be detected;
etching the bottom surface of the wafer to be detected to form a plurality of etching areas which are not connected with each other, wherein the area, which is not etched, of the bottom surface of the wafer to be detected is divided into a plurality of non-etched areas by the etching areas at intervals, and the surface roughness of the etching areas is greater than that of the non-etched areas;
forming a bottom metal layer on the bottom surface of the wafer to be detected, wherein the bottom metal layer located in the etched region is in ohmic contact with the wafer to be detected, and the bottom metal layer located in the non-etched region is in Schottky contact with the wafer to be detected;
forming a patterned top surface metal layer on the top surface of the wafer to be detected, wherein the top surface metal layer is in Schottky contact with the wafer to be detected;
and measuring the deep energy level transient capacitance spectrum curve of the wafer to be detected, utilizing the deep energy level transient capacitance spectrum curve to draw an Arrhenius curve, and obtaining the energy level position and concentration information of the deep energy level defect of the wafer to be detected.
Optionally, defining N etched regions and K adjacent unetched regions as a test group, wherein the bottom metal layers covered by each test group are not connected to each other; wherein N is an integer of 1 or more, and K is an integer of 1 or more.
Optionally, the etching regions are in a long strip shape, and the width of each etching region is between 0.01mm and 1 mm.
Optionally, the bottom metal layer in the non-etched region is in contact with the wafer to be detected to form a bottom schottky junction, the top metal layer is in contact with the wafer to be detected to form a top schottky junction, and the barrier height of the bottom schottky junction is different from that of the top schottky junction.
Optionally, the diameter of the wafer to be detected is greater than or equal to 300 mm.
Optionally, the method for obtaining the energy level position and the concentration information of the deep energy level defect of the wafer to be detected includes:
providing a deep energy level transient spectrum testing device;
setting the test voltage of the deep energy level transient spectrum test device to be smaller than the starting voltage of the top surface Schottky junction of the wafer to be detected, and obtaining a multi-sub-trap deep energy level transient capacitance spectrum curve based on the measurement of the deep energy level transient spectrum test device;
setting the test voltage of the deep energy level transient spectrum test device to be greater than the starting voltage of the top surface Schottky junction of the wafer to be detected, and measuring based on the deep energy level transient spectrum test device to obtain a common deep energy level transient capacitance spectrum curve of the minority carrier trap and the multi-carrier trap;
carrying out envelope analysis on the multi-electron trap deep level transient capacitance spectrum curve, the minority electron trap and the multi-electron trap common deep level transient capacitance spectrum curve to obtain a minority electron trap deep level transient capacitance spectrum curve;
and making an Arrhenius curve by using the multi-electron trap deep energy level transient capacitance spectrum curve and the few-electron trap deep energy level transient capacitance spectrum curve, and obtaining the energy level position and concentration information of the deep energy level defect of the wafer to be detected.
Optionally, the arrhenius curve satisfies the following equation:
in the formula, e n For emission of electrons from deep energy levelsT is temperature, K is constant, σ n To capture the cross section, E C Is the conduction band energy level, E T Is the defect state energy level, and k is the boltzmann constant.
Optionally, temperature scanning is carried out on the wafer to be detected at different temperatures, and a deep energy level transient capacitance spectrum curve of deep energy level defects distributed along with the temperatures is measured; wherein the temperature is between 50K and 500K.
Optionally, in the step of measuring a deep level transient capacitance spectrum curve shared by the minority carrier trap and the majority carrier trap, the test voltage is between 2V and 10V.
As described above, according to the method for detecting a deep energy level defect state in a large-sized wafer, ohmic contact and schottky contact are formed on the bottom surface of the wafer to be detected, schottky contact is formed on the top surface of the wafer to be detected, the top surface schottky junction and the bottom surface schottky junction respectively located on the two surfaces form a double schottky diode structure together, and the leakage current of the double schottky diode structure is low, so that the measuring method can measure a defect state with a deeper energy level; the low leakage current also enables the measuring method to measure with higher measuring voltage, and reduces the interference of low-level defect state to the measuring result; meanwhile, the measurement temperature range during measurement is widened due to low leakage current, so that the electron excitation probability in the deep-level defect is higher, and more accurate information about the state concentration and the energy level position of the deep-level defect can be obtained.
Drawings
Fig. 1 is a schematic flow chart illustrating a method for detecting deep level defect states in a large-sized wafer according to the present invention.
Fig. 2 is a schematic view of a wafer structure to be tested according to the present invention.
Fig. 3 is a schematic structural diagram of the wafer to be tested after forming an etched region and an unetched region.
Fig. 4 is a schematic structural diagram of the wafer to be tested after the bottom metal layer is formed thereon.
Fig. 5 is a schematic structural diagram of the wafer to be tested after a patterned top metal layer is formed thereon according to the present invention.
Fig. 6 shows a deep level transient capacitance spectrum obtained by conventional transient capacitance detection in comparison example one.
Fig. 7 shows a deep level transient capacitance spectrum curve obtained by the detection method according to the present invention in a first comparative example.
FIG. 8 is a graph showing an Arrhenius curve obtained by the detection method according to the present invention in a comparative example.
Fig. 9 shows a deep level transient capacitance spectrum obtained by the conventional transient capacitance detection method in the second comparative example.
Fig. 10 shows a deep level transient capacitance spectrum curve obtained by the detection method according to the present invention in the second comparative example.
FIG. 11 is a graph showing an Arrhenius curve obtained by the detection method according to the present invention in a comparative example II.
Description of the element reference numerals
100 wafer to be inspected
110 bottom surface
111 etch region
112 unetched region
120 top surface
200 bottom metal layer
201 bottom surface ohmic junction
202 bottom surface schottky junction
300 patterned top metal layer
301 top surface schottky junction
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the present embodiment provides a method for detecting deep level defect states in a large-sized wafer, where the method includes steps 1) to 5).
Step 1): as shown in fig. 2, a wafer 100 to be inspected is provided.
In this embodiment, the wafer 100 to be detected is made of silicon, the forbidden band width of the wafer is only 1.1eV, the critical breakdown field strength is 0.3MV/cm, and the silicon is a narrow forbidden band material.
Specifically, the diameter of the wafer 100 to be detected is greater than or equal to 300 mm.
In this embodiment, the larger the size of the wafer 100 to be detected is, the more difficult the defect state characterization in the material thereof becomes, and the size of the wafer to be detected applicable to the detection method of this embodiment is at least equal to or greater than 300 mm.
Step 2): etching the bottom surface 110 of the wafer 100 to be detected to form a plurality of etching areas 111 which are not connected with each other, wherein the area of the bottom surface 110 of the wafer to be detected, which is not etched, is divided into a plurality of non-etching areas 112 by the etching area, and the surface roughness of the etching area 111 is greater than that of the non-etching areas 112.
In this embodiment, as shown in fig. 3, one surface of the wafer 100 to be detected is defined as a bottom surface 110, and the other surface is defined as a top surface 120; the bottom surface 110 is etched by an etching process to form an etching pit, so that the surface roughness of the etched area 111 is greater than that of the unetched area 112. The adopted etching process method can be wet chemical etching, capacitive coupling plasma etching, inductive coupling plasma etching, mechanical physical etching and the like.
Specifically, the etching regions 111 are in a strip shape, and the width of each etching region 111 is between 0.01mm and 1 mm.
In this embodiment, the left side and the right side of each etching region 111 are respectively an unetched region 112 (the unetched region is also in a strip shape), the left side and the right side of the unetched region 112 are respectively an etching region 111, the etching regions 111 and the unetched regions 112 are arranged at intervals and in an array, the width of each etching region and each unetched region is between 0.01mm and 1mm, and the depth of a pit formed by etching in the etching region is between 100nm and 10 μm.
Step 3): as shown in fig. 4, a bottom metal layer 200 is formed on the bottom surface 110 of the wafer 100 to be detected, wherein the bottom metal layer 200 located in the etched region 111 is in ohmic contact with the wafer 100 to be detected, and the bottom metal layer 200 located in the non-etched region 112 is in schottky contact with the wafer 100 to be detected.
In this embodiment, the bottom metal layer 200 in the etched region 111 contacts the wafer 100 to be detected to form a bottom ohmic junction 201, and the bottom metal layer 200 in the non-etched region 112 contacts the wafer 100 to be detected to form a bottom schottky junction 202. The method for forming the bottom metal layer 200 may include, but is not limited to, magnetron sputtering, molecular beam epitaxy, electron beam evaporation, and the like; the bottom metal layer 200 is formed to have a thickness of 50nm to 1000nm, and the material thereof may include, but is not limited to, Au, Ag, Al, Ti, Ni, W, TiN, Cu, and alloys thereof.
Specifically, N etched regions 111 and K adjacent unetched regions 112 are defined as a test group, and the bottom metal layer 200 covered on each test group is not connected to each other; wherein N is an integer greater than or equal to K.
In this embodiment, the bottom metal layer 200 may be etched by an etching method, the etched bottom metal layer 200 is divided into different regions, and the different regions are not connected to each other, so as to achieve isolation; or, in the step of forming the bottom metal layer 200, a mask layer may be used to cover the bottom metal layer above the test groups, and the bottom metal layer is not formed or an isolation wall structure is formed in the spacing region between the test groups, so as to achieve isolation.
Step 4): as shown in fig. 5, a patterned top metal layer 300 is formed on the top surface 120 of the wafer 100 to be tested, wherein the top metal layer 300 is in schottky contact with the wafer 100 to be tested.
In this embodiment, the patterned top metal layer 300 contacts the wafer 100 to be detected to form a plurality of top schottky junctions 301 that are not connected to each other, the plurality of top schottky junctions 301 are arranged in an array and vertically correspond to the test group of the bottom surface of the wafer to be detected, as shown in fig. 5, each top schottky junction 301 corresponds to at least one test group, the bottom schottky junctions 202 in the test groups, the silicon material and the top schottky junctions 301 form a double schottky contact diode with a three-layer structure, and the double schottky contact diode structure can effectively reduce leakage current generated during measurement. Moreover, each top surface schottky junction 301 and the corresponding test group form a detection area together, and deep level defects in different areas of the wafer 100 to be detected can be obtained by measuring different detection areas. The top metal layer 300 patterning method sequentially includes a coating process, an exposure process, and an etching process.
Specifically, the barrier heights of the bottom-side schottky junction 202 and the top-side schottky junction 301 may be the same or different. When the barrier heights of the bottom-side schottky junction 202 and the top-side schottky junction 301 are different, the schottky junction turn-on voltages at the two sides are different, and the higher schottky junction turn-on voltage makes the set value of the test voltage higher during the test.
In this embodiment, the barrier height of the bottom surface schottky junction 201 is different from the barrier height of the top surface schottky junction 301. As an example, the barrier height of the bottom schottky junction 201 may be different from the barrier height of the top schottky junction 301 by selecting different metal materials, or the barrier height of the bottom schottky junction 201 may be different from the barrier height of the top schottky junction 301 by doping. Preferably, the bottom metal layer and the top metal layer are made of different metals, so that the barrier height of the bottom schottky junction 201 is different from that of the top schottky junction 301.
Step 5): and measuring the deep energy level transient capacitance spectrum curve of the wafer 100 to be detected, and drawing an arrhenius curve by using the deep energy level transient capacitance spectrum curve to obtain the energy level position and concentration information of the deep energy level defect of the wafer 100 to be detected.
In this embodiment, during measurement, the bottom schottky junction 202 and the bottom ohmic junction 201 in the bottom metal layer 200 are grounded, the top schottky junction 301 in the top metal layer 300 is connected to the test voltage interface, the dual schottky contact diode structure can effectively reduce leakage current generated during measurement, and the grounded bottom ohmic junction 201 can ensure that the change in capacitance value measured during measurement is caused by deep level defects. The deep energy level transient capacitance spectrum can be measured by adopting methods such as a standard deep energy level transient capacitance spectrum, a Laplace transform deep energy level transient capacitance spectrum, a Fourier transform deep energy level transient capacitance spectrum, a normal capacitance deep energy level transient voltage spectrum, a double-pulse deep energy level transient capacitance spectrum and the like.
Specifically, the method for obtaining the energy level position and the concentration information of the deep energy level defect of the wafer 100 to be detected includes: step 51) to step 55).
Step 51): a deep energy level transient spectrum testing device is provided.
In this embodiment, the deep energy level transient spectrum testing device may be a deep energy level transient spectrum tester or an electrical probe station, and during measurement, temperature scanning is performed on the wafer to be tested at different temperatures, so as to measure a deep energy level transient capacitance spectrum curve of deep energy level defects distributed along with the temperature; wherein the scanning temperature is not less than 50K at the lowest and not more than 500K at the highest.
Step 52): setting the test voltage of the deep energy level transient spectrum test device to be less than the opening voltage of the top surface Schottky junction 301 of the wafer 100 to be detected, and obtaining a multi-sub-trap deep energy level transient capacitance spectrum curve based on the measurement of the deep energy level transient spectrum test device.
In this embodiment, after the metal material of the top metal layer 300 is selected, the schottky junction turn-on voltages at different temperatures can be calculated through the barrier heights between the metal material and the silicon material, the temperature range during measurement is further selected, the test voltage is set to be smaller than the turn-on voltage (the schottky junction turn-on voltage corresponding to the highest measurement temperature), and the multi-quantum trap deep-level transient capacitance spectrum curve is measured.
Moreover, because the bottom schottky junction 202, the silicon material and the top schottky junction 301 form a double-schottky contact diode structure, the leakage current is small, and therefore, when the test is carried out in a high-temperature interval (the size of the leakage current is in positive correlation with the temperature), the potential between the capacitor plates formed at the two ends of the wafer to be detected is slowly reduced, so that the formed capacitance spectrum curve is completely represented; moreover, the higher the temperature, the higher the probability that electrons in the defect state of the deeper level are excited, and the more accurately the deep level defect state can be measured.
Step 53): setting the test voltage of the deep energy level transient spectrum test device to be greater than the opening voltage of the top surface Schottky junction 301 of the wafer 100 to be detected, and obtaining a common deep energy level transient capacitance spectrum curve of the minority carrier trap and the multi carrier trap based on the measurement of the deep energy level transient spectrum test device.
In this embodiment, the test voltage is set to be greater than the turn-on voltage (schottky junction turn-on voltage corresponding to the lowest measurement temperature); because the bottom schottky junction 202, the silicon material and the top schottky junction 301 form a double schottky contact diode structure with small leakage current, when the test voltage is set to be larger during measurement, the potential between the capacitor plates formed at the two ends of the wafer to be detected can be maintained in a high voltage interval for a longer time, and deep level information can be obtained better (the interference of shallow level information is avoided). By way of example, in the step of measuring the deep level transient capacitance spectrum curve shared by the minority carrier trap and the multi carrier trap, the test voltage is between 2V and 10V (including two end values).
Step 54): and carrying out envelope analysis on the multi-electron trap deep level transient capacitance spectrum curve, the minority electron trap and the multi-electron trap shared deep level transient capacitance spectrum curve to obtain the minority electron trap deep level transient capacitance spectrum curve.
Step 55): and making an arrhenius curve by using the multi-sub trap deep level transient capacitance spectrum curve and the minority trap deep level transient capacitance spectrum curve, and obtaining the energy level position and concentration information of the deep level defect of the wafer 100 to be detected.
Specifically, the arrhenius curve satisfies the following equation:
in the formula, e n Thermal emissivity of electrons emitted from deep levels, T is temperature, K is constant, σ n To capture the cross-section, E C Is the conduction band energy level, E T Is the defect state energy level, and k is the boltzmann constant.
In this embodiment, the energy level position of the defect state can be obtained by using the slope of the arrhenius curve, the trapping cross section of the defect state can be obtained from the intercept, and the concentration of the defect state can be obtained from the peak intensity of the deep-level transient capacitance spectrum.
In order to better demonstrate the beneficial effects of the method for detecting deep level defect states in a large-sized wafer according to the present embodiment, the present embodiment further provides two comparative examples for illustration.
Comparative example 1
In this comparative example: the size of the wafer 100 to be inspected is 300 mm.
Detecting by adopting a traditional transient capacitance detection method, forming a top metal Ni layer on the upper surface of the wafer 100 to be detected, wherein the thickness of the top metal Ni layer is 100nm, and the top metal Ni layer is in Schottky contact with the silicon material; after the lower surface of the wafer 100 to be detected is completely etched, a bottom metal AL layer is formed, the thickness of the bottom metal AL layer is 100nm, the bottom metal Ni layer is in ohmic contact with a silicon material, the measurement is carried out by a standard deep level transient capacitance spectrum technology, the applied measurement voltage is 0.2V and 5V respectively, the temperature scanning range during the measurement is 50K-300K, two parameters of 264Hz and 352Hz are used for carrying out measurement for two times, the deep level transient capacitance spectrum curve of the wafer 100 to be detected obtained by the two measurements is shown in figure 6, the signal curve is irregular, the curve has great fluctuation, and an Arrhenius curve cannot be obtained through the test curve;
by adopting the detection method of the deep level defect state provided by the embodiment, the top metal layer 300 adopts metal Ni with the thickness of 100nm, and the width of each top electrode 301 is 1 mm; the bottom metal layer 200 is made of metal AL with the thickness of 100nm, the width of the bottom ohmic junction is 0.1mm, and the width of the bottom Schottky junction 202 is 0.1 mm; each top surface schottky junction 301 corresponds to 5 bottom surface ohmic junctions and 5 bottom surface schottky junctions 202, the temperature scanning range during measurement is 50K-300K, the applied measurement voltage is 0.2V and 5V respectively, two times of measurement are carried out by using two parameters of 264Hz and 352Hz, the deep energy level transient capacitance spectrum curve of the wafer 100 to be detected obtained through two times of measurement is shown in fig. 7 and is displayed as a regular deep energy level signal curve, and an arrhenius curve (shown in fig. 8) can be calculated through the curve.
Comparative example 2
In this comparative example: the size of the wafer 100 to be inspected is 300 mm.
Detecting by adopting a traditional transient capacitance detection method, forming a top metal Ni layer on the upper surface of the wafer 100 to be detected, wherein the thickness of the top metal Ni layer is 150nm, and the top metal Ni layer is in Schottky contact with the silicon material; after the lower surface of the wafer 100 to be detected is completely etched, a bottom surface metal AL layer is formed, the thickness of the bottom surface metal AL layer is 150nm, the bottom surface metal AL layer is in ohmic contact with a silicon material, the measurement is carried out by a standard deep level transient capacitance spectrum technology, the applied measurement voltage is 0.2V and 6V respectively, the temperature scanning range during the measurement is 50K-300K, two parameters of 176Hz and 264Hz are used for carrying out measurement for two times, the deep level transient capacitance spectrum curve of the wafer 100 to be detected obtained through the measurement for two times is shown in figure 9, the signal curve is irregular, the curve has great fluctuation, and an Arrhenius curve cannot be obtained through the test curve;
by adopting the detection method for the deep level defect state provided by the embodiment, the top metal layer 300 adopts metal Ni with the thickness of 150nm, and the width of each top electrode 301 is 1 mm; the bottom metal layer 200 is made of metal AL with the thickness of 150nm, the width of the bottom ohmic junction is 0.1mm, and the width of the bottom Schottky junction 202 is 0.1 mm; each top surface schottky junction 301 corresponds to 5 bottom surface ohmic junctions and 5 bottom surface schottky junctions 202, the temperature scanning range during measurement is 50K to 300K, the applied measurement voltage is 0.2V and 6V respectively, two times of measurement are carried out by using two parameters of 176Hz and 264Hz, the deep energy level transient capacitance spectrum curve of the wafer 100 to be detected measured in two times is shown in fig. 10, and even if the test frequency (352Hz) is increased, a regular deep energy level signal curve can be obtained, and an arrhenius curve (shown in fig. 11) can be calculated by using the deep energy level signal curve.
In summary, according to the method for detecting the deep energy level defect state in the large-size wafer, ohmic contact and schottky contact are formed on the bottom surface of the wafer to be detected, schottky contact is formed on the top surface of the wafer to be detected, the top surface schottky junction and the bottom surface schottky junction which are respectively located on the two surfaces form a double schottky diode structure together, and the leakage current of the double schottky diode structure is low, so that the measuring method can measure the defect state of a deeper energy level; the low leakage current also enables the measuring method to measure with higher measuring voltage, and reduces the interference of low-energy-level defect states on measuring results; meanwhile, the measurement temperature range during measurement is widened due to low leakage current, so that the electron excitation probability in the deep-level defect is higher, and more accurate information about the state concentration and the energy level position of the deep-level defect can be obtained. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for detecting deep energy level defect states in a large-size wafer is characterized by comprising the following steps:
providing a wafer to be detected;
etching the bottom surface of the wafer to be detected to form a plurality of etching areas which are not connected with each other, wherein the area, which is not etched, of the bottom surface of the wafer to be detected is divided into a plurality of non-etched areas by the etching areas at intervals, and the surface roughness of the etching areas is larger than that of the non-etched areas;
forming a bottom metal layer on the bottom surface of the wafer to be detected, wherein the bottom metal layer located in the etched region is in ohmic contact with the wafer to be detected, and the bottom metal layer located in the non-etched region is in Schottky contact with the wafer to be detected;
forming a patterned top surface metal layer on the top surface of the wafer to be detected, wherein the top surface metal layer is in Schottky contact with the wafer to be detected;
and measuring the deep energy level transient capacitance spectrum curve of the wafer to be detected, utilizing the deep energy level transient capacitance spectrum curve to draw an Arrhenius curve, and obtaining the energy level position and concentration information of the deep energy level defect of the wafer to be detected.
2. The method as claimed in claim 1, wherein N etched regions and K adjacent unetched regions are defined as a test group, and the bottom metal layers covered by each test group are not connected to each other; wherein N is an integer of 1 or more, and K is an integer of 1 or more.
3. The method as claimed in claim 1 or 2, wherein the etching regions are in the shape of stripes, and the width of each etching region is between 0.01mm and 1 mm.
4. The method as claimed in claim 1, wherein the bottom metal layer in the non-etched region contacts the wafer to be detected to form a bottom schottky junction, the top metal layer contacts the wafer to be detected to form a top schottky junction, and the barrier height of the bottom schottky junction is different from the barrier height of the top schottky junction.
5. The method as claimed in claim 1, wherein the diameter of the wafer to be detected is greater than or equal to 300 mm.
6. The method for detecting the deep level defect state in the large-size wafer according to claim 1, wherein the method for obtaining the energy level position and the concentration information of the deep level defect of the wafer to be detected comprises the following steps:
providing a deep energy level transient spectrum testing device;
setting the test voltage of the deep energy level transient spectrum test device to be smaller than the starting voltage of the top surface Schottky junction of the wafer to be detected, and obtaining a multi-sub-trap deep energy level transient capacitance spectrum curve based on the measurement of the deep energy level transient spectrum test device;
setting the test voltage of the deep energy level transient spectrum test device to be greater than the starting voltage of the top surface Schottky junction of the wafer to be detected, and measuring based on the deep energy level transient spectrum test device to obtain a common deep energy level transient capacitance spectrum curve of the minority carrier trap and the multi-carrier trap;
carrying out envelope analysis on the multi-electron trap deep level transient capacitance spectrum curve, the minority electron trap and the multi-electron trap common deep level transient capacitance spectrum curve to obtain a minority electron trap deep level transient capacitance spectrum curve;
and making an Arrhenius curve by using the multi-electron trap deep energy level transient capacitance spectrum curve and the few-electron trap deep energy level transient capacitance spectrum curve, and obtaining the energy level position and concentration information of the deep energy level defect of the wafer to be detected.
7. The method as claimed in claim 6, wherein the arrhenius curve satisfies the following equation:
in the formula, e n Thermal emissivity of electrons emitted from deep levels, T is temperature, K is constant, σ n To capture the cross-section, E C Is the conduction band energy level, E T Is the defect state energy level, and k is the boltzmann constant.
8. The method for detecting the state of the deep level defect in the large-size wafer according to claim 6, wherein the wafer to be detected is subjected to temperature scanning at different temperatures, and a deep level transient capacitance spectrum curve of the deep level defect along with the temperature distribution is measured; wherein the temperature is between 50K and 500K.
9. The method for detecting the deep level defect state in the large-size wafer according to claim 6, wherein in the step of measuring the common deep level transient capacitance spectrum curve of the minority carrier trap and the majority carrier trap, the test voltage is between 2V and 10V.
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