CN115019849A - Memory and storage device - Google Patents

Memory and storage device Download PDF

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Publication number
CN115019849A
CN115019849A CN202210592393.4A CN202210592393A CN115019849A CN 115019849 A CN115019849 A CN 115019849A CN 202210592393 A CN202210592393 A CN 202210592393A CN 115019849 A CN115019849 A CN 115019849A
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CN
China
Prior art keywords
transistor
electrically connected
word line
terminal
drain
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CN202210592393.4A
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Chinese (zh)
Inventor
郑钟倍
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Priority to CN202210592393.4A priority Critical patent/CN115019849A/en
Publication of CN115019849A publication Critical patent/CN115019849A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

The application discloses memory and storage device, this memory includes the word line, the word line decoder, first power module and power selection module, be global word line sub-decoding portion through first power module, word line voltage drive portion provides mains voltage all the way, power selection module provides another mains voltage for word line voltage drive portion, the independent power supply of two way mains voltage has not only been realized, and another mains voltage that power selection module provided to word line voltage drive portion can realize independent adjustment, can shorten the electric potential change time of word line voltage drive portion output through power selection module, the electric potential change time of word line has also been shortened simultaneously, and then the work efficiency of memory has been improved.

Description

Memory and storage device
Technical Field
The present application relates to the field of storage technologies, and in particular, to a memory and a storage device.
Background
Most memories in the conventional technical scheme are provided with word line decoders and word lines, and the word line decoders can provide different potentials for the corresponding word lines as required to realize corresponding operations. The transition between different potentials provided to the word line by the word line decoder requires a corresponding time to complete, and an excessively long time often affects the operating efficiency of the memory.
Disclosure of Invention
The application provides a memory and a storage device, which are used for solving the technical problem that the jumping time length between different potentials output by a word line decoder is long.
In a first aspect, the present application provides a memory, including a word line, a word line decoder, a first power module, and a power selection module, where the word line decoder includes a global word line sub-decoding portion and a word line voltage driving portion, and the word line voltage driving portion is electrically connected to the global word line sub-decoding portion and the word line; the first power supply module is electrically connected with the global word line sub-decoding part and the word line voltage driving part; the power selection module is electrically connected with the word line voltage driving part and is used for shortening the output potential change time of the word line voltage driving part.
In some embodiments, the power selection module includes a second power module and a voltage selection module, and the voltage selection module is electrically connected to the second power module and the word line potential generator, and is configured to selectively provide different potentials to the word line potential generator.
In some embodiments, the first input terminal of the word line voltage driving portion is electrically connected to the output terminal of the first power module, the second input terminal of the word line voltage driving portion is electrically connected to the output terminal of the second power module, the third input terminal of the word line voltage driving portion is electrically connected to the first low potential terminal, and the fourth input terminal of the word line voltage driving portion is electrically connected to the second low potential terminal; the first control end of the word line voltage driving part is electrically connected with the first output end of the global word line sub-decoding part, and the second control end of the word line voltage driving part is electrically connected with the second output end of the global word line sub-decoding part; the output end of the word line voltage driving part is electrically connected with a word line.
In some embodiments, the word line voltage driving portion includes a first transistor, a second transistor and a third transistor, a substrate of the first transistor is electrically connected to the output terminal of the first power module, one of a source/drain of the first transistor is electrically connected to the output terminal of the voltage selection module, a gate of the first transistor is electrically connected to the first output terminal of the global word line sub-decoding portion, and the first transistor is a P-channel transistor; one of a source/drain of the second transistor is electrically connected with the other of the source/drain of the first transistor and the word line, the other of the source/drain of the second transistor is electrically connected with the first low potential terminal, a gate of the second transistor is electrically connected with a gate of the first transistor, a substrate of the second transistor is electrically connected with the second low potential terminal, and the second transistor is an N-channel transistor; one of a source/drain of the third transistor is electrically connected to one of a source/drain of the first transistor, the other of the source/drain of the third transistor is electrically connected to the other of the source/drain of the first transistor, a gate of the third transistor is electrically connected to the second output terminal of the global word line sub-decoding portion, a substrate of the third transistor is electrically connected to the second low potential terminal, and the third transistor is an N-channel transistor.
In some embodiments, the first input terminal of the global word line sub-decoding portion is electrically connected to the output terminal of the first power module, the second input terminal of the global word line sub-decoding portion is electrically connected to the third low-potential terminal, and the third input terminal of the global word line sub-decoding portion is electrically connected to the second low-potential terminal; the first control end of the global word line sub-decoding part is electrically connected with the fourth potential end, and the second control end of the global word line sub-decoding part is electrically connected with the fifth potential end; the first output end of the global word line sub-decoding part is electrically connected with the first control end of the word line voltage driving part, and the second output end of the global word line sub-decoding part is electrically connected with the second control end of the word line voltage driving part.
In some embodiments, the global word line sub-decoding portion includes a first voltage generating unit, a conduction control unit, and a second voltage generating unit, a first input terminal of the first voltage generating unit is electrically connected to an output terminal of the first power module, a second input terminal of the first voltage generating unit is electrically connected to a third low potential terminal, a third input terminal of the first voltage generating unit is electrically connected to the second low potential terminal, a first control terminal of the first voltage generating unit is electrically connected to a fourth potential terminal, and a second control terminal of the first voltage generating unit is electrically connected to a fifth potential terminal; the first input end of the conduction control unit is electrically connected with the first input end of the first voltage generation unit, the second input end of the conduction control unit is electrically connected with the third input end of the first voltage generation unit, the control end of the conduction control unit is electrically connected with the output end of the first voltage generation unit, and the output end of the conduction control unit is electrically connected with the first control end of the word line voltage driving part; the first input end of the second voltage generation unit is electrically connected with the first input end of the conduction control unit, the second input end of the second voltage generation unit is electrically connected with the second input end of the conduction control unit, the control end of the second voltage generation unit is electrically connected with the output end of the conduction control unit, and the output end of the second voltage generation unit is electrically connected with the second control end of the word line voltage driving portion.
In some embodiments, the first voltage generating unit includes a fourth transistor and a fifth transistor, one of a source/drain of the fourth transistor is electrically connected to the substrate of the fourth transistor and the output terminal of the first power module, a gate of the fourth transistor is electrically connected to the fourth potential terminal, the other of the source/drain of the fourth transistor is electrically connected to the control terminal of the turn-on control unit, and the fourth transistor is a P-channel transistor; one of a source/drain of the fifth transistor is electrically connected to the other of the source/drain of the fourth transistor, the other of the source/drain of the fifth transistor is electrically connected to the third low potential terminal, a substrate of the fifth transistor is electrically connected to the second low potential terminal, a gate of the fifth transistor is electrically connected to the fifth potential terminal, and the fifth transistor is an N-channel transistor.
In some embodiments, the turn-on control unit includes a sixth transistor and a seventh transistor, one of a source/drain of the sixth transistor is electrically connected to the substrate of the sixth transistor and the output terminal of the first power module, a gate of the sixth transistor is electrically connected to the other of the source/drain of the fourth transistor, the other of the source/drain of the sixth transistor is electrically connected to the control terminal of the second voltage generating unit and the first control terminal of the word line voltage driving part, and the sixth transistor is a P-channel transistor; one of a source/drain of the seventh transistor is electrically connected to the other of the source/drain of the sixth transistor, the other of the source/drain of the seventh transistor is electrically connected to the substrate of the seventh transistor and the second low-potential terminal, a gate of the seventh transistor is electrically connected to the gate of the sixth transistor, and the seventh transistor is an N-channel transistor.
In some embodiments, the second voltage generating unit includes an eighth transistor and a ninth transistor, one of a source/drain of the eighth transistor is electrically connected to the substrate of the eighth transistor and the output terminal of the first power module, a gate of the eighth transistor is electrically connected to the other of the source/drain of the sixth transistor, the other of the source/drain of the eighth transistor is electrically connected to the second control terminal of the word line voltage driving portion, and the eighth transistor is a P-channel type transistor; one of a source/drain of the ninth transistor is electrically connected to the other of the source/drain of the eighth transistor, the other of the source/drain of the ninth transistor is electrically connected to the substrate of the ninth transistor and the second low potential terminal, a gate of the ninth transistor is electrically connected to the gate of the eighth transistor, and the ninth transistor is an N-channel transistor.
In some embodiments, the power selection module is configured to output a second voltage signal, where the potential of the second voltage signal includes a verify potential and a programming potential, and the programming potential is higher than the verify potential; the output potential change time is a time required for switching from the verify potential to the program potential or a time required for switching from the program potential to the verify potential.
In some embodiments, the first power module is configured to output a first voltage signal, and the first voltage signal is a constant voltage signal; the potential of the first voltage signal is higher than or equal to the programming potential.
In some embodiments, the second voltage signal output by the power selection module is the same as the output signal of the word line voltage driver and the transmission signal of the word line.
In a second aspect, the present application provides a storage device, which includes the memory in at least one of the above embodiments, where the memory is a serial flash memory.
The application provides a memory and a storage device, be global word line sub-decoding portion through first power module, word line voltage drive portion provides mains voltage all the way, power selection module provides another mains voltage for word line voltage drive portion, the independent power supply of two way mains voltage has not only been realized, and power selection module provides another mains voltage to word line voltage drive portion and can realize independent adjustment, can shorten the electric potential change time of word line voltage drive portion output through power selection module, the electric potential change time of word line has also been shortened simultaneously, and then the work efficiency of memory has been improved.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic diagram of an overall structure of a memory according to an embodiment of the present disclosure.
Fig. 2 is a schematic partial structure diagram of a memory according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a global word line sub-decoding portion according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a word line voltage driving portion according to an embodiment of the present disclosure.
Fig. 5 is a timing diagram of the related signals in fig. 3 and 4.
Fig. 6 is a schematic partial structure diagram of a memory according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of another global word line sub-decoding portion according to an embodiment of the present disclosure.
Fig. 8 is a schematic structural diagram of another word line voltage driving portion according to an embodiment of the present disclosure.
Fig. 9 is a timing diagram of the related signals in fig. 7 and 8.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a schematic diagram illustrating an overall structure of a memory according to an embodiment of the present invention, and the memory device shown in fig. 1 includes a plurality of memory blocks 200, a plurality of local bit line decoders 300, a plurality of word line decoders 100, a plurality of global bit line decoders 400, and other circuits 500.
Fig. 2 is a schematic diagram of a local structure of a memory according to an embodiment of the present invention, wherein each global word line sub-decoding portion, such as a first global word line sub-decoding portion 101 to an nth global word line sub-decoding portion 10N, and a plurality of groups of word line voltage driving portions are disposed in the word line decoder 100 shown in fig. 1, each group of word line voltage driving portions may include a first word line voltage driving portion 201, a second word line voltage driving portion 202 to an M-1 word line voltage driving portion 20M-1, and an mth word line voltage driving portion 20M, an output end of each word line voltage driving portion is correspondingly connected to a word line, for example, output ends of the first word line voltage driving portion 201, the second word line voltage driving portion 202 to the M-1 word line voltage driving portion 20M-1, and the mth word line voltage driving portion 20M are sequentially and correspondingly connected to the first word line to the mth word line, the first to mth word lines are used to transmit corresponding signals WL11, WL12 to WL1M-1 and WL 1M. Each global word line sub-decoding part is connected with a corresponding group of word line voltage driving parts.
Alternatively, the first power module 301 and the voltage selection module 401 may be configured in the word line decoder 100 shown in fig. 1, or in other circuits 500 shown in fig. 1, or in other circuits or modules in the memory as needed.
The first power module 301 is configured to output a voltage signal VPPX1 to each global word line sub-decoding unit, each word line voltage driving unit, and the voltage selection module 401, and each word line voltage driving unit generates corresponding signals WL11, WL12 to WL1M-1, and WL1M according to a signal PWL1 output by the voltage selection module 401.
Fig. 3 is a schematic structural diagram of a global word line sub-decoding portion according to an embodiment of the present disclosure, and fig. 4 is a schematic structural diagram of a word line voltage driving portion according to an embodiment of the present disclosure. Referring to fig. 2 to 4, a global word line sub-decoding section shown in fig. 3 provides a corresponding output signal GWLB and an output signal GWL for a word line voltage driving section shown in fig. 4, the word line voltage driving section generates a series of signals WL1 [ M:1 ] under the control of the output signal GWLB and the output signal GWL, and the series of signals WL1 [ M:1 ] may be at least one of signals WL11, WL12 to WL1M-1, and WL 1M.
However, since the global word line sub-decoding units and the word line voltage driving units share the voltage signal VPPX1 output by the first power supply block 301, the modulation of the voltage signal VPPX1 affects the operating states of the global word line sub-decoding units and the word line voltage driving units at the same time. Therefore, the modulation of the voltage signal VPPX1 becomes difficult, for example, the switching time t1PUMP between the verify potential and the program potential and/or the switching time t1DISQ between the program potential and the verify potential shown in fig. 5 are difficult to be changed, and the switching time t1PUMP and/or the switching time t1DISQ being too long easily affects the operating efficiency of the memory.
In view of the above-mentioned technical problem that the transition time duration between different potentials output by the word line decoder is long, the present embodiment provides a memory, as shown in fig. 6 to 9, the memory includes a word line (not shown), a word line decoder, a first power module 301 and a power selection module 340, the word line decoder includes a global word line sub-decoding portion and a word line voltage driving portion, and the word line voltage driving portion is electrically connected to the global word line sub-decoding portion and the word line; the first power supply module 301 is electrically connected with the global word line sub-decoding part and the word line voltage driving part; the power selection module 340 is electrically connected to the word line voltage driver for shortening the output potential variation time of the word line voltage driver.
It can be understood that, compared with the memory shown in fig. 1 to 4, in the memory provided in this embodiment, the first power module 301 provides one path of power voltage for the global word line sub-decoding portion and the word line voltage driving portion, and the power selection module 340 provides the other path of power voltage for the word line voltage driving portion, which not only realizes independent power supply of the two paths of power voltages, but also realizes independent adjustment of the other path of power voltage provided to the word line voltage driving portion by the power selection module 340, and can shorten the potential change time output by the word line voltage driving portion through the power selection module 340, and also shorten the potential change time of the word line, thereby improving the working efficiency of the memory.
In one embodiment, as shown in fig. 6, the power selection module 340 includes a second power module 302 and a voltage selection module 401, and the voltage selection module 401 is electrically connected to the second power module 302 and the word line potential generator for selectively providing different potentials to the word line potential generator.
It should be noted that, in this embodiment, the newly added second power module 302 is used to separately supply power to the voltage selection module 401, so that the voltage signal VPPX _ PWL output by the second power module 302 can be correspondingly modulated according to needs, for example, the switching time t2PUMP and/or the switching time t2DISQ shown in fig. 9 can be shortened, and further, the potential change time output by the word line voltage driving unit can be shortened.
In one embodiment, as shown in fig. 7 and 8, the first input terminal of the global word line sub-decoding portion is electrically connected to the output terminal of the first power module 301, the second input terminal of the global word line sub-decoding portion is electrically connected to the third low potential terminal, and the third input terminal of the global word line sub-decoding portion is electrically connected to the second low potential terminal; the first control end of the global word line sub-decoding part is electrically connected with the fourth potential end, and the second control end of the global word line sub-decoding part is electrically connected with the fifth potential end; the first output end of the global word line sub-decoding part is electrically connected with the first control end of the word line voltage driving part, and the second output end of the global word line sub-decoding part is electrically connected with the second control end of the word line voltage driving part.
It should be noted that, in one embodiment, the second input terminal of the global word line sub-decoding section and the third input terminal of the global word line sub-decoding section may also be connected to one of the second low potential terminal and the third low potential terminal.
In one embodiment, as shown in fig. 7 and 8, the global word line sub-decoding portion includes a first voltage generating unit 110, a conduction control unit 120, and a second voltage generating unit 130, a first input terminal of the first voltage generating unit 110 is electrically connected to an output terminal of the first power module 301, a second input terminal of the first voltage generating unit 110 is electrically connected to a third low-potential terminal, a third input terminal of the first voltage generating unit 110 is electrically connected to the second low-potential terminal, a first control terminal of the first voltage generating unit 110 is electrically connected to a fourth-potential terminal, and a second control terminal of the first voltage generating unit 110 is electrically connected to a fifth-potential terminal; a first input terminal of the conduction control unit 120 is electrically connected to a first input terminal of the first voltage generation unit 110, a second input terminal of the conduction control unit 120 is electrically connected to a third input terminal of the first voltage generation unit 110, a control terminal of the conduction control unit 120 is electrically connected to an output terminal of the first voltage generation unit 110, and an output terminal of the conduction control unit 120 is electrically connected to a first control terminal of the word line voltage driving part; the first input terminal of the second voltage generating unit 130 is electrically connected to the first input terminal of the conduction control unit 120, the second input terminal of the second voltage generating unit 130 is electrically connected to the second input terminal of the conduction control unit 120, the control terminal of the second voltage generating unit 130 is electrically connected to the output terminal of the conduction control unit 120, and the output terminal of the second voltage generating unit 130 is electrically connected to the second control terminal of the word line voltage driving portion.
It should be noted that the first voltage generating unit 110 is configured to output a signal introduced by the second low potential terminal. The turn-on control unit 120 is used for outputting a signal introduced by a first input terminal of the turn-on control unit 120. The second voltage generating unit 130 is used for outputting a signal introduced by a second input terminal of the second voltage generating unit 130.
In one embodiment, as shown in fig. 7 and 8, the first voltage generating unit 110 includes a fourth transistor P0 and a fifth transistor N0, one of a source/drain of the fourth transistor P0 is electrically connected to the substrate of the fourth transistor P0 and the output terminal of the first power module 301, a gate of the fourth transistor P0 is electrically connected to the fourth potential terminal, the other of the source/drain of the fourth transistor P0 is electrically connected to the control terminal of the turn-on control unit 120, and the fourth transistor P0 is a P-channel transistor; one of a source/drain of the fifth transistor N0 is electrically connected to the other of the source/drain of the fourth transistor P0, the other of the source/drain of the fifth transistor N0 is electrically connected to the third low potential terminal, the substrate of the fifth transistor N0 is electrically connected to the second low potential terminal, the gate of the fifth transistor N0 is electrically connected to the fifth potential terminal, and the fifth transistor N0 is an N-channel transistor.
It should be noted that the second low potential terminal is used for providing a second constant voltage low potential signal VEEX. The third low potential terminal is used for providing a third constant voltage low potential signal XSSEC. The fourth potential terminal is used for providing a fourth potential signal XRSTB. The fifth potential terminal is used for providing a fifth potential signal XPREA.
One operation of the first voltage generating unit 110 is as follows: in this case, the potential at the output terminal of the first voltage generating unit 110, i.e., one of the source and the drain of the fifth transistor N0, is continuously pulled down by the second constant voltage low potential signal VEEX through the fifth transistor N0, that is, the signal output by the first voltage generating unit 110 is the second constant voltage low potential signal VEEX.
In one embodiment, as shown in fig. 7 and 8, the turn-on control unit 120 includes a sixth transistor P1 and a seventh transistor N1, one of the source/drain of the sixth transistor P1 is electrically connected to the substrate of the sixth transistor P1 and the output terminal of the first power module 301, the gate of the sixth transistor P1 is electrically connected to the other of the source/drain of the fourth transistor P0, the other of the source/drain of the sixth transistor P1 is electrically connected to the control terminal of the second voltage generating unit 130 and the first control terminal of the word line voltage driving part, and the sixth transistor P1 is a P-channel transistor; one of a source/drain of the seventh transistor N1 is electrically connected to the other of the source/drain of the sixth transistor P1, the other of the source/drain of the seventh transistor N1 is electrically connected to the substrate of the seventh transistor N1 and the second low potential terminal, the gate of the seventh transistor N1 is electrically connected to the gate of the sixth transistor P1, and the seventh transistor N1 is an N-channel transistor.
It should be noted that one operation of the conduction control unit 120 is as follows: since the first voltage generating unit 110 outputs a low potential signal of a constant voltage, the sixth transistor P1 is in a turned-on state, and the seventh transistor N1 is in a turned-off state, in this case, a signal output from the output terminal of the turn-on control unit 120, i.e., one of the source/drain of the seventh transistor N1, is the output signal VPPX2 of the first power module 301, and the output signal VPPX2 is a high potential signal as shown in fig. 9; that is, the output signal GWLB of the first output terminal of the global word line sub-decoding section is the same as the output signal VPPX 2.
In one embodiment, as shown in fig. 7 and 8, the second voltage generating unit 130 includes an eighth transistor P2 and a ninth transistor N2, one of a source/drain of the eighth transistor P2 is electrically connected to the substrate of the eighth transistor P2 and the output terminal of the first power module 301, a gate of the eighth transistor P2 is electrically connected to the other of the source/drain of the sixth transistor P1, the other of the source/drain of the eighth transistor P2 is electrically connected to the second control terminal of the word line voltage driving part, and the eighth transistor P2 is a P-channel transistor; one of a source/drain of the ninth transistor N2 is electrically connected to the other of the source/drain of the eighth transistor P2, the other of the source/drain of the ninth transistor N2 is electrically connected to the substrate of the ninth transistor N2 and the second low potential terminal, a gate of the ninth transistor N2 is electrically connected to the gate of the eighth transistor P2, and the ninth transistor N2 is an N-channel transistor.
It should be noted that one operation of the second voltage generating unit 130 is as follows: since the turn-on control unit 120 outputs the high potential signal, the ninth transistor N2 is in a turn-on state, and the eighth transistor P2 is in a turn-off state, in which case, a signal output by the output terminal of the second voltage generating unit 130, i.e., one of the source/drain of the ninth transistor N2, is the output signal GWL, i.e., the second constant voltage low potential signal VEEX.
In one embodiment, as shown in fig. 7 and 8, a first input terminal of the word line voltage driver is electrically connected to an output terminal of the first power module 301, a second input terminal of the word line voltage driver is electrically connected to an output terminal of the second power module 302, a third input terminal of the word line voltage driver is electrically connected to the first low potential terminal, and a fourth input terminal of the word line voltage driver is electrically connected to the second low potential terminal; the first control end of the word line voltage driving part is electrically connected with the first output end of the global word line sub-decoding part, and the second control end of the word line voltage driving part is electrically connected with the second output end of the global word line sub-decoding part; the output end of the word line voltage driving part is electrically connected with a word line.
It should be noted that the first low potential terminal is used for providing the first constant voltage low potential signal SVEEX.
In one embodiment, as shown in fig. 7 and 8, the word line voltage driving portion includes a first transistor P3, a second transistor N3 and a third transistor N4, a substrate of the first transistor P3 is electrically connected to the output terminal of the first power module 301, one of a source and a drain of the first transistor P3 is electrically connected to the output terminal of the voltage selection module 401, a gate of the first transistor P3 is electrically connected to the first output terminal of the global word line sub-decoding portion, and the first transistor P3 is a P-channel transistor; one of a source/drain of the second transistor N3 is electrically connected to the other of the source/drain of the first transistor P3 and the word line, the other of the source/drain of the second transistor N3 is electrically connected to the first low potential terminal, a gate of the second transistor N3 is electrically connected to a gate of the first transistor P3, a substrate of the second transistor N3 is electrically connected to the second low potential terminal, and the second transistor N3 is an N-channel type transistor; one of the source/drain of the third transistor N4 is electrically connected to one of the source/drain of the first transistor P3, the other of the source/drain of the third transistor N4 is electrically connected to the other of the source/drain of the first transistor P3, the gate of the third transistor N4 is electrically connected to the second output terminal of the global word line sub-decoding portion, the substrate of the third transistor N4 is electrically connected to the second low potential terminal, and the third transistor N4 is an N-channel type transistor.
The gate of the first transistor P3 and the gate of the second transistor N3 are used as the first control terminal of the word line voltage driver, and the gate of the third transistor N4 is used as the second control terminal of the word line voltage driver. The substrate of the first transistor P3 serves as a first input terminal of the word line voltage driver, and one of the source/drain of the first transistor P3 and one of the source/drain of the third transistor N4 serve as a second input terminal of the word line voltage driver. The other of the source/drain of the first transistor P3, the one of the source/drain of the second transistor N3, and the other of the source/drain of the third transistor N4 serve as output terminals of the word line voltage driver.
As shown in fig. 9, one operation of the word line voltage driver is as follows: since the output signal GWLB is high and the output signal GWL is low, the first transistor P3 and the third transistor N4 are turned on, and the second transistor N3 is turned off, in this case, the signal output by the word line voltage driver is the output signal PWL2 of the power selection block 340.
Here, the series of signals WL2 [ M:1 ] output by the word line voltage driving section may be at least one of the output signals WL21, WL22 to WL2M-1 and WL2M in fig. 6.
In one embodiment, the power selection module 340 is configured to output a voltage signal PWL2, where the potential of the voltage signal PWL2 includes a verify potential and a program potential, and the program potential is higher than the verify potential; the output potential change time of the series signal WL2 [ M:1 ] is the time required for switching from the verify potential to the program potential or the time required for switching from the program potential to the verify potential.
In one embodiment, the first power module 301 is configured to output a voltage signal VPPX2, where the voltage signal VPPX2 is a constant voltage signal, and may be a constant voltage high potential signal; the potential of voltage signal VPPX2 is higher than or equal to the programming potential.
In one embodiment, the voltage signal PWL2 output by the power selection module 340 or the voltage selection module 401 is the same as the output signals WL21, WL22 to WL2M-1, WL2M of the word line voltage driver and the transmission signals of the word line.
As shown in fig. 6 and fig. 9, it should be noted that the switching time between the verify potential and the programming potential can be reduced by configuring the switching time t2PUMP to be less than the switching time t1PUMP and/or the switching time t2DISQ to be less than the switching time t1DISQ, so as to improve the setup time and the release time of the programming potential, and further improve the operating efficiency of the memory. The verification time tVERIFY and the programming time tPROGRAM may be correspondingly modulated according to actual needs, and are not specifically developed here.
The potential of the constant voltage low potential signal may be, but not limited to, 0V, or may be other potentials that can satisfy the requirement. The high potential or the constant voltage high potential may be set according to actual needs, and is not particularly limited herein.
Note that the material used for each transistor is not particularly limited, and any transistor that can achieve the above functions and functions may be considered as an embodiment of the present application. The memory may also be in the form of a chip, in which case the various transistors employed should be able to reside on the chip.
In one embodiment, the present embodiment provides a storage device, which includes the memory in at least one embodiment described above, where the memory is a serial flash memory.
It can be understood that, in the storage device provided in this embodiment, the first power module 301 provides one path of power voltage for the global word line sub-decoding portion and the word line voltage driving portion, and the power selection module 340 provides another path of power voltage for the word line voltage driving portion, which not only realizes independent power supply of two paths of power voltages, but also realizes independent adjustment of the other path of power voltage provided by the power selection module 340 to the word line voltage driving portion, and can shorten the potential change time output by the word line voltage driving portion through the power selection module 340, and also shorten the potential change time of the word line, thereby improving the working efficiency of the memory.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The memory and the storage device provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the above embodiments is only used to help understanding the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (13)

1. A memory, comprising:
a word line;
the word line decoder comprises a global word line sub-decoding part and a word line voltage driving part, and the word line voltage driving part is electrically connected with the global word line sub-decoding part and the word line;
the first power supply module is electrically connected with the global word line sub-decoding part and the word line voltage driving part; and
and the power selection module is electrically connected with the word line voltage driving part and is used for shortening the output potential change time of the word line voltage driving part.
2. The memory of claim 1, wherein the power selection module comprises:
a second power supply module; and
the voltage selection module is electrically connected with the second power supply module and the word line potential generator and is used for selectively providing different potentials to the word line potential generator.
3. The memory according to claim 2, wherein a first input terminal of the word line voltage driver is electrically connected to an output terminal of the first power supply module, a second input terminal of the word line voltage driver is electrically connected to an output terminal of the second power supply module, a third input terminal of the word line voltage driver is electrically connected to a first low potential terminal, and a fourth input terminal of the word line voltage driver is electrically connected to a second low potential terminal;
the first control end of the word line voltage driving part is electrically connected with the first output end of the global word line sub-decoding part, and the second control end of the word line voltage driving part is electrically connected with the second output end of the global word line sub-decoding part;
the output end of the word line voltage driving part is electrically connected with one word line.
4. The memory according to claim 3, wherein the word line voltage driving section includes:
a first transistor, a substrate of which is electrically connected to an output terminal of the first power module, one of a source/drain of which is electrically connected to an output terminal of the voltage selection module, a gate of which is electrically connected to a first output terminal of the global word line sub-decoding portion, and the first transistor is a P-channel transistor;
a second transistor, one of a source/drain of which is electrically connected to the other of the source/drain of the first transistor and the word line, the other of the source/drain of which is electrically connected to the first low potential terminal, a gate of which is electrically connected to a gate of the first transistor, a substrate of which is electrically connected to the second low potential terminal, the second transistor being an N-channel transistor; and
a third transistor, one of a source/drain of the third transistor being electrically connected to one of a source/drain of the first transistor, the other of the source/drain of the third transistor being electrically connected to the other of the source/drain of the first transistor, a gate of the third transistor being electrically connected to the second output terminal of the global word line sub-decoding portion, a substrate of the third transistor being electrically connected to the second low potential terminal, the third transistor being an N-channel transistor.
5. The memory according to claim 1, wherein the first input terminal of the global word line sub-decoding portion is electrically connected to the output terminal of the first power supply module, the second input terminal of the global word line sub-decoding portion is electrically connected to a third low potential terminal, and the third input terminal of the global word line sub-decoding portion is electrically connected to the second low potential terminal;
the first control end of the global word line sub-decoding part is electrically connected with the fourth potential end, and the second control end of the global word line sub-decoding part is electrically connected with the fifth potential end;
the first output end of the global word line sub-decoding part is electrically connected with the first control end of the word line voltage driving part, and the second output end of the global word line sub-decoding part is electrically connected with the second control end of the word line voltage driving part.
6. The memory according to claim 5, wherein the global word line sub-decoding section comprises:
a first voltage generating unit, a first input end of which is electrically connected to an output end of the first power module, a second input end of which is electrically connected to the third low potential end, a third input end of which is electrically connected to the second low potential end, a first control end of which is electrically connected to the fourth potential end, and a second control end of which is electrically connected to the fifth potential end;
a conduction control unit, a first input end of the conduction control unit being electrically connected to a first input end of the first voltage generation unit, a second input end of the conduction control unit being electrically connected to a third input end of the first voltage generation unit, a control end of the conduction control unit being electrically connected to an output end of the first voltage generation unit, and an output end of the conduction control unit being electrically connected to a first control end of the word line voltage driving portion;
the first input end of the second voltage generation unit is electrically connected with the first input end of the conduction control unit, the second input end of the second voltage generation unit is electrically connected with the second input end of the conduction control unit, the control end of the second voltage generation unit is electrically connected with the output end of the conduction control unit, and the output end of the second voltage generation unit is electrically connected with the second control end of the word line voltage driving portion.
7. The memory according to claim 6, wherein the first voltage generation unit includes:
a fourth transistor, one of a source and a drain of the fourth transistor being electrically connected to a substrate of the fourth transistor and an output terminal of the first power module, a gate of the fourth transistor being electrically connected to the fourth potential terminal, the other of the source and the drain of the fourth transistor being electrically connected to the control terminal of the conduction control unit, the fourth transistor being a P-channel transistor; and
a fifth transistor, one of a source/drain of the fifth transistor being electrically connected to the other of the source/drain of the fourth transistor, the other of the source/drain of the fifth transistor being electrically connected to the third terminal of low potential, a substrate of the fifth transistor being electrically connected to the second terminal of low potential, a gate of the fifth transistor being electrically connected to the fifth terminal of low potential, the fifth transistor being an N-channel transistor.
8. The memory according to claim 7, wherein the conduction control unit comprises:
a sixth transistor, one of a source and a drain of the sixth transistor being electrically connected to the substrate of the sixth transistor and the output terminal of the first power module, a gate of the sixth transistor being electrically connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor being electrically connected to the control terminal of the second voltage generation unit and the first control terminal of the word line voltage driving unit, the sixth transistor being a P-channel transistor; and
a seventh transistor, one of a source/drain of the seventh transistor being electrically connected to the other of the source/drain of the sixth transistor, the other of the source/drain of the seventh transistor being electrically connected to the substrate of the seventh transistor and the second low potential terminal, a gate of the seventh transistor being electrically connected to the gate of the sixth transistor, the seventh transistor being an N-channel transistor.
9. The memory according to claim 8, wherein the second voltage generation unit comprises:
an eighth transistor, one of a source and a drain of the eighth transistor being electrically connected to the substrate of the eighth transistor and the output terminal of the first power module, a gate of the eighth transistor being electrically connected to the other of the source and the drain of the sixth transistor, the other of the source and the drain of the eighth transistor being electrically connected to the second control terminal of the word line voltage driving part, the eighth transistor being a P-channel transistor; and
a ninth transistor, one of a source/drain of the ninth transistor is electrically connected to the other of the source/drain of the eighth transistor, the other of the source/drain of the ninth transistor is electrically connected to the substrate of the ninth transistor and the second low potential terminal, a gate of the ninth transistor is electrically connected to the gate of the eighth transistor, and the ninth transistor is an N-channel transistor.
10. The memory according to any one of claims 1 to 9, wherein the power selection module is configured to output a second voltage signal, the potential of the second voltage signal includes a verify potential and a programming potential, and the programming potential is higher than the verify potential; the output potential change time is a time required to switch from the verify potential to the program potential or a time required to switch from the program potential to the verify potential.
11. The memory of claim 10, wherein the first power module is configured to output a first voltage signal, and wherein the first voltage signal is a constant voltage signal; the potential of the first voltage signal is higher than or equal to the programming potential.
12. The memory according to claim 10, wherein the second voltage signal outputted from the power selection block is the same as the output signal of the word line voltage driver and the transmission signal of the word line.
13. A memory device comprising the memory according to any one of claims 1 to 12, wherein the memory is a serial flash memory.
CN202210592393.4A 2022-05-27 2022-05-27 Memory and storage device Pending CN115019849A (en)

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CN202210592393.4A CN115019849A (en) 2022-05-27 2022-05-27 Memory and storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210592393.4A CN115019849A (en) 2022-05-27 2022-05-27 Memory and storage device

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