CN115016161A

CN115016161A - Display panel and display mother board

Info

Publication number: CN115016161A
Application number: CN202210724796.XA
Authority: CN
Inventors: 凌维声
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2022-06-23
Filing date: 2022-06-23
Publication date: 2022-09-06
Anticipated expiration: 2042-06-23
Also published as: CN115016161B

Abstract

The application discloses a display panel and a display mother board, wherein the display panel is provided with a display area, and a frame glue area and a peripheral area which are sequentially arranged on the periphery of the display area; the display panel comprises a first substrate, a second substrate, a switching layer and conductive adhesive, wherein the switching layer and the conductive adhesive are positioned between the first substrate and the second substrate; the first substrate comprises a first substrate, and a common electrode line and an insulating layer which are sequentially arranged on the first substrate; the second substrate includes a second substrate and a common electrode; the transfer layer is positioned on the insulating layer and comprises a first transfer part positioned in the frame rubber area and a second transfer part extending from at least part of the first transfer part to the peripheral area; the first switching part penetrates through the insulating layer and is electrically connected with the common electrode wire; the distance between the switching layer on the insulating layer and the common electrode is equal to a preset value; the conductive adhesive is arranged on the first switching part in a dotted manner and is in contact with the common electrode, or the conductive adhesive is arranged on the second switching part in a linear manner and is in contact with the common electrode. The method and the device can improve the productivity and the quality of the display panel.

Description

Display panel and display mother board

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display mother board.

Background

In a Liquid Crystal Display (LCD) of va (vertical alignment) technology, a vertical electric field formed between a color film substrate and an array substrate causes Liquid crystals to rotate, so that the Liquid crystals form different deflection angles, and the upper polarizer transmits light of different intensities. In the process of electric field loading, an electric field on the color filter substrate guides signals from the array substrate to the color filter substrate through a Transfer Pad (Transfer Pad).

The Transfer Pad is usually designed in the frame glue area of the panel, for example, a transparent electrode layer is laid on the common electrode wire exposed in the frame glue area to form the Transfer Pad. In the actual working process of the panel, a common electrode signal connected to the common electrode line is transmitted to the common electrode of the color film substrate in the transfer Pad area through gold balls (Au) arranged on the transparent electrode layer.

In the existing product, Au is positioned on a transfer pad at a fixed position in an Au dotting (dot) mode. With the increasing generation lines and the increasing sizes of LCD products, the number of Au dots to be coated on a single substrate increases, the yield of the whole ODF (One Drop Filling) segment is affected by the conventional Au dot printing process, and the quality risk of the printed dots miss exists.

Disclosure of Invention

The application provides a display panel and a display mother board, which can be compatible with a dotting process and a linear coating process when conductive adhesive is formed, and are beneficial to improving the productivity and the quality of the display panel.

The application provides a display panel, which is provided with a display area, a frame rubber area arranged around the display area, and a peripheral area positioned on one side of the frame rubber area far away from the display area; the display panel comprises a first substrate, a second substrate, a switching layer and conductive adhesive, wherein the first substrate and the second substrate are oppositely arranged, and the switching layer and the conductive adhesive are positioned between the first substrate and the second substrate;

the first substrate comprises a first substrate at least positioned in the frame rubber area and the peripheral area, and a common electrode wire and an insulating layer which are sequentially positioned on the first substrate; the second substrate comprises a second substrate at least positioned in the frame rubber area and the peripheral area and a common electrode positioned on one side of the second substrate close to the insulating layer; the transfer layer is positioned on the insulating layer and comprises a first transfer part positioned in the frame rubber area and a second transfer part extending from at least part of the first transfer part to the peripheral area; the first switching part penetrates through the insulating layer and is electrically connected with the common electrode wire;

the distance between the switching layer positioned on the insulating layer and the common electrode is equal to a preset value; the conductive adhesive is arranged on the first switching part in a dotted manner and is in contact with the common electrode, or the conductive adhesive is arranged on the second switching part in a linear manner and is in contact with the common electrode.

Optionally, the display panel further includes a plurality of first through holes and a plurality of second through holes located in the frame rubber region and penetrating through the insulating layer; the first switching part comprises a plurality of first sub-switching parts which correspond to the first through holes one by one and are arranged at intervals, and a second sub-switching part which covers the second through holes and is arranged at intervals with the first sub-switching parts;

the second sub-switching parts are positioned on one sides of the first sub-switching parts, which are far away from the display area; the second adapter portion extends from the second sub-adapter portion to the peripheral region.

Optionally, the second sub-switching part comprises at least one feedback signal switching part and a common voltage signal switching part;

the feedback signal transfer part and the common voltage signal transfer part are arranged at intervals, and the second transfer part extending from the feedback signal transfer part to the peripheral area and the second transfer part extending from the common voltage signal transfer part to the peripheral area are arranged at intervals.

Optionally, the first substrate further includes a plurality of binding units located in the peripheral region; at least part of the second switching parts are positioned between the frame glue and the plurality of binding units;

the second switching parts positioned between the frame glue and the binding units are distributed in a multi-section mode and are arranged in a staggered mode with the binding units.

Optionally, the insulating layer includes at least a gate insulating layer, a passivation layer, and an organic planarization layer sequentially disposed on the first substrate.

Optionally, the material of the conductive paste comprises gold balls; the material of the switching layer comprises indium tin oxide.

Optionally, the display panel further includes a retaining wall located in the peripheral region and disposed around the sealant; the second switching portion is located the frame glue with between the barricade.

The application also provides a display mother board which is provided with a plurality of panel areas arranged at intervals and areas to be cut, wherein the areas to be cut are arranged adjacent to each panel area; the display motherboard comprises the display panel in the panel area, a plurality of switching gaskets in the area to be cut, and the conductive adhesive on the switching gaskets;

the first substrate, the common electrode line, the insulating layer, the second substrate and the common electrode further extend to the region to be cut; the display mother board also comprises a plurality of third through holes which penetrate through the insulating layer and are arranged in one-to-one correspondence with the plurality of switching gaskets; each of the landing pads includes a first pad part located in the corresponding third via hole and electrically connected to the common electrode line and a second pad part extending from the first pad part onto the insulating layer;

the distance between the transfer pad on the insulating layer and the common electrode is equal to the preset value; the conductive adhesive is disposed in a dotted manner in the first pad portion and is in contact with the common electrode, or the conductive adhesive is disposed in a linear manner in the second pad portion and is in contact with the common electrode.

Optionally, the plurality of panel regions are distributed in an array; the plurality of adapter pads comprise a plurality of alignment electrification adapter pad groups which are arranged in one-to-one correspondence with the plurality of panel areas;

each alignment electrification switching gasket group comprises alignment electrification switching gaskets which are respectively positioned at two opposite sides of the corresponding panel area; the alignment powered landing pads in the plurality of sets of alignment powered landing pads are distributed in an array.

Optionally, the plurality of landing pads further comprises a plurality of balanced voltage landing pads disposed near an edge of the display motherboard and spaced apart from the aligned powered landing pads; the plurality of balanced voltage transfer pads are arranged in one-to-one correspondence with a part of the panel areas among the plurality of panel areas.

According to the display panel and the display mother board, the insulating layer is arranged in the frame rubber area and the peripheral area, so that the distance between the switching layer located on the insulating layer and the common electrode is equal to a preset value, the switching layer extends from the frame rubber area to the peripheral area, and a first switching part located in the frame rubber area and a second switching part located in the peripheral area are formed, so that conductive adhesive used for conducting a common electrode wire in the first substrate and the common electrode in the second substrate can be formed on the first switching part by adopting a dotting process and can also be formed on the second switching part by adopting a linear coating process, and the selectivity of a production process is increased; and, form the second switching portion that is used for coating threadiness conducting resin in peripheral region, be favorable to improving the coating speed of frame gum and the coating speed of conducting resin on the one hand to be favorable to improving display panel's productivity, on the other hand can avoid the error of dotting, thereby be favorable to improving display panel's quality, on the other hand can guarantee that first base plate and second base plate pressfitting are normal, thereby avoid the display panel periphery to appear mura.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of the distribution of transfer pads of a prior art LCD panel.

Fig. 2 is a schematic cross-sectional view of a part of a prior art lcd panel.

Fig. 3 is a schematic distribution diagram of an interposer layer of a display panel according to an embodiment of the present disclosure.

Fig. 4 is a partially enlarged view of the area a in fig. 3.

Fig. 5 is a schematic partial cross-sectional structure diagram of a display panel according to an embodiment of the present disclosure.

Fig. 6 is a schematic partial cross-sectional structure diagram of a frame glue region and a peripheral region in a display panel according to an embodiment of the present disclosure.

Fig. 7 is a schematic distribution diagram of landing pads of a display motherboard according to an embodiment of the present disclosure.

Fig. 8 is a schematic cross-sectional view illustrating a region where landing pads of a motherboard are located according to an embodiment of the present disclosure.

Fig. 9 is a top view of an aligned powered landing pad according to an embodiment of the present application.

Fig. 10 is a top view of a balanced voltage transfer pad according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the application. To simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.

As shown in fig. 1, in a VA or HVA mode liquid crystal display panel 1, a conductive paste of gold ball material is generally positioned on a transfer pad 2 at a fixed position by an Au dot process to conduct a common electrode line in an array substrate and a common electrode in a color filter substrate, thereby controlling liquid crystal deflection. However, as the generation line is larger and larger, the size of the product is larger and larger, and more Au dots need to be arranged on the monolithic substrate (for example, the number of the dots needed for the product G1165 UD is 26), the efficiency of the dot printing process is too low, which affects the productivity of the whole ODF section; also, part of the transfer pad is used to deliver feedback signals, which must be turned on to balance the large size crosstalk problem; however, the miss may cause the feedback signal not to be transmitted normally, resulting in a risk of product quality.

In order to avoid the low ODF productivity and product quality risk caused by the Au dotting process, a linear gold ball conductive adhesive may be coated on each of the two rows of transfer pads 2 shown in fig. 1 by the Au line coating process. As can be appreciated, the Au line coating process allows for a substantial reduction in coating time and a substantial reduction in Au miss risk. However, the current Au line coating process has the problem that the particle size of the gold ball is not properly selected due to the conventional panel structure.

Taking a COA (Color-Film on Array) type liquid crystal display panel as an example, as shown in fig. 1 and fig. 2, a PFA (polymer Film on Array) layer 3 in the liquid crystal display panel 1 extends from a display region 4 to a sealant region 5, a transparent electrode layer 6 in a transfer pad region is directly connected to a lower common electrode line 8 through a through hole 7, and the transparent electrode layer 6 partially extends onto the PFA layer 3. When gold balls with a larger particle size (for example, AU-2 with a particle size of D2 in fig. 2) are selected to be coated to satisfy the conduction between the common electrode line 8 in the array substrate 9 and the common electrode 11 in the counter substrate 10, the difference between the transparent electrode layer 6 on the PFA layer 3 and the transparent electrode layer 6 in the through hole 7 is larger due to the thickness of the PFA layer 3 being about 1.3um, so that the transparent electrode layer 6 on the PFA layer 3 cannot be normally laminated, and mura (display unevenness) occurs around the panel. When the gold ball with smaller particle size (for example, AU-1 with particle size D1 in fig. 2) is selected for coating so that the in-plane normal pressure can be achieved, the particle size of the gold ball to be arranged on the transfer pad including LOC (laser Patterning on cf) pad and LOC bridging pad out-of-plane is equal to the particle size D2 of AU-2, which results in poor contact between the upper and lower plates after lamination, thereby resulting in abnormal alignment due to the failure of normal conduction between the upper and lower plates during alignment.

The upper and lower plates refer to an array substrate and an opposite substrate (or a color filter substrate); in-plane refers to the chip area on the large board (mother board), i.e. the panel area; the out-of-plane refers to a Dummy area in the large plate, namely an area to be cut; cutting the large plate to form a plurality of small chips, namely forming a plurality of display panels; the transfer pad is arranged in the plane and used for conducting the upper plate and the lower plate to play a lightening role; LOC pad and bridge pad are arranged out of plane, LOC pad is used for conducting electrification alignment in HVA technology, and LOC bridge pad is used for balancing whole board voltage in HVA electrification process. It can be understood that Au glue needs to be coated on the transfer pad, the LOC pad and the LOC bridging pad to realize conduction between the upper plate and the lower plate, and specifically, conduction between the common electrode line in the array substrate and the common electrode in the color film substrate is realized.

In order to solve the technical problem, the embodiment of the application provides a display panel and a display mother board, and two process modes of Au dot and Au line can be compatible in the manufacturing process of the display panel by modifying the film layer structures of the inner frame glue area and the outer area to be cut, so that the production capacity can be improved and the product quality can be improved. Reference will be made in detail to the following description of several embodiments.

Referring to fig. 3 to 6, an embodiment of the present disclosure provides a display panel 20. As shown in fig. 3 and 4, the display panel 20 has a display area 21, a sealant area 22 disposed around the display area 21, and a peripheral area 23 located on a side of the sealant area 22 away from the display area 21. As shown in fig. 5 and 6, the display panel 20 includes a first substrate 24 and a second substrate 25 disposed opposite to each other, and a liquid crystal layer 26, a sealant 27, an adaptor layer 28 and a conductive adhesive 29 disposed between the first substrate 24 and the second substrate 25; the liquid crystal layer 26 is positioned in the display area 21; the frame glue 27 is positioned in the frame glue area 22; the first substrate 24 comprises a first substrate 30 at least positioned in the frame glue area 22 and the peripheral area 23, and a common electrode line 31 and an insulating layer 32 which are sequentially positioned on the first substrate 30; the second substrate 25 comprises a second substrate 33 at least positioned in the frame glue area 22 and the peripheral area 23, and a common electrode 34 positioned on one side of the second substrate 33 close to the insulating layer 32; the transfer layer 28 is located on the insulating layer 32 and includes a first transfer portion 35 located in the frame adhesive region 22 and a second transfer portion 36 extending from at least a portion of the first transfer portion 35 to the peripheral region 23; the first junction 35 penetrates the insulating layer 32 and is electrically connected to the common electrode line 31; the spacing between the interposer layer 28 on the insulating layer 32 and the common electrode 34 is equal to a preset value; the conductive paste 29 is provided in a dot shape on the first transfer portion 35 and is in contact with the common electrode 34, or the conductive paste 29 is provided in a line shape on the second transfer portion 36 and is in contact with the common electrode 34.

It should be noted that fig. 5 and 6 in the present application only show that the conductive paste 29 is linearly disposed on the second transition portion 36, but the present invention is not limited thereto, and the conductive paste 29 may be disposed on the first transition portion 35 in a dot shape.

Specifically, the first substrate 24 is an array substrate, and the second substrate 25 is an opposite substrate; the material of the first substrate 30 and the second substrate 33 includes glass, but is not limited thereto.

Specifically, the material of the conductive paste 29 includes gold balls (Au); the material of the interposer layer 28 includes, but is not limited to, Indium Tin Oxide (ITO).

It can be understood that the conductive paste 29 may be formed on the first transfer portion 35 by a dotting process, and may also be formed on the second transfer portion 36 by a line-shaped coating process, that is, the display panel 20 provided in the embodiment of the present application may be compatible with two process manners, namely, Au dot (Au dotting) and Au line (Au line-shaped coating), so that the selectivity of the production process is increased, and the production efficiency is improved. Specifically, when the dotting process is selected to form the dot-shaped conductive paste 29 on the first junction 35, the particle size of the gold ball may be selected from the particle size D2 of AU-2 shown in fig. 2; when the linear conductive paste 29 is formed on the second transfer portion 36 by a linear coating process, the particle size of the gold ball may be selected from the particle size D1 (i.e., a predetermined value) of AU-1 in fig. 2.

Specifically, the distance between the via layer 28 and the common electrode 34 on the insulating layer 32 is equal to a predetermined value, wherein the predetermined value is the size of the gold ball in the conductive paste 29, for example, the predetermined value is the particle size D1 of AU-1 shown in fig. 2.

It can be understood that the second interposer 36 of the present application is a flat transparent electrode layer, that is, the height of the second interposer 36 is the same everywhere, and after the gold ball with the particle size of the preset value D1 is selected, the linear conductive adhesive 29 is coated on the second interposer 36 to ensure that the pressing of the peripheries of the first substrate 24 and the second substrate 25 is normal, thereby avoiding the peripheral mura problem of the display panel 20.

Specifically, the frame rubber region 22 and the peripheral region 23 constitute a non-display region; the first substrate 30, the insulating layer 32, the second substrate 33, and the common electrode 34 are also provided in the display region 21; the common electrode line 31 may be disposed only in the non-display region, or may be disposed in the display region 21 and the non-display region, and the application is not limited thereto.

Specifically, the common electrode line 31 in the sealant region 22 may be in a grid shape, which is beneficial to increase the transmittance of UV (ultraviolet) when the sealant 27 is cured, and improve the curing effect.

Specifically, as shown in fig. 6, the insulating layer 32 located in the non-display region includes at least a gate insulating layer (GI)37, a passivation layer (PV)38, and an organic planarization layer (e.g., PFA)39 sequentially disposed on the first substrate 30.

It is understood that in the embodiment of the present application, the film structure under the via layer 28 is kept consistent except for the portion of the via layer 28 that penetrates through the insulating layer 32, so that the spacing between the via layer 28 on the insulating layer 32 and the common electrode 34 is constant (for example, the predetermined value D1), which is beneficial to normal pressing of different positions of the via layer 28.

In one embodiment, the display panel 20 further includes a plurality of through holes located in the sealant region 22 and penetrating through the insulating layer 32, and the first transition portion 35 covers the plurality of through holes and directly contacts the common electrode lines 31 therebelow through the plurality of through holes; wherein, first switching portion 35 can be the transfer pad in the present panel structure, and this application can be on the basis of present panel structure, and the transparent electrode layer that will form the transfer pad sets up in succession and extends to peripheral district 23 from frame gum district 22, forms the gold ball coating region that is located peripheral district 23 for the gold ball coating is not influenced by frame gum 27, and can avoid the unusual problem of local pressfitting.

In another embodiment, as shown in fig. 3 and 4, the display panel 20 further includes a plurality of first through holes 40 and a plurality of second through holes 41 located in the sealant region 22 and penetrating the insulating layer 32; the first transfer part 35 includes a plurality of first sub-transfer parts 43 corresponding to the plurality of first through holes 40 one by one and arranged at intervals, and a second sub-transfer part 44 covering the plurality of second through holes 41 and arranged at intervals with the first sub-transfer parts 43; the second sub-adapter 44 is located on a side of the plurality of first sub-adapters 43 away from the display area 21; the second transition portion 36 extends from the second sub-transition portion 44 to the peripheral region 23.

Specifically, the shapes and sizes of the orthographic projections of the first through hole 40 and the second through hole 41 may be the same, or may be different from each other, and are not limited herein. It can be understood that when the first through hole 40 and the second through hole 41 are formed in the same process, the shape and size of the orthographic projection of the two holes are consistent, which is beneficial to improving the production efficiency.

As can be understood, the first sub-via 43 directly contacts the underlying common electrode line 31 through the first through hole 40, and the edge of the first sub-via 43 further extends onto the insulating layer 32, so that the first via 35 is formed on the sidewall and the bottom of the first through hole 40; the second sub-via 44 directly contacts the common electrode line 31 below through the second through hole 41.

It should be noted that the first sub-adapter 43 may be a transfer pad in an existing panel structure, and the second sub-adapter 44 may be a transfer pad added newly. For example, on the basis of the conventional transfer pad, a second through hole 41 is formed by drilling on the insulating layer 32 located in the frame glue region 22, a second sub-interposer 44 electrically connected to the common electrode line 31 is formed in the second through hole 41, the second sub-interposer 44 is extended to the peripheral region 23, a gold ball coating region located in the peripheral region 23 is formed, and the original Au dotting position is remained.

Specifically, as shown in fig. 3, the second sub-switching section 44 includes at least one feedback (feedback) signal switching section 45 and a common voltage (COM) signal switching section 46; the feedback signal transfer part 45 is disposed at an interval from the common voltage signal transfer part 46, and the second transfer part 36 extending from the feedback signal transfer part 45 to the peripheral area 23 is disposed at an interval from the second transfer part 36 extending from the common voltage signal transfer part 46 to the peripheral area 23. This setting can avoid public voltage signal switching portion to appear Au miss and influence the normal transmission of feedback signal, has guaranteed that the feedback function is normal.

Specifically, as shown in fig. 3, the first substrate 24 further includes a plurality of bonding units 47 located in the peripheral region 23, for example, the bonding unit 47 located on the source side of the first substrate 24; at least part of the second transferring parts 36 are located between the frame glue (frame glue region 22) and the plurality of binding units 47; the second switching portions 36 located between the sealant and the plurality of binding units 47 are distributed in a multi-section manner and are staggered with the binding units 47. This setting can avoid second switching portion 36 to be connected with binding unit 47 electricity, guarantees that different signal of telecommunication transmission is normal and stable.

In one embodiment, as shown in FIG. 3, the first substrate 24 includes oppositely disposed first and

second sides

48, 49; a portion of transfer layer 28 is disposed proximate first side 48 and another portion is disposed proximate second side 49; the binding unit 47 is arranged close to the first side 48; the second switching portions 36 of the switching layer 28 disposed near the first side 48 are disposed between the sealant (sealant region 22) and the plurality of binding units 47, and are distributed in a multi-segment manner, and are staggered with the binding units 47; the feedback signal transition 45 and the common voltage signal transition 46 are disposed proximate the second side 49.

Specifically, as shown in fig. 4 and 5, the display panel 20 further includes a retaining wall 50 located in the peripheral region 23 and surrounding the sealant 27; the second transfer portion 36 is located between the frame glue (frame glue region 22) and the retaining wall 50. Certainly, another retaining wall 50' surrounding the display area 21 can be disposed between the display area 21 and the sealant area 22 to prevent the liquid crystal from contacting the sealant 27.

Specifically, the first substrate 24 located in the display area 21 includes a first substrate 30, and a thin film transistor layer, a color resist layer, and an organic planarization layer (e.g., PFA) sequentially disposed on the first substrate 30; wherein the gate insulating layer 32 and the passivation layer extend from the thin film transistor layer to the non-display region. The second substrate 25 further includes a light-shielding layer (e.g., BM)51 between the common electrode 34 and the second substrate 33. It is understood that the display panel 20 in the embodiment of the present application is a COA type liquid crystal display panel, but is not limited thereto, and may also be a liquid crystal display panel in which a color resist layer is disposed on a second substrate.

In the embodiment of the present application, the insulating layer 32 is disposed in the frame adhesive region 22 and the peripheral region 23, such that a distance between the adapting layer 28 and the common electrode 34 on the insulating layer 32 is equal to a preset value, and the adapting layer 28 extends from the frame adhesive region 22 to the peripheral region 23 to form a first adapting portion 35 located in the frame adhesive region 22 and a second adapting portion 36 located in the peripheral region 23, such that the conductive adhesive 29 for conducting the common electrode line 31 in the first substrate 24 and the common electrode 34 in the second substrate 25 may be formed on the first adapting portion 35 by using a dotting process, or may be formed on the second adapting portion 36 by using a linear coating process, such that the selectivity of the production process is increased; moreover, the second adapting portion 36 for coating the linear conductive adhesive 29 is formed in the peripheral area 23, which is beneficial to improving the coating speed of the sealant 27 and the coating speed of the conductive adhesive 29, so as to improve the productivity of the display panel 20, and can avoid dotting errors, so as to improve the quality of the display panel 20, and can ensure that the first substrate 24 and the second substrate 25 are normally laminated, so as to avoid mura around the display panel 20.

As shown in fig. 7 and 8, the present embodiment also provides a display mother board 60, where the display mother board 60 has a plurality of panel regions 61 arranged at intervals and a region to be cut 62 arranged adjacent to each panel region 61; the display motherboard 60 includes a display panel as described in the previous embodiment in a panel area 61, a plurality of landing pads 63 in an area to be cut 62, and conductive paste 29 on the plurality of landing pads 63; the first substrate 30, the common electrode line 31, the insulating layer 32, the second substrate 33, and the common electrode 34 also extend to the region to be cut 62; the display motherboard 60 further includes a plurality of third through holes 64 penetrating the insulating layer 32 and disposed in one-to-one correspondence with the plurality of adapter pads 63; each relay pad 63 includes a first pad portion 65 located in the corresponding third via hole 64 and electrically connected to the common electrode line 31 and a second pad portion 66 extending from the first pad portion 65 onto the insulating layer 32; the spacing between the landing pad 63 on the insulating layer 32 and the common electrode 34 is equal to a preset value D1; the conductive paste 29 is disposed in a dot shape in the first pad portion 65 and contacts the common electrode 34, or the conductive paste 29 is disposed in a line shape in the second pad portion 66 and contacts the common electrode 34.

It should be noted that fig. 8 in the present application only shows that the conductive paste 29 is disposed on the second pad portion 66 in a linear shape, but the present application is not limited thereto, and the conductive paste 29 may be disposed on the first pad portion 65 in a dot shape. Fig. 3 to 6 may be referred to with respect to the structure of the display panel 20.

Specifically, a dotting process may be selected to form the dot-shaped conductive paste 29 on the first transition portion 35 located in the panel region 61 and the first pad portion 65 located in the region to be cut 62, or a linear coating process may be selected to form the linear conductive paste 29 on the second transition portion 36 located in the panel region 61 and the second pad portion 66 located in the region to be cut 62, respectively.

It should be noted that panel area 61 may be referred to as in-plane and area to be cut 62 may be referred to as out-of-plane or Dummy area. In the embodiment of the present application, the switching pad 63 located in the area to be cut 62 needs to be conducted with the common electrode line 31 in the first substrate 24 and the common electrode 34 in the second substrate 25 by disposing the conductive adhesive 29, as in the switching layer 28 located in the panel area 61; the insulating layer 32 is extended from the panel area 61 to the area to be cut 62, so that the insulating layer 32 is also arranged below the switching gasket 63, the film layer structure of the area where the switching gasket 63 is located in the area to be cut 62 is the same as that of the area where the switching layer 28 is located in the panel area 61, the distances between the switching gasket 63 located on the insulating layer 32 and the switching layer 28 and the common electrode 34 are the same preset value D1, and when the conductive adhesive 29 of the area to be cut 62 and the conductive adhesive 29 of the panel area 61 are formed by the same process, the problem of poor contact of the outer upper plate and the lower plate after lamination caused by improper selection of the grain diameter of the gold balls is avoided.

It will be appreciated that the area 62 to be cut on the display motherboard 60 is cut to form a plurality of display panels 20 as described in the previous embodiments.

In a specific embodiment, the shape and size of the projection of the second pad portion 66 in the direction perpendicular to the display mother board 60 are equal to the shape and size of the projection of the first pad portion 65 in the direction perpendicular to the display mother board 60. This arrangement is advantageous for the machine station to quickly identify the second pad portion 66 when the linear coating process is employed, and does not excessively increase the area occupied by the adapter pad 63. Of course, the size of the second pad portion 66 is not limited in the present application as long as the machine can be identified.

Specifically, as shown in fig. 7 and 9, a plurality of panel regions 61 are distributed in an array; the plurality of interposer pads 63 include a plurality of aligned electrical interposer pad sets 67 disposed in one-to-one correspondence with the plurality of panel regions 61; each alignment energization via pad set 67 includes alignment energization via pads 68, such as LOC pads, respectively located at opposite sides of the corresponding panel region 61; the aligned electrical landing pads 68 in the plurality of aligned electrical landing pad sets 67 are distributed in an array.

Specifically, the alignment electrical connection pads 68 in the plurality of alignment electrical connection pad sets 67 are disposed in a plurality of rows, and each row of the alignment electrical connection pads 68 may be coated with a conductive adhesive 29.

Specifically, as shown in fig. 7 and 10, the plurality of via pads 63 further includes a plurality of balanced voltage via pads (e.g., LOC bridge pads) 69 disposed near the edge of the display mother board 60 and spaced apart from the aligned electrically-powered via pads 68; the plurality of balanced voltage transfer pads 69 are disposed in one-to-one correspondence with the partial panel regions 61 among the plurality of panel regions 61. The plurality of balanced voltage pads 69 located on the same side of the panel region 61 are arranged along the same direction, so that the conductive paste 29 can be formed by a linear coating process for the plurality of balanced voltage pads 69.

It should be noted that the protection scope of the embodiments of the present application is not limited to the transfer pad, the LOC pad, and the LOC bridging pad, and the protection scope of the present application is applicable to any position where the common electrode line 31 and the common electrode 34 need to be connected by providing the conductive paste.

In the embodiment of the present application, the insulating layer 32 is extended from the panel region 61 to the region to be cut 62, so that the insulating layer 32 is disposed below the switching pad 63, and thus the region where the switching pad 63 located in the region to be cut 62 is located is the same as the film structure of the region where the switching layer 28 located in the panel region 61 is located, so that the distances between the switching pad 63 located on the insulating layer 32 and the switching layer 28 and the common electrode 34 are the same preset value; when the conductive adhesive 29 of the area to be cut 62 and the conductive adhesive 29 of the panel area 61 are formed by the same process, the problem of poor contact between the upper and lower plates after lamination due to improper selection of the particle size of the gold ball is avoided, and normal alignment can be ensured, so that the product quality is improved.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The display panel and the display motherboard provided by the embodiment of the present application are described in detail above, and a specific example is applied in the description to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display panel is characterized by comprising a display area, a frame rubber area arranged around the display area, and a peripheral area positioned on one side of the frame rubber area far away from the display area; the display panel comprises a first substrate, a second substrate, a switching layer and conductive adhesive, wherein the first substrate and the second substrate are oppositely arranged, and the switching layer and the conductive adhesive are positioned between the first substrate and the second substrate;

2. The display panel according to claim 1, further comprising a plurality of first through holes and a plurality of second through holes located in the sealant region and penetrating the insulating layer; the first switching part comprises a plurality of first sub-switching parts which correspond to the first through holes one by one and are arranged at intervals, and a second sub-switching part which covers the second through holes and is arranged at intervals with the first sub-switching parts;

3. The display panel according to claim 2, wherein the second sub-switching part comprises at least one feedback signal switching part and one common voltage signal switching part;

4. The display panel according to claim 2, wherein the first substrate further comprises a plurality of binding units located in the peripheral region; at least part of the second switching part is positioned between the frame glue and the plurality of binding units;

5. The display panel according to claim 1, wherein the insulating layer comprises at least a gate insulating layer, a passivation layer, and an organic planarization layer sequentially disposed on the first substrate.

6. The display panel according to claim 1, wherein the material of the conductive paste comprises gold balls; the material of the switching layer comprises indium tin oxide.

7. The display panel according to claim 1, further comprising a dam disposed around the sealant in the peripheral region; the second switching portion is located the frame glue with between the barricade.

8. A display mother board is characterized by comprising a plurality of panel areas arranged at intervals and areas to be cut, wherein the areas to be cut are arranged adjacent to each panel area; the display motherboard comprises the display panel as claimed in any one of claims 1 to 7 in the panel area, a plurality of landing pads in the area to be cut, and the conductive adhesive on the landing pads;

9. The display motherboard of claim 8, wherein the plurality of panel regions are distributed in an array; the plurality of adapter pads comprise a plurality of alignment electrification adapter pad groups which are arranged in one-to-one correspondence with the plurality of panel areas;

10. The display motherboard of claim 9, wherein the plurality of landing pads further comprises a plurality of balanced voltage landing pads disposed proximate an edge of the display motherboard and spaced apart from the aligned powered landing pads; the plurality of balanced voltage transfer pads are arranged in one-to-one correspondence with a part of the panel areas among the plurality of panel areas.