CN115002582B - Universal multiplication-free clock phase error detection method and system - Google Patents
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Abstract
The invention provides a general multiplication-free clock phase error detection method and a module. The clock phase error detection method and module enhance the clock component through single nonlinear symbol operation, and accurately extract the clock frequency component under different sampling frequencies through time domain phase shift. The clock phase error detection method and the module do not need multiplication operation, and are suitable for Nyquist pulse shaping signals and non-Nyquist pulse shaping signals with different roll-off coefficients, pulse amplitude modulation format signals, phase shift keying modulation format signals and quadrature amplitude modulation format signals, and various sampling rates with sampling multiplying power larger than 1. The invention is suitable for clock phase error detection of signals with various pulse shapes, modulation formats and sampling rates, has extremely low calculation complexity, can reduce the resource occupation of a digital signal processing chip, reduces the module power consumption, and has good application prospects in short-distance high-speed, long-distance backbone, optical fiber access and other optical transmission systems.
Description
Technical Field
The present invention relates to the technical field of optical communication, optical signal detection and digital signal processing, and more particularly, to a method and system for detecting clock phase errors in an optical receiver.
Background
In digital communication systems, particularly high-speed digital fiber optic communication systems, the transmitter and receiver must achieve accurate synchronization between the clocks to extract the optimal sampling point. The clock recovery module can calculate the frequency error and the phase error of the receiving-transmitting end clock, and compensates the frequency error and the phase error by adopting an internal interpolation filter in a feedforward or feedback mode. The clock phase error detection (TPED) algorithm is the core of the clock recovery module, and the current TPED algorithm can be divided into a frequency domain algorithm and a time domain algorithm according to the working mode. The frequency domain TPED algorithm extracts a clock component by processing the signal spectrum, while the time domain TPED algorithm extracts a clock component by processing the sequence of time domain sample values. The classical clock recovery algorithm in the time domain is the Gardner algorithm, while the frequency domain is the Godard algorithm. The calculation complexity is large, hundreds of real multiplications are needed for calculating the clock phase error each time, so that the hardware resources are occupied, the power consumption is large, the feedback delay is increased for the feedback clock recovery module, and the tracking speed of the clock frequency and the phase error is reduced.
Bandwidth limitation of optoelectronic devices in ultra-high speed communication systems is one of the bottlenecks affecting signal quality and limiting rate improvement. Conventional non-nyquist pulse shaping signals such as return-to-zero (NRZ) and non-return-to-zero (RZ) signals have a wide spectral width, and the bandwidth limitations of the optoelectronic devices can result in serious degradation of system performance. In order to reduce the signal bandwidth, nyquist pulse shaping is currently used in ultra-high speed optical transmission systems. The classical Gardner and Godard algorithm is not applicable to low roll-off nyquist pulse-shaping signals. To solve this problem, the fourth-order Gardner and Godard algorithm has recently been proposed, which is characterized by subjecting the signal sample values to a nonlinear modulo operation, followed by extraction of the clock component. But neither the fourth-order Gardner nor Godard algorithm is applicable to non-nyquist pulse-shaping signals. This results in the TPED algorithm not being applicable to a variety of different pulse-shaping signals.
In addition, a high-order Pulse Amplitude Modulation (PAM) signal, a Phase Shift Keying (PSK) modulation format signal, and a Quadrature Amplitude Modulation (QAM) format signal are generally employed in a high-speed optical transmission system. The PSK and QAM systems need to be modulated and demodulated by adopting a digital coherence technology, and the system cost is high, so that the PSK and QAM system is suitable for long-distance backbone networks and metropolitan area networks. The PAM system only needs to adopt an intensity modulation direct detection technology for modulation and demodulation, has lower system cost, and is suitable for low-cost short-distance optical transmission systems such as a data center, an optical access network and the like. An excellent clock phase error detection algorithm should be suitable for various modulation formats. In addition, in order to reduce power consumption of a DSP system in an ultra-high speed communication system, it is required to reduce sampling rate of signals as much as possible. The traditional clock phase error detection algorithm generally requires that the sampling multiplying power is more than or equal to 2, otherwise, the traditional clock phase error detection algorithm cannot work. For example Gardner, godard, fourth-order Gardner, and fourth-order Godard can only operate at 2 times the sampling rate, and cannot meet the requirement of reducing the sampling rate.
Disclosure of Invention
In order to solve the problems that the traditional clock phase error detection method and module have high calculation complexity and cannot be suitable for various pulse shapes, modulation formats and sampling rates, the invention provides a novel general multiplication-free clock phase error detection method and system.
In response to the above-identified deficiencies or improvements in the art, the present invention provides a universal multiplicative-free clock phase error detection system comprising: the data buffer module, several clock phase error calculation units, accumulator and complex phase arithmetic unit;
The data buffer module is used for receiving and buffering a plurality of sampling data and respectively outputting two adjacent sampling data to one clock phase error calculation unit;
each clock phase error calculation unit comprises a first conjugate arithmetic unit, a second conjugate arithmetic unit, a first 90-degree phase shifter, a second 90-degree phase shifter, a first adder, a second adder, a complex symbol function arithmetic unit, a multiplier and a phase shifter;
The accumulator is used for receiving the output values calculated by the clock phase error calculation units and summing the output values;
and the complex phase arithmetic unit is used for receiving the output of the accumulator, carrying out complex phase arithmetic and then outputting clock phase error.
The invention also provides a detection method adopted by the universal multiplication-free clock phase error detection system, and the clock phase error is calculated by the following formula
In the above formula, x n is a sequence of signal sample values input to the clock phase error detector, x n and x n+1 are two adjacent sample values, and n is a sequence index; (. Cndot.) * represents the conjugation of the operand in brackets; csgn (·) represents the sign function csgn (c) =sgn [ Re (c) ]+j·sgn [ Im (c) ], where c represents a complex number operated number, sgn (·) represents the sign function, the output is 1 when the number in parentheses is positive, and conversely is-1; re (-) and Im (-) represent the real and imaginary parts of the bracketed operand and arg (-) represents the phase angle of the bracketed operand; n represents the total number of signal sampling values used for calculating clock phase errors, and M represents the number of sampling points in a single symbol of a signal, namely the sampling rate.
As another alternative, the general detection method adopted by the non-multiplicative clock phase error detection module calculates the clock phase error by the following formula:
Preferably, in the method for detecting a common multiplication-free clock phase error detection module, the clock phase error is calculated by the following formula:
preferably, in the method for detecting a common multiplicative clock phase error detection module, the clock phase error is calculated by the following formula:
It should be noted that, the present invention proposes four general preferred methods for detecting a phase error without multiplication, the core of which is that the data spectrum is widened by csgn (·) symbol functions to keep a better clock component, and arg (·) and Im (·) represent the phase and imaginary parts of the clock component respectively, so the four preferred methods essentially have the same calculation principle for obtaining the clock error. The invention is applicable to various pulse shapes, modulation formats and sampling rates with sampling multiplying power larger than 1, meanwhile, multiplication operation is not needed, the invention has extremely low calculation complexity, can reduce the resource occupation of a digital signal processing chip, reduces the module power consumption, and has good application prospects in short-distance high-speed, long-distance backbone, optical fiber access and other optical transmission systems.
Drawings
The technical scheme of the invention is further specifically described below with reference to the accompanying drawings and the detailed description.
Fig. 1 is a schematic diagram of a general method and system for detecting phase errors of a multiplication-free clock according to the present invention.
The sub-graphs (a), (b) and (c) of fig. 2 show the clock component sizes calculated by the classical Lee algorithm for Non-Nyquist QPSK signals, nyquist QPSK signals with a roll-off factor (ROF) of 0, and Nyquist QPSK signals with a roll-off factor (ROF) of 0, respectively; the sub-graphs (d), (e) and (f) of fig. 2 show the magnitudes of clock components calculated by the fourth-order Gardner algorithm for a Non-Nyquist QPSK signal, a Nyquist QPSK signal with a roll-off factor (ROF) of 0, and a Nyquist QPSK signal with a roll-off factor (ROF) of 0, respectively; the sub-graphs (g), (h) and (i) of fig. 2 respectively show the magnitudes of clock components calculated by the general clock phase error detection method according to the first embodiment of the present invention for a Non-Nyquist QPSK signal, a Nyquist QPSK signal with a roll-off factor (ROF) of 0, and a Nyquist QPSK signal with a roll-off factor (ROF) of 0. In fig. 2B is the signal baud rate.
FIG. 3 (a) shows a plot of the calculated clock component size (dB units) versus Nyquist pulse-shaping roll-off factor for a pair of QPSK signal input signals for an embodiment of the present invention; fig. 3 (b) shows a plot of clock component size (dB units) versus sampling rate M for the nyquist shaping signal input with roll-off factor (ROF) of 0 and 0.1 according to an embodiment.
Fig. 4 (a) shows a graph (S-curve) of the estimated value and the true value of the clock phase error in four preferred forms of the proposed universal clock phase error detection method according to the first embodiment of the present invention when the input signal is complex (PSK, QAM modulated signal); fig. 4b shows a graph (S curve) of the relationship between the estimated value of the clock phase error and the true value in the first embodiment when the input signal is a real number (PAM-modulated signal).
Fig. 5 (a) shows a graph (S-curve) of the estimated value and the true value of the clock phase error of the general clock phase error detection method according to the second embodiment when the input signal is complex (PSK, QAM modulated signal); fig. 5 (b) shows a graph (S-curve) of the estimated value of the clock phase error versus the true value of the universal clock phase error detection method according to the second embodiment when the input signal is a real number (PAM-modulated signal).
Fig. 6 (a) shows a graph (S-curve) of the estimated value and the true value of the clock phase error of the universal clock phase error detection method according to the third embodiment when the input signal is complex (PSK, QAM modulated signal); fig. 6 (b) shows a graph (S-curve) of the relationship between the estimated value and the true value of the clock phase error of the universal clock phase error detection method proposed in the third embodiment when the input signal is a real number (PAM-modulated signal).
Fig. 7 (a) shows a graph (S-curve) of the estimated value and the true value of the clock phase error of the universal clock phase error detection method according to the fourth embodiment when the input signal is complex (PSK, QAM modulated signal); fig. 7b shows a graph (S-curve) of the relationship between the estimated value and the true value of the clock phase error in the general clock phase error detection method according to the fourth embodiment when the input signal is a real number (PAM-modulated signal).
Detailed Description
The present invention will be described in further detail with reference to the drawings, tables and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The invention provides a general multiplication-free clock phase error detection method and system, which are suitable for various pulse shapes, modulation formats and various sampling rates with sampling multiplying power larger than 1, do not need multiplication operation, have extremely low calculation complexity, can reduce the resource occupation of a digital signal processing chip, reduce the module power consumption, and have good application prospects in short-distance high-speed, long-distance backbone, optical fiber access and other optical transmission systems.
As shown in fig. 1, the general multiplication-free clock phase error detection module comprises a data buffer module 1, and identical N-1 clock phase error calculation units, an accumulator 11 and a complex phase operator 12. The data buffer module 1 is used for receiving and buffering a plurality of sampling data and respectively outputting two adjacent sampling data to one clock phase error calculation unit; each clock phase error calculation unit comprises a first conjugate operator 2, a second conjugate operator 3, a first 90 DEG phase shifter 4, a second 90 DEG phase shifter 5, a first adder 6, a second adder 7, a complex symbol function operator 8, a multiplier 9 and a phase shifter 10; the accumulator 11 is used for receiving and summing the output values calculated by the clock phase error calculation units; the complex phase operator 12 is used for receiving the output of the accumulator, performing complex phase operation and then outputting clock phase error.
As an embodiment one, a signal having M times the sampling rate (each symbol period contains M sampling values, M > 1) is input at the input of a clock phase error detection method and system, which calculates a clock phase error by the following formula:
as a second embodiment, a signal having M times the sampling rate (each symbol period contains M sampling values, M > 1) is input at the input of a clock phase error detection method and system, which calculates a clock phase error by the following formula:
as an embodiment three, a signal having M times the sampling rate (each symbol period contains M sampling values, M > 1) is input at the input of a clock phase error detection method and system, which calculates a clock phase error by the following formula:
as an embodiment four, a signal having M times the sampling rate (each symbol period contains M sampling values, M > 1) is input at the input of the clock phase error detection method and system, and the clock phase error detection method calculates the clock phase error by the following formula:
In the above formulas (1), (2), (3) and (4), x n is a sequence of signal sample values input to the clock phase error detector, x n and x n+1 are two adjacent sample values, and n is a sequence index; (. Cndot.) * represents the conjugation of the operand in brackets; csgn (·) represents the sign function sgn (c) =sgn [ Re (c) ]+j·sgn [ Im (c) ], where c represents a complex number, sgn (·) represents the sign function, and the output is 1 when the number in parentheses is positive, and conversely is-1; re (-) and Im (-) represent the real and imaginary parts of the bracketed operand and arg (-) represents the phase angle of the bracketed operand; n represents the total number of signal sampling values used for calculating clock phase errors, and M represents the number of sampling points in a single symbol of a signal, namely the sampling rate.
Referring to fig. 2, it should be noted that, in the second, third and fourth embodiments of the present invention, the magnitudes of clock components calculated for Non-Nyquist QPSK signals, nyquist QPSK signals with a roll-off factor (ROF) of 0, and Nyquist QPSK signals with a roll-off factor (ROF) of 0 are highly similar to those of the sub-graphs (g), (h) and (i) in fig. 1. As can be seen from fig. 2, only the universal clock error detection method proposed by the present invention in fig. 2 can obtain better clock components under different pulse shaping data, and has better versatility.
Referring to fig. 3, fig. 3 (a) shows a variation curve of a clock component size (dB unit) calculated for a pair of QPSK signal input signals according to a nyquist pulse-shaping roll-off factor according to an embodiment of the present invention; fig. 3 (b) shows a plot of clock component size (dB units) versus sampling rate M for the nyquist shaping signal input with roll-off factor (ROF) of 0 and 0.1 according to an embodiment. It should be noted that, the clock component size (dB unit) calculated by the QPSK signal input signal according to the second, third and fourth embodiments is highly similar to the change curve of the nyquist pulse shaping roll-off factor in fig. 3 (a); the transition curves of the clock component magnitudes (dB units) obtained at nyquist shaping signal inputs with roll-off factors (ROF) of 0 and 0.1 for embodiments two, three, and four, respectively, with sampling magnification M are highly similar to fig. 3 (b). Therefore, as can be seen from fig. 3 (a) and fig. 3 (b), the universal clock error detection method provided by the invention can be suitable for different pulse shaping schemes, various sampling rates with sampling multiplying power larger than 1, and has good universality.
As can be seen from fig. 4 to fig. 7, the four preferred forms of the universal clock phase error detection methods respectively proposed in the first, second, third and fourth embodiments have a better typical S-curve shape under different modulation format inputs, and have a better versatility. Meanwhile, the four preferred forms of the first embodiment, the second embodiment, the third embodiment and the fourth embodiment have different S-curve shapes, so that the optimal scheme can be selected according to application scenes. Illustrating: if the method is applied to a feedforward clock recovery system, the detection modes of the first and second embodiments with linear S curves are selected; if the method is applied to a feedback clock recovery system which does not need one-to-one correspondence between the estimated value of the clock phase error and the true value and has strict requirement on calculation delay, the detection mode of the third and fourth embodiments with the sine S curve can be selected.
Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiment examples, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention, and all such modifications and equivalents are intended to be encompassed in the scope of the claims of the present invention.
Claims (5)
1. A universal multiplicative-free clock phase error detection system, comprising: the data buffer module, several clock phase error calculation units, accumulator and complex phase arithmetic unit;
The data buffer module is used for receiving and buffering a plurality of sampling data and respectively outputting two adjacent sampling data to one clock phase error calculation unit;
each clock phase error calculation unit comprises a first conjugate arithmetic unit, a second conjugate arithmetic unit, a first 90-degree phase shifter, a second 90-degree phase shifter, a first adder, a second adder, a complex symbol function arithmetic unit, a multiplier and a phase shifter;
The accumulator is used for receiving the output values calculated by the clock phase error calculation units and summing the output values;
The complex phase arithmetic unit is used for receiving the output of the accumulator, carrying out complex phase arithmetic and then outputting clock phase error;
Input data are firstly input into the data buffer module, the data buffer module respectively outputs two adjacent paths of data to each clock phase error calculation unit, one path of input signals are parallelly sent to the first conjugate operator and the first adder, the other path of input signals are parallelly sent to the first 90-degree phase shifter and the second conjugate operator, the first 90-degree phase shifter is output to the first adder, and the second conjugate operator is output to the second 90-degree phase shifter; the first adder outputs to the complex symbol function operator, the first conjugate operator and the second 90 ° phase shifter outputs to the second adder, the complex symbol function operator and the second adder outputs to a multiplier, the multiplier outputs to the phase shifter, the phase shifter outputs to the accumulator, the accumulator outputs to the complex phase operator, and the complex phase operator outputs a clock phase error.
2. A method of detecting a universal multiplicative-free clock phase error as recited in claim 1, wherein: calculating clock phase error using the following formula
Wherein x n is a sequence of signal sample values input to the clock phase error detector, x n and x n+1 are two adjacent sample values, and n is a sequence index; (. Cndot.) * represents the conjugation of the operand in brackets; csgn (·) represents the sign function csgn (c) =sgn [ Re (c) ]+j·sgn [ Im (c) ], where c represents a complex number operated number, sgn (·) represents the sign function, the output is 1 when the number in parentheses is positive, and conversely is-1; re (-) and Im (-) represent the real and imaginary parts of the bracketed operand and arg (-) represents the phase angle of the bracketed operand; n represents the total number of signal sampling values used for calculating clock phase errors, and M represents the number of sampling points in a single symbol of a signal, namely the sampling rate.
3. A method of detecting a universal multiplicative-free clock phase error as recited in claim 1, wherein: calculating clock phase error using the following formula
Wherein x n is a sequence of signal sample values input to the clock phase error detector, x n and x n+1 are two adjacent sample values, and n is a sequence index; (. Cndot.) * represents the conjugation of the operand in brackets; csgn (·) represents the sign function csgn (c) =sgn [ Re (c) ]+j·sgn [ Im (c) ], where c represents a complex number operated number, sgn (·) represents the sign function, the output is 1 when the number in parentheses is positive, and conversely is-1; re (-) and Im (-) represent the real and imaginary parts of the bracketed operand and arg (-) represents the phase angle of the bracketed operand; n represents the total number of signal sampling values used for calculating clock phase errors, and M represents the number of sampling points in a single symbol of a signal, namely the sampling rate.
4. A method of detecting a universal multiplicative-free clock phase error as recited in claim 1, wherein: calculating clock phase error using the following formula
Wherein x n is a sequence of signal sample values input to the clock phase error detector, x n and x n+1 are two adjacent sample values, and n is a sequence index; (. Cndot.) * represents the conjugation of the operand in brackets; csgn (·) represents the sign function csgn (c) =sgn [ Re (c) ]+j·sgn [ Im (c) ], where c represents a complex number operated number, sgn (·) represents the sign function, the output is 1 when the number in parentheses is positive, and conversely is-1; re (-) and Im (-) represent the real and imaginary parts of the bracketed operand and arg (-) represents the phase angle of the bracketed operand; n represents the total number of signal sampling values used for calculating clock phase errors, and M represents the number of sampling points in a single symbol of a signal, namely the sampling rate.
5. A method of detecting a universal multiplicative-free clock phase error as recited in claim 1, wherein: calculating clock phase error using the following formula
Wherein x n is a sequence of signal sample values input to the clock phase error detector, x n and x n+1 are two adjacent sample values, and n is a sequence index; (. Cndot.) * represents the conjugation of the operand in brackets;
csgn (·) represents the sign function csgn (c) =sgn [ Re (c) ]+j·sgn [ Im (c) ], where c represents a complex number operated number, sgn (·) represents the sign function, the output is 1 when the number in parentheses is positive, and conversely is-1; re (-) and Im (-) represent the real and imaginary parts of the bracketed operand and arg (-) represents the phase angle of the bracketed operand; n represents the total number of signal sampling values used for calculating clock phase errors, and M represents the number of sampling points in a single symbol of a signal, namely the sampling rate.
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