CN115002368A

CN115002368A - Method and device for correcting oblique wave signal, processing device and image sensor

Info

Publication number: CN115002368A
Application number: CN202210608957.9A
Authority: CN
Inventors: 蔡化
Original assignee: Chengdu Image Design Technology Co Ltd
Current assignee: Chengdu Image Design Technology Co Ltd
Priority date: 2022-05-31
Filing date: 2022-05-31
Publication date: 2022-09-02

Abstract

The invention provides a method and a device for correcting a ramp signal, a processing device and an image sensor. The ramp signal correction method includes: an initialization phase and a correction phase; the initialization phase comprises: acquiring a count value of a counter corresponding to a reference pixel signal in a VR stage; and obtaining the count values of counters corresponding to ramp signals with different slopes in the VS stage; calculating the difference value of the count values of the ramp signals corresponding to the VR stage and the VS stage; after the initialization stage is finished, entering a correction stage; the correction phase comprises: acquiring an actual count value of a counter corresponding to an actual ramp signal of an actual pixel signal at a VS stage; and comparing the magnitude relation between the actual count value and the count value, and outputting according to the comparison result. The ramp signal correction method provided by the invention can correct different offset errors of the SS-ADC caused by ramp signals with different slopes, and further ensures the linearity of the CIS.

Description

Method and device for correcting oblique wave signal, processing device and image sensor

Technical Field

The invention is mainly applied to the field of integrated circuit design, and particularly relates to a ramp signal correction method, a correction device, a processing device and an image sensor which are applied to a CMOS Image Sensor (CIS).

Background

CMOS Image Sensors (CIS) have been widely used in the imaging fields of video, surveillance, industrial manufacturing, automobiles, home appliances, and the like. The main-stream reading circuit structure of the CIS is a reading circuit mainly comprising a column-level single-slope analog-to-digital converter (SS-ADC), so that the CIS is guaranteed to have sufficient conversion accuracy and speed under reasonable power consumption. The major drawback of this architecture is the long count period required for conversion, which increases exponentially with the ADC resolution. For example, a 12-bit SS-ADC, requires 4095 count cycles. In applications where the resolution and frame rate of CIS are high, the readout circuit structure based on the conventional SS-ADC has not been able to meet such requirements. Therefore, SS-ADC structures with segmented slopes are adopted in some designs, so that the time of an integral signal conversion stage is greatly shortened, and the frame rate of the CIS is improved. However, due to the different slopes of the ramp signals, the offset difference of the signals converted by the SS-ADC is different, which greatly increases the non-linearity error of the SS-ADC.

Therefore, the invention provides a ramp signal correction method, a correction device, a processing device and an image sensor, so as to correct different offset errors of the SS-ADC, which are caused by ramp signals with different slopes.

Disclosure of Invention

The embodiment of the invention provides a ramp signal correction method, a correction device, a processing device and an image sensor, which are used for correcting different offset errors of an SS-ADC (system-to-analog converter) caused by ramp signals with different slopes.

In a first aspect, the present invention provides a method for correcting a ramp signal, including: an initialization phase and a correction phase;

the initialization phase comprises:

acquiring reference oblique wave signals of reference pixel signals output by a row of pixel units corresponding to a first oblique wave stage, obtaining a reference count value of a counter according to the reference oblique wave signals, and resetting the counter; acquiring a first ramp signal of a second ramp stage, acquiring a first count value of a counter according to the first ramp signal, and resetting the counter; acquiring a second ramp signal of a second ramp stage, acquiring a second count value of the counter according to the second ramp signal, and resetting the counter; acquiring a third ramp signal of a second ramp stage, acquiring a third counting value of the counter according to the third ramp signal, and resetting the counter;

wherein a slope of the first ramp signal is equal to a slope of the reference ramp signal, a slope of the second ramp signal is M times the slope of the first ramp signal, a slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1;

calculating a first difference value, which is a difference value between the reference count value and the second count value; calculating a second difference value, the second difference value being a difference value between the reference count value and the third count value;

the correction phase comprises:

acquiring actual ramp signals of actual pixel signals output by pixel units of corresponding columns in the pixel array, which correspond to the second ramp stage, and acquiring an actual count value of the counter according to the actual ramp signals;

outputting the actual count value when the actual count value is less than or equal to the first count value; when the actual count value is greater than the first count value and less than or equal to a second count value, outputting a first true value, wherein the first true value is a difference between the actual count value and the first difference; and outputting a second true value when the actual count value is greater than the second count value and less than or equal to a third count value, wherein the second true value is a difference value between the actual count value and the second difference value.

The beneficial effects are that: the oblique wave signal correction method provided by the invention can correct different offset errors of the SS-ADC caused by oblique wave signals with different slopes, and further ensures the linearity of the CIS.

Optionally, M is less than or equal to 3 and N is less than or equal to 3.

In a second aspect, the present invention provides a ramp signal correction device configured to perform the ramp signal correction method of any one of the first aspects, including: an initialization module and a correction module;

the initialization module comprises an acquisition module and a calculation module, wherein the acquisition module comprises a reference value acquisition unit, a first value acquisition unit, a second value acquisition unit and a third value acquisition unit; the computing module comprises a first computing unit and a second computing unit;

the reference value acquisition unit is used for acquiring reference pixel signals output by a row of pixel units corresponding to reference ramp signals in a first ramp stage and acquiring a reference count value of the counter according to the reference ramp signals; the first numerical value acquisition unit is used for acquiring a first ramp signal of a second ramp stage and acquiring a first count value of the counter according to the first ramp signal; the second value acquisition unit is used for acquiring a second ramp signal of a second ramp stage and acquiring a second count value of the counter according to the second ramp signal; the third value acquisition unit is used for acquiring a third ramp signal of the second ramp stage and acquiring a third counting value of the counter according to the third ramp signal;

the first calculating unit is configured to calculate a first difference value, where the first difference value is a difference value between the reference count value and the second count value; the second calculating unit is configured to calculate a second difference value, where the second difference value is a difference value between the reference count value and the third count value;

the correction module comprises an actual numerical value acquisition unit, a judgment unit and an output unit;

the actual numerical value acquisition unit is used for acquiring actual ramp signals of actual pixel signals output by the pixel units of the corresponding column in the pixel array corresponding to the second ramp stage, and acquiring an actual count value of the counter according to the actual ramp signals;

the judging unit is used for judging the relationship between the actual counting value and the first counting value, the second counting value and the third counting value;

when the actual count value is less than or equal to the first count value, the output unit is configured to output the actual count value; when the actual count value is greater than the first count value and less than or equal to a second count value, the output unit is configured to output a first true value, where the first true value is a difference between the actual count value and the first difference; when the actual count value is greater than the second count value and less than or equal to a third count value, the output unit is configured to output a second true value, where the second true value is a difference between the actual count value and the second difference value.

Optionally, M is less than or equal to 3 and N is less than or equal to 3.

Further optionally, the ramp signal correction device further includes a reset control module;

the reset control module is used for controlling the counter to reset when the reference value acquisition unit obtains the reference count value of the counter; the first numerical value obtaining unit is further used for controlling the counter to reset when the first counting value of the counter is obtained; the counter is also used for controlling the counter to reset when the second count value of the counter is obtained by the second count value obtaining unit; and the counter is also used for controlling the reset of the counter when the third numerical value acquisition unit obtains the third numerical value of the counter.

In a third aspect, the present invention provides a ramp signal processing apparatus, including: a ramp generator and a ramp signal correction device as defined in any one of the second aspects.

The fourth invention, the present invention provides an image sensor comprising: a pixel array formed by pixel units, an ADC module, the ramp signal processing device according to the third aspect, a time sequence control module, a row selection decoding driving module and an output signal processing module;

the row selection decoding driving module is used for controlling the pixel array to output pixel signals;

the oblique wave generator is used for outputting oblique wave signals;

the ADC module comprises a comparator and a counter, wherein the comparator is used for comparing the pixel signal with the ramp signal, and the counter is used for outputting a current count value when the comparator deflects;

the ramp signal correction device is used for correcting the current count value of the counter and sending the corrected value to the output signal processing device;

the time sequence control module is used for controlling the working state of the image sensor.

As for the advantageous effects of the above second to fourth aspects, reference may be made to the description in the above first aspect.

Drawings

FIG. 1 is a circuit structure of a CIS standard four-transistor pixel unit;

FIG. 2 is a timing diagram of a standard four-transistor pixel cell;

FIG. 3 is a schematic diagram of a CIS readout circuit;

FIG. 4 is a timing diagram of the operation of a CIS readout circuit;

FIG. 5 is a flowchart of an initialization phase of a ramp signal calibration method according to the present invention;

FIG. 6 is a flowchart of a calibration phase of a ramp signal calibration method according to the present invention;

FIG. 7 is a schematic diagram illustrating the operation of a method for calibrating a ramp signal according to the present invention;

fig. 8 is a schematic diagram of a ramp signal correction device according to the present invention.

Detailed Description

The technical solution in the embodiments of the present application is described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, the terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the specification of the present application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, such as "one or more", unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe the association relationship of the associated objects, and means that there may be three relationships; for example, a and/or B, may represent: a alone, both A and B, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather mean "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise. The term "coupled" includes both direct and indirect connections, unless otherwise noted. "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

In the embodiments of the present application, the words "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Fig. 1 is a circuit structure of a CIS standard four-tube pixel unit, which is generally applied to a CIS of a row exposure mode and is composed of a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, a source follower transistor Msf, and a row strobe transistor Msel. One end of the photodiode PD is grounded, and the other end of the photodiode PD is connected to the drain of the transfer transistor Mtg; the gate of the transmission transistor Mtg is used for receiving a TX signal, and the source of the transmission transistor Mtg is connected to the drain of the reset transistor Mrst and the gate of the source follower transistor Msf; the source electrode of the reset transistor Mrst is connected with a power supply, and the grid electrode of the reset transistor Mrst is connected with an RX signal; the source electrode of the source electrode following transistor Msf is connected with a power supply, the drain electrode of the source electrode following transistor Msf is connected with the source electrode of the row gating transistor Msel, the grid electrode of the row gating transistor Msel is connected with a SEL signal, and the drain electrode of the row gating transistor Msel is connected with a row output line of the pixel array. The photodiode PD generates photoelectrons proportional to the intensity of light when it senses light. The transfer transistor Mtg is used to transfer photoelectrons in the photodiode PD, and when the TX signal is high, the transfer transistor Mtg is turned on to transfer photoelectrons in the photodiode PD to the floating node FD. The reset transistor Mrst is operative to reset the potential of the floating point FD when the RX signal is high. The source follower transistor Msf is an amplifier tube, when SEL is at a high potential, the row gate transistor Msel is turned on, the source follower transistor Msf, the row gate transistor Msel and a current source to the ground form a path, and the source follower transistor Msf follows the potential change of the floating point FD and is finally output from the output bus PIX _ OUT.

Fig. 2 is a timing sequence of the four-tube pixel unit shown in fig. 1, which is divided into reset (Rst), exposure (Exp), and signal Read (Read). In the Rst phase, the TX signal and the RX signal are "high", the transfer transistor Mtg and the reset transistor Mrst are both turned on, the floating point FD is reset and its potential is pulled up to the power supply voltage VDD. Then, the RX signal and the TX signal become "low" potential, and the Exp stage is entered, and the floating-point PD senses light and accumulates electrons. Then, entering a Read stage, wherein SEL is at a high potential, the RX signal is at a high potential, after the potential of the floating point FD is reset, the RX signal is pulled to a low potential, the TX signal is kept at a low potential, and the source follower transistor Msf is controlled by the floating point FD potential and is switched onThe over-output bus PIX _ OUT outputs the reset potential VRST. Thereafter, the TX signal is pulled to "high" potential and transfers electrons on the photodiode PD to the floating point FD, at which time the source follower transistor Msf is controlled by the potential of the floating point FD and outputs the integration potential VSIG through the output bus PIX _ OUT. The difference of VRST-VSIG is the amount of analog voltage corresponding to the photoelectrons on the photodiode PD. The VRST and VSIG potentials are converted to digital values by an analog-to-digital converter (ADC) circuit and subtracted to obtain digital values corresponding to the photoelectrons on the photodiode PD. If the ADC is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT ═ VRST-VSIG) × 2 ¹² /VREF。

Fig. 3 is a schematic structural diagram of a CIS readout circuit, which includes: the device comprises a pixel array, an ADC module, an oblique wave generator, a time sequence control module, a row selection decoding driving module and an output signal processing module. The pixel array is composed of a plurality of pixel units P as shown in fig. 1. The pixel array is read out in a ROW-by-ROW manner, specifically in the order ROW (0), ROW (1), … … ROW (k-1), ROW (k). And k is a positive integer. Each column of the pixel array is connected to a respective output bus, which is PIX _ OUT (0), PIX _ OUT (1), … PIX _ OUT (n-1), PIX _ OUT (n). The output ends of the output buses are connected with the ADC module. The ADC module is composed of a comparator and a counter, the comparator compares an output pixel signal with a RAMP signal RAMP, and the comparison result determines the count value of the counter. The ADC module also respectively judges the VRST and the VSIG potentials and converts the VRST-VSIG difference value into a digital quantity to be output.

Fig. 4 is a sequence of operation of the CIS sensing circuit shown in fig. 3, i.e., a Read phase of the sequence shown in fig. 2. The Read phase is entered, SEL is pulled to a "high" potential, RX is to a "high" potential, and the pixel cell is reset. RST _ CM is a comparator reset control signal and RST _ CM is also pulled high to reset the comparators in all ADC blocks. Then RX, RST _ CM change from "high" to "low" potential, ADC module enters normal working state. The working process of the ADC module comprises two processes of comparison and counting, firstly, when the RAMP potential starts to fall, the counter CNT starts to count until the comparator signal is turned from low potential to high potential, the counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC module needs to perform the above operations twice, that is, two ramp waves are generated as a reference of the ADC module. In the first ramp phase (i.e., "VR phase" in fig. 4), the ADC module will determine and store the reset potential VRST, and the counter CNT will count and store the count value CN1 corresponding to the t1 time period within t 1; in the second ramp phase (i.e., "VS phase" in fig. 4), the ADC module will determine and store the reset potential VSIG, and the counter CNT will count and store the count value CN2 corresponding to the time period t2 within the time period t 2. The final counter CNT outputs the count difference Δ CN equal to CN2-CN1 corresponding to the difference between VSIG and VRST. The above timing is the conventional SS-ADC conversion process. It can be seen that the main time required for conventional SS-ADC conversion is the "VS phase". A12-bit SS-ADC, whose "VS phase" takes at least 4095 count cycles. In order to shorten the time of the "VS phase", the prior art proposes a slope-segmented SS-ADC, that is, the ramp signal of the "VS phase" is divided into several ramp signal phases with different slopes, as shown by the dashed line of the "VS phase" in fig. 4, where the "VS phase" is divided into three phases (corresponding to three amplitudes of "small", "medium", and "large" in the pixel signal, respectively) of "VS 1, VS2, and VS 3". After the three stages are completed, the same signal amplitude range as that of the traditional SS-ADC can still be achieved.

Since the CIS is in low light, the main noise is from the readout noise, the slope of the ramp signal in the "VS 1 stage" is kept consistent with that in the "VR stage", and the conversion accuracy in the "VS 1 stage" is high. One least significant bit LSB of the ADC module is 1/2 ¹² V (the effective signal range of the ADC module is assumed to be 1V), so that the image detail under the low light of the CIS can be ensured to be complete; as the illumination intensity increases, the shot noise of photoelectrons becomes the dominant factor of CIS noise, and the quantization noise of the analog-to-digital converter is very small relative to the shot noise, which can properly reduce the precision of the ADC module, so that the slope of the ramp signal in the "VS 2 stage" is doubled compared with the slope of the ramp signal in the "VS 1 stage",such that one LSB is 1/2 ⁶ V; similarly, when the illumination intensity is larger, the ADC accuracy can be further reduced, the slope of the ramp signal in the "VS 3 stage" is increased by one time than that of the ramp signal in the "VS 2 stage", so that one LSB is 1/2 ³ And V. Because the slope is increased, the time for the comparator to deflect is shortened, namely the time for the counter to count is shortened, the counting time of the "VS 2 stage" is shortened compared with that of the original SS-ADC, and similarly, the counting time of the "VS 3 stage" is also shortened compared with that of the original SS-ADC. It can be seen that the SS-ADC based on slope segmentation in the VS stage can effectively improve the conversion speed of the SS-ADC. However, because the slopes of the ramp waves in the "VS 2 stage" and the "VS 3 stage" are different from that in the "VR stage", the flip delay of the comparator is necessarily different, so that different delay times exist in the conversion of the ADC signals in the three stages of "VS 1, VS2, and VS 3", and further different offset errors exist in the signals with three amplitudes of "small", "medium", and "large" of the pixel signals, which affects the linearity of the final CIS image.

In order to solve the influence of the misalignment error on the CIS image, the invention provides a ramp signal correction method, which comprises the following steps: an initialization phase and a correction phase.

The specific process of the initialization phase is shown in fig. 5, and includes:

s501: acquiring a reference oblique wave signal of a reference pixel signal output by a row of pixel units corresponding to a first oblique wave stage (VR stage), obtaining a reference count value of a counter according to the reference oblique wave signal, and resetting the counter;

s502: acquiring a first ramp signal of a second ramp stage (VS stage), acquiring a first count value of a counter according to the first ramp signal, and resetting the counter;

s503: acquiring a second ramp signal of a VS stage, obtaining a second count value of the counter according to the second ramp signal, and resetting the counter;

s504: acquiring a third oblique wave signal of a VS stage, obtaining a third counting value of the counter according to the third oblique wave signal, and resetting the counter; wherein a slope of the first ramp signal is equal to a slope of the reference ramp signal, a slope of the second ramp signal is M times the slope of the first ramp signal, a slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1;

s505: calculating a first difference value, which is a difference value between the reference count value and the second count value;

s506: calculating a second difference value, the second difference value being a difference value of the reference count value and the third count value.

The flow of the correction phase is shown in fig. 6, and includes:

s601: acquiring actual ramp signals corresponding to VS (voltage VS) stages of actual pixel signals output by pixel units in corresponding columns in a pixel array, and obtaining an actual count value of a counter according to the actual ramp signals;

s602: and judging the magnitude relation among the actual count value, the first count value, the second count value and the third count value, and outputting the values according to the judgment result.

S602 specifically comprises: outputting the actual count value when the actual count value is less than or equal to the first count value; when the actual count value is greater than the first count value and less than or equal to a second count value, outputting a first true value, wherein the first true value is a difference value between the actual count value and the first difference value; and when the actual count value is greater than the second count value and less than or equal to a third count value, outputting a second true value, wherein the second true value is a difference value between the actual count value and the second difference value.

Optionally, M is less than or equal to 3 and N is less than or equal to 3.

Illustratively, in the CIS conversion process, the first frame is generally an initialization frame where various CIS parameters, such as gain, exposure time, frequency, etc., are determined. In the initialization frame, the input terminal of the ADC is first grounded ("SW" is high in fig. 3, so that the switches S (0), S (1), … S (n) are turned on). Then, the initialization stage is entered, which has two detection processes, i.e. the detection process of the count delay difference caused by the deflection of the comparator due to the ramp signal in the "VS 2 stage" and the ramp signal in the "VR stage", and the detection process of the count delay difference caused by the deflection of the comparator due to the ramp signal in the "VS 3 stage" and the "VR stage". As shown in fig. 7, the first process: acquiring a reference RAMP signal RAMP _ R of a reference pixel signal output by a row of pixel units corresponding to a VR stage, obtaining a reference count value CN _ R of a counter according to the reference RAMP signal RAMP _ R, and resetting the counter; acquiring a first RAMP signal RAMP _ S1 in a "VS stage", obtaining a first count value CN _ S1 of a counter according to the first RAMP signal RAMP _ S1, and resetting the counter, wherein a slope of the first RAMP signal RAMP _ S1 is equal to a slope of the reference RAMP signal RAMP _ R, so CN _ S1 is equal to CN _ R.

Next, a second RAMP signal RAMP _ S2 in a "VS stage" is obtained, a second count value CN _ S2 of the counter is obtained according to the second RAMP signal RAMP _ S2, the counter is reset, a slope of the second RAMP signal RAMP _ S2 is 2 times of a slope of the first RAMP signal RAMP _ S1, a first difference Δ CN _ VS2, that is, a difference between the reference count value CN _ R and the second count value CN _ S2 is calculated, and Δ CN _ VS2 is CN _ S2-CN _ R. Δ CN _ VS2 is temporarily stored. The reference count value CN _ R contains the flip delay information D _ R of the comparator at the time of the normal slope ramp signal. CN _ S2 contains the flip delay information D _ S2 of the comparator in the case of a ramp signal with a slope twice as large, so the first difference Δ CN _ VS2 is the digital quantity of the signal falling in the VS2 stage corresponding to the flip delay difference of the comparator in the "VR" stage.

And finally, acquiring a third RAMP signal RAMP _ S3 in a VS stage, obtaining a third count value CN _ S3 of the counter according to the third RAMP signal RAMP _ S3, and resetting the counter, wherein the slope of the third RAMP signal RAMP _ S3 is 2 times that of the second RAMP signal RAMP _ S2. A second difference value Δ CN _ VS3, i.e. the difference between the reference count value CN _ R and the third count value CN _ S3, is calculated, Δ CN _ VS3 ═ CN _ S3-CN _ R. Δ CN _ VS3 is the delay difference for the slope at "VS 3 stage", which is also registered. After the initialization phase is completed, the CIS will continue to configure other parameters, such as gain, exposure time, etc., in the initial frame.

The correction phase follows. Entering a normal frame, acquiring an actual ramp signal of an actual pixel signal output by a pixel unit of a corresponding column in a pixel array corresponding to a VS stage, and obtaining an actual count value CN _ T of a counter according to the actual ramp signal; outputting the actual count value CN _ T when the actual count value CN _ T is less than or equal to the first count value CN _ S1; outputting a first true value CN _ T1 when the actual count value CN _ T is greater than the first count value CN _ S1 and less than or equal to a second count value CN _ S2, wherein the first true value CN _ T1 is a difference between the actual count value CN _ T and the first difference Δ CN _ VS 2; when the actual count value CN _ T is greater than the second count value CN _ S2 and less than or equal to a third count value CN _ S3, a second true value CN _ T2 is output, and the second true value CN _ T2 is a difference between the actual count value CN _ T and the second difference Δ CN _ VS 3.

The method for correcting the ramp signal can correct different offset errors of the SS-ADC caused by the ramp signals with different slopes, and further ensures the linearity of the CIS.

The present invention also provides a ramp signal correction device, as shown in fig. 8, configured to perform the ramp signal correction method according to any one of the above embodiments, including: an initialization module 801 and a correction module 802.

The initialization module 801 includes an obtaining module 8011 and a calculating module 8012, where the obtaining module 8011 includes a reference value obtaining unit 80111, a first value obtaining unit 80112, a second value obtaining unit 80113, and a third value obtaining unit 80114; the computing module 8012 comprises a first computing unit 80121 and a second computing unit 80122.

The reference value acquiring unit 80111 is configured to acquire a reference ramp signal, where the reference pixel signal output by a row of pixel units corresponds to a "VR stage", and obtain a reference count value of the counter according to the reference ramp signal; the first value obtaining unit 80112 is configured to obtain a first ramp signal in a "VS stage", and obtain a first count value of a counter according to the first ramp signal; the second count value acquiring unit 80113 is configured to acquire a second ramp signal in a "VS stage", and obtain a second count value of the counter according to the second ramp signal; the third value obtaining unit 80114 is configured to obtain a third ramp signal in a "VS stage", and obtain a third count value of the counter according to the third ramp signal. Wherein a slope of the first ramp signal is equal to a slope of the reference ramp signal, a slope of the second ramp signal is M times the slope of the first ramp signal, a slope of the third ramp signal is N times the slope of the second ramp signal, and both M and N are greater than 1; the first calculating unit 80121 is configured to calculate a first difference value, which is a difference value between the reference count value and the second count value; the second calculation unit 80122 is configured to calculate a second difference value, which is a difference value between the reference count value and the third count value.

The calibration module 802 includes an actual numerical value obtaining unit 8021, a determining unit 8022, and an output unit 8023; the actual value obtaining unit 8021 is configured to obtain an actual ramp signal, in which an actual pixel signal output by a corresponding row of pixel units in the pixel array corresponds to a "VS stage", and obtain an actual count value of the counter according to the actual ramp signal; the determining unit 8022 is configured to determine a relationship between the actual count value and the first count value, the second count value, and the third count value; when the actual count value is less than or equal to the first count value, the output unit 8023 is configured to output the actual count value; when the actual count value is greater than the first count value and less than or equal to a second count value, the output unit 8023 is configured to output a first true value, where the first true value is a difference between the actual count value and the first difference value; when the actual count value is greater than the second count value and less than or equal to a third count value, the output unit 8023 is configured to output a second true value, where the second true value is a difference between the actual count value and the second difference value.

Optionally, M is less than or equal to 3 and N is less than or equal to 3.

Further optionally, the ramp signal correction device further includes a reset control module; the reset control module is used for controlling the counter to reset when the reference value acquisition unit obtains the reference count value of the counter; the first numerical value obtaining unit is further used for controlling the counter to reset when the first counting value of the counter is obtained; the counter is also used for controlling the counter to reset when the second count value of the counter is obtained by the second count value obtaining unit; and the counter is also used for controlling the reset of the counter when the third numerical value acquisition unit obtains the third numerical value of the counter.

Based on the ramp signal correction device according to any of the embodiments, the present invention provides a ramp signal processing device, including: a ramp generator and a ramp signal correction device as in any one of the embodiments described above.

Based on the ramp signal processing device provided by the invention, the invention also provides an image sensor, which comprises: the device comprises a pixel array consisting of pixel units, an ADC module, a ramp signal processing device, a time sequence control module, a row selection decoding driving module and an output signal processing module, wherein the ramp signal processing device, the time sequence control module, the row selection decoding driving module and the output signal processing module are arranged in the pixel array; the row selection decoding driving module is used for controlling the pixel array to output pixel signals; the oblique wave generator is used for outputting oblique wave signals; the ADC module comprises a comparator and a counter, wherein the comparator is used for comparing the pixel signal with the ramp signal, and the counter is used for outputting a current count value when the comparator deflects; the oblique wave signal correction device is used for correcting the current count value of the counter and sending the corrected value to the output signal processing device; the time sequence control module is used for controlling the working state of the image sensor.

The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered within the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for correcting a ramp signal, comprising: an initialization phase and a correction phase;

the initialization phase comprises:

the correction phase comprises:

acquiring actual ramp signals corresponding to VS (voltage VS) stages of actual pixel signals output by pixel units in corresponding columns in a pixel array, and obtaining an actual count value of a counter according to the actual ramp signals;

outputting the actual count value when the actual count value is less than or equal to the first count value; when the actual count value is greater than the first count value and less than or equal to a second count value, outputting a first true value, wherein the first true value is a difference value between the actual count value and the first difference value; and outputting a second true value when the actual count value is greater than the second count value and less than or equal to a third count value, wherein the second true value is a difference value between the actual count value and the second difference value.

2. The ramp signal correction method according to claim 1, wherein M is less than or equal to 3 and N is less than or equal to 3.

3. A ramp signal correction apparatus configured to perform the ramp signal correction method according to any one of claims 1 to 2, comprising: an initialization module and a correction module;

the reference value acquisition unit is used for acquiring reference pixel signals output by a row of pixel units corresponding to reference ramp signals in a first ramp stage and acquiring a reference count value of the counter according to the reference ramp signals; the first numerical value acquisition unit is used for acquiring a first ramp signal of a second ramp stage and acquiring a first count value of the counter according to the first ramp signal; the second numerical value acquisition unit is used for acquiring a second ramp signal of a second ramp stage and acquiring a second numerical value of the counter according to the second ramp signal; the third value acquisition unit is used for acquiring a third ramp signal of the second ramp stage and acquiring a third counting value of the counter according to the third ramp signal;

the judging unit is used for judging the relation between the actual counting value and the first counting value, the second counting value and the third counting value;

the output unit is used for outputting the actual count value when the actual count value is less than or equal to the first count value; when the actual count value is greater than the first count value and less than or equal to a second count value, the output unit is configured to output a first true value, where the first true value is a difference between the actual count value and the first difference; when the actual count value is greater than the second count value and less than or equal to a third count value, the output unit is configured to output a second true value, where the second true value is a difference between the actual count value and the second difference.

4. The ramp signal correction device according to claim 3, wherein M is less than or equal to 3 and N is less than or equal to 3.

5. The ramp signal correction device according to claim 3, further comprising a reset control module;

the reset control module is used for controlling the counter to reset when the reference value acquisition unit obtains the reference count value of the counter;

the first numerical value obtaining unit is further used for controlling the counter to reset when the first counting value of the counter is obtained;

the counter is also used for controlling the counter to reset when the second count value of the counter is obtained by the second count value obtaining unit;

and the counter is also used for controlling the reset of the counter when the third numerical value acquisition unit obtains the third numerical value of the counter.

6. A ramp signal processing apparatus, comprising: a ramp generator and a ramp signal correction device as claimed in any one of claims 3 to 5.

7. An image sensor, comprising: a pixel array composed of pixel units, an ADC module, the ramp signal processing device according to claim 6, a timing control module, a row selection decoding driving module, an output signal processing module;

the oblique wave generator is used for outputting oblique wave signals;

the oblique wave signal correction device is used for correcting the current count value of the counter and sending the corrected value to the output signal processing device;