CN115000019A - Manufacturing method of oxide TFT thin film circuit - Google Patents
Manufacturing method of oxide TFT thin film circuit Download PDFInfo
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- CN115000019A CN115000019A CN202210525297.8A CN202210525297A CN115000019A CN 115000019 A CN115000019 A CN 115000019A CN 202210525297 A CN202210525297 A CN 202210525297A CN 115000019 A CN115000019 A CN 115000019A
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- 239000010409 thin film Substances 0.000 title claims abstract description 67
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000000059 patterning Methods 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 239000010408 film Substances 0.000 claims description 92
- 239000010410 layer Substances 0.000 claims description 50
- 238000007747 plating Methods 0.000 claims description 38
- 238000000034 method Methods 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 12
- 239000011241 protective layer Substances 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 3
- DNAUJKZXPLKYLD-UHFFFAOYSA-N alumane;molybdenum Chemical compound [AlH3].[Mo].[Mo] DNAUJKZXPLKYLD-UHFFFAOYSA-N 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229910001182 Mo alloy Inorganic materials 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- -1 molybdenum-niobium-aluminum-neodymium-molybdenum-niobium Chemical compound 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000011149 active material Substances 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
A manufacturing approach of the thin-film circuit of oxide TFT, the thin-film circuit includes TFT department and transparent electrode, TFT department includes grid, gate insulating layer, source, drain-source resistance and active part, the drain-source resistance is connected with transparent electrode, it sets up the first stack layer formed by grid, gate insulating layer, source, drain-source resistance and transparent electrode on the plaque first, the lateral surface of the first stack layer reserves the setting position used for setting up the active part; then, an active portion is provided on the set site, the active portion being formed by patterning an oxide semiconductor thin film. The TFT thin film circuit manufactured by the manufacturing method can keep relatively stable performance of the TFT.
Description
Technical Field
The invention relates to a manufacturing method of an oxide TFT thin film circuit, belonging to the field of semiconductor manufacturing.
Background
TFTs (thin film transistors) generally employ a plated semiconductor thin film as its active portion (active layer). A thin film circuit formed of TFTs is mainly used as a pixel driving circuit for a flat panel display device such as a TFT liquid crystal display, and its basic structure generally includes a TFT portion (that is, a TFT device) and a driving electrode, and the driving electrode is generally a transparent electrode formed by patterning an oxide transparent conductive film such as ITO.
The semiconductor thin film of the conventional TFT is generally an amorphous silicon thin film, which has low electron mobility and is manufactured by a complicated CVD (chemical vapor deposition) process. Thus, an oxide TFT using an oxide semiconductor thin film such as IGZO (indium zinc gallium oxide) as an active portion has been proposed, and the oxide semiconductor thin film has high electron mobility and can be produced by a relatively simple PVD (physical vapor deposition) process, and is a more preferable TFT active material.
In order to ensure high resistance of the oxide TFT in an off state, the oxide semiconductor thin film thereof generally needs to maintain an amorphous state and a stable chemical composition. However, in the manufacturing method of the oxide TFT thin film circuit, since a plurality of film layers such as a metal film, an insulating layer, and a transparent conductive film are required to be formed, the amorphous state of the oxide semiconductor thin film is easily damaged under the high temperature condition, and the chemical composition of the oxide semiconductor thin film is easily changed by diffusion doping of other film layers, which finally affects the TFT performance.
Disclosure of Invention
The invention aims to provide a manufacturing method of an oxide TFT thin film circuit, wherein a TFT can keep relatively stable performance, and the adopted technical scheme is as follows:
a method of manufacturing an oxide TFT thin film circuit, the thin film circuit including a TFT portion and a transparent electrode, the TFT portion including a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and an active portion, the drain electrode being connected to the transparent electrode, characterized in that:
firstly, arranging a first lamination composed of the grid electrode, a grid insulating layer, a source electrode, a drain electrode and a transparent electrode on a substrate, wherein a setting position for setting the active part is reserved on the outer side surface of the first lamination; then, the active portion is provided on the set bit, the active portion being formed by patterning an oxide semiconductor thin film.
Specifically, the substrate may be a glass substrate or a polyimide substrate. In the TFT portion, the gate electrode, the gate insulating layer, the source electrode, the drain electrode and the active portion are generally disposed in a bottom gate coplanar structure commonly used for TFT devices, that is, the gate electrode, the gate insulating layer are padded under the source electrode, the drain electrode and the active portion, and the active portion is stacked on the source electrode and the drain electrode.
The gate electrode may be a single-layer or multi-layer metal film composed of al, cr, cu, mo, and their alloys, and is patterned into a gate pattern, and in a specific circuit, the gate electrode is generally connected to an external driving circuit (e.g., a scanning line of a TFT liquid crystal display) which is also patterned from the above-mentioned metal film. The gate insulating layer is typically an insulating inorganic film layer, such as a silicon oxide (SiO2) or silicon nitride (Si3N4) film, covering the gate electrode. The source electrode and the drain electrode are typically patterned with another metal thin film, such as a single-layered or multi-layered metal film also made of al, cr, cu, mo, and an alloy thereof, and in a specific circuit, the source electrode is typically connected to an external driving circuit (such as a data line of a TFT liquid crystal display) also patterned with the metal thin film, and the drain electrode is connected to the transparent electrode.
The transparent electrode is typically patterned from an oxide transparent conductive film, such as an Indium Tin Oxide (ITO) film. High-temperature plating (the plating temperature exceeds 250 ℃) or high-temperature annealing (the annealing temperature exceeds 250 ℃) is preferably adopted in the manufacturing process to ensure the transparency.
The active portion is patterned from an oxide semiconductor film, which is generally an IGZO film, and which exhibits a high resistance state (surface resistance exceeding 10) in a natural state in accordance with a stoichiometric ratio in particular 10 Omega) is about 50 to 100 nm thick. The oxide semiconductor thin film is preferably in an amorphous state (generally, an amorphous state is obtained by PVC film formation under a condition of not more than 200 ℃) to ensure uniformity thereof.
The films can be formed by deposition through a PVC process, and patterning is realized through a photoetching process.
In a preferred embodiment of the present invention, the method for manufacturing a TFT thin film circuit includes the steps of:
plating a layer of transparent conductive oxide film, and patterning the transparent conductive oxide film into the transparent electrode;
plating a first layer of metal film, and patterning the first layer of metal film into the grid;
plating an inorganic insulating film covering the grid electrode, and arranging an opening or a through hole on the inorganic insulating film, wherein the opening or the through hole is positioned on the transparent electrode;
plating a second metal film, and patterning the second metal film into a source electrode lead-out portion, a drain electrode lead-out portion and a drain electrode lead-out portion, wherein the drain electrode lead-out portion extends to the opening or the through hole to be connected with the transparent electrode, so that the gate electrode, the gate insulating layer, the source electrode, the drain electrode extension portion and the transparent electrode form a first laminated structure, the source electrode and the drain electrode are oppositely arranged through a gap, the gap is defined as a channel region, the gate electrode is located in the channel region, and the source electrode, the drain electrode and the channel region form the set position;
and step five, further plating an oxide semiconductor film, and patterning the oxide semiconductor film into an active layer on the set position, wherein the active layer forms the connection of the source electrode and the drain electrode.
Alternatively, in another preferred embodiment of the present invention, the method for manufacturing a TFT thin film circuit includes the steps of:
step one, plating a first layer of metal film and patterning the first layer of metal film into the grid;
plating an inorganic insulating film covering the grid;
plating a layer of transparent conductive oxide film, and patterning the transparent conductive oxide film into the transparent electrode;
plating a second metal film and patterning the second metal film into a source electrode, a drain electrode and a drain electrode lead-out part, wherein the drain electrode lead-out part extends and is overlapped on part of the transparent electrode to be connected with the transparent electrode, so that the gate electrode, the gate insulating layer, the source electrode, the drain electrode extension part and the transparent electrode form a first laminated structure, the source electrode and the drain electrode are oppositely arranged at a gap, the gap is defined as a channel region, the gate electrode is positioned in the channel region, and the source electrode, the drain electrode and the channel region form the set position;
and step five, further plating an oxide semiconductor film, and patterning the oxide semiconductor film into an active part on the set position, wherein the active part forms the connection of the source electrode and the drain electrode.
Preferably, in order to further protect the active portion from external environmental leads, a protective layer is further covered on the active portion, and the protective layer is a cured photosensitive resin coating which does not need high temperature conditions during manufacturing and does not affect the active portion.
Therefore, the active part of the oxide TFT thin film circuit manufactured by the method is left to be manufactured at last, so that the oxide semiconductor thin film of the active part is not influenced by a high-temperature process when other film layers are manufactured, the amorphous state of the oxide semiconductor thin film can be effectively prevented from being damaged by a high-temperature condition, the chemical components of the oxide TFT thin film circuit are prevented from being changed by diffusion doping of other film layers in contact with the oxide TFT thin film circuit under the high-temperature condition, and the stability of the oxide TFT is finally ensured.
The technical solution of the present invention is further explained by the accompanying drawings and the specific embodiments.
Drawings
FIG. 1 is a schematic plan view of an oxide TFT thin film circuit according to a first embodiment;
FIG. 2 is a schematic cross-sectional view taken along line A-A' of FIG. 1;
FIG. 3 is a schematic diagram of a first process step of fabricating an oxide TFT thin film circuit according to a first embodiment;
FIG. 4 is a second schematic diagram illustrating a second process step of fabricating an oxide TFT thin film circuit according to the first embodiment;
FIG. 5 is a schematic view of a third process step of fabricating an oxide TFT thin film circuit according to the first embodiment;
FIG. 6 is a fourth schematic diagram illustrating a fourth exemplary embodiment of a method for fabricating an oxide TFT thin film circuit;
FIG. 7 is a fifth schematic view of a first embodiment of a process for fabricating an oxide TFT thin film circuit;
FIG. 8 is a sixth schematic diagram illustrating a first exemplary embodiment of a process for fabricating an oxide TFT thin film circuit;
FIG. 9 is a schematic plan view of an oxide TFT thin film circuit according to a second embodiment;
FIG. 10 is a cross-sectional view taken along line B-B' of FIG. 9;
FIG. 11 is a schematic view of a first process step of fabricating an oxide TFT thin film circuit according to a second embodiment;
FIG. 12 is a second schematic diagram illustrating a second process step for fabricating an oxide TFT thin film circuit according to a second embodiment;
FIG. 13 is a schematic view of a third exemplary embodiment of a second exemplary embodiment of a third exemplary embodiment of an oxide TFT thin film circuit;
FIG. 14 is a fourth schematic diagram illustrating a second exemplary embodiment of a manufacturing process of an oxide TFT thin film circuit;
FIG. 15 is a fifth schematic view of a fifth process step for fabricating an oxide TFT thin film circuit according to the second embodiment;
fig. 16 is a sixth schematic view of a manufacturing step of an oxide TFT thin film circuit according to the second embodiment.
Detailed Description
Example one
As shown in fig. 1 and 2, the oxide TFT thin film circuit 100 includes a TFT section 10 and a transparent electrode 20. The TFT section 10 includes a gate electrode 11, a gate insulating layer 12, a source electrode 13, a drain electrode 14, and an active portion 15, and the drain electrode 14 is connected to a transparent electrode 20.
The method for manufacturing the thin film circuit 100 includes: 1) firstly, a first laminated layer 30 consisting of a grid electrode 11, a grid insulating layer 12, a source electrode 13, a drain electrode 14 and a transparent electrode 20 is arranged on a substrate, and a setting position 31 for setting an active part 15 is reserved on the outer side surface of the first laminated layer 30; 2) then, the active portion 15 patterned from the IGZO thin film is provided on the setting site 31.
Specifically, as shown in fig. 3 to 8, the above manufacturing method is to perform the following steps on a glass substrate 40 (or a polyimide substrate):
step one, plating an ITO film and patterning the ITO film into a transparent electrode 20, wherein the film plating temperature of the ITO film is more than or equal to 250 ℃, or heating the ITO film to more than or equal to 250 ℃ after film plating is finished so as to anneal;
plating a first molybdenum-aluminum-molybdenum (molybdenum-niobium-aluminum-neodymium-molybdenum-niobium) alloy film, and patterning the first molybdenum-aluminum-molybdenum alloy film into a grid 11;
step three, plating a silicon nitride (or silicon oxide) film 12 covering the grid electrode 11, and arranging a through hole 121 on the silicon nitride (or silicon oxide) film by ion etching, wherein the through hole 121 is positioned above the transparent electrode 20;
step four, plating a second layer of molybdenum-aluminum-molybdenum alloy film, and patterning the second layer of molybdenum-aluminum-molybdenum alloy film into a source electrode 13 and a drain electrode 14 (including a lead-out part), wherein the lead-out part of the drain electrode 14 extends to the through hole 12 and is connected with the transparent electrode 20, so that the gate electrode 11, the gate insulating layer 12, the source electrode 13, the drain electrode 14 and the transparent electrode 20 form a first stack 30, wherein a gap between the source electrode 13 and the drain electrode 14 is a channel region 16 of the TFT, the gate electrode 11 is positioned below the channel region 16, and the source electrode 13, the drain electrode 14 and the channel region 16 form a setting bit 31;
step five, further plating an IGZO semiconductor film, and patterning the IGZO semiconductor film into an active part 15 on the set position 31, wherein the active part 15 forms the connection of the source electrode 13 and the drain electrode 14, and the plating temperature of the IGZO semiconductor film is controlled within 200 ℃;
and step six, further curing a photosensitive resin coating layer serving as a protective layer 17 on the active part 15.
The films are all formed by PVC process deposition, and the patterning is realized by a photoetching process.
Therefore, the TFT active portion 15 of the thin film circuit 100 is left to be manufactured last, so that the IGZO film of the active portion 15 is not affected by a high temperature process when manufacturing other film layers, so that the amorphous state of the thin film circuit can be effectively prevented from being damaged by a high temperature condition, and the chemical composition of the thin film circuit can be prevented from being changed by diffusion doping of the other film layers in contact with the thin film circuit under the high temperature condition, thereby finally ensuring the stability of the TFT 10.
Example two
As shown in fig. 9 to 16, in addition to the first embodiment, the following steps are performed on the glass substrate 40 (or polyimide substrate) instead of the specific manufacturing method of the thin film circuit 100, so as to constitute a second embodiment of the present invention:
step one, plating a first layer of molybdenum-aluminum-molybdenum (molybdenum-niobium-aluminum-neodymium-molybdenum-niobium) alloy film, and patterning the first layer of molybdenum-aluminum-molybdenum (molybdenum-niobium-aluminum-neodymium-molybdenum-niobium) alloy film into a grid 11;
step two, plating a silicon nitride (or silicon oxide) film covering the grid 11;
plating an ITO film and patterning the ITO film into a transparent electrode 20, wherein the film plating temperature of the ITO film is more than or equal to 250 ℃, or heating the ITO film to more than or equal to 250 ℃ after film plating is finished so as to anneal;
step four, plating a second molybdenum-aluminum-molybdenum alloy film, and patterning the second molybdenum-aluminum-molybdenum alloy film into a source electrode 13 and a drain electrode 14, wherein the drain electrode 14 extends and is overlapped on a part of the transparent electrode 20 to form connection with the transparent electrode, so that the gate electrode 11, the gate insulating layer 12, the source electrode 13, the drain electrode 14 and the transparent electrode 20 form a first laminated layer 30, a gap between the source electrode 13 and the drain electrode 14 is a channel region 16 of the TFT, the gate electrode 11 is positioned below the channel region 16, and the source electrode 13, the drain electrode 14 and the channel region 16 form a set bit 31;
step five, further plating an IGZO semiconductor film, and patterning the IGZO semiconductor film into an active part 15 on the set position 31, wherein the active part 15 forms the connection of the source electrode 13 and the drain electrode 14, and the plating temperature of the IGZO semiconductor film is controlled within 200 ℃;
step six, a photosensitive resin coating layer as a protective layer 17 is further cured on the active portion 15.
In addition, it should be noted that the names of the parts and the like of the embodiments described in the present specification may be different, and the equivalent or simple change of the structure, the characteristics and the principle described in the present patent idea is included in the protection scope of the present patent. Various modifications, additions and substitutions for the specific embodiments described may be made by those skilled in the art without departing from the scope of the invention as defined in the accompanying claims.
Claims (9)
1. A method of manufacturing an oxide TFT thin film circuit, the thin film circuit comprising a TFT portion and a transparent electrode, the TFT portion comprising a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and an active portion, the drain electrode being connected to the transparent electrode, characterized in that:
firstly, arranging a first laminated layer consisting of the grid electrode, the grid insulating layer, the source electrode, the drain electrode and the transparent electrode on a substrate, wherein a setting position for setting the active part is reserved on the outer side surface of the first laminated layer; then, the active portion is provided on the set bit, the active portion being formed by patterning an oxide semiconductor thin film.
2. The method of manufacturing an oxide TFT thin film circuit according to claim 1, wherein: the transparent electrode is formed by patterning an indium tin oxide film.
3. The method for manufacturing an oxide TFT thin film circuit according to claim 2, wherein: the indium tin oxide film is subjected to high-temperature coating or high-temperature annealing in the manufacturing process.
4. The method of manufacturing an oxide TFT thin film circuit according to claim 1, wherein: the oxide semiconductor film is an IGZO thin film.
5. The method for manufacturing an oxide TFT thin film circuit according to claim 4, wherein: the IGZO thin film is in an amorphous state.
6. The method for manufacturing an oxide TFT thin film circuit according to claim 1, wherein the following steps are performed on the substrate:
plating a layer of transparent conductive oxide film, and patterning the transparent conductive oxide film into the transparent electrode;
plating a first layer of metal film, and patterning the first layer of metal film into the grid;
plating an inorganic insulating film covering the grid electrode, and arranging an opening or a through hole on the inorganic insulating film, wherein the opening or the through hole is positioned on the transparent electrode;
plating a second metal film, and patterning the second metal film into a source electrode lead-out portion, a drain electrode lead-out portion and a drain electrode lead-out portion, wherein the drain electrode lead-out portion extends to the opening or the through hole to be connected with the transparent electrode, so that the gate electrode, the gate insulating layer, the source electrode, the drain electrode extension portion and the transparent electrode form a first laminated structure, the source electrode and the drain electrode are oppositely arranged through a gap, the gap is defined as a channel region, the gate electrode is located in the channel region, and the source electrode, the drain electrode and the channel region form the set position;
and step five, further plating an oxide semiconductor film, and patterning the oxide semiconductor film into an active layer on the set position, wherein the active layer forms the connection of the source electrode and the drain electrode.
7. The method of manufacturing an oxide TFT thin film circuit according to claim 6, wherein: still further, a protective layer is covered on the active part, and the protective layer is a cured photosensitive resin coating.
8. The method for manufacturing an oxide TFT thin film circuit as claimed in claim 1, wherein the following steps are performed on a substrate:
step one, plating a first layer of metal film, and patterning the first layer of metal film into the grid;
plating an inorganic insulating film covering the grid;
plating a layer of transparent conductive oxide film, and patterning the transparent conductive oxide film into the transparent electrode;
plating a second metal film and patterning the second metal film into a source electrode, a drain electrode and a drain electrode lead-out part, wherein the drain electrode lead-out part extends and is overlapped on part of the transparent electrode to be connected with the transparent electrode, so that the gate electrode, the gate insulating layer, the source electrode, the drain electrode extension part and the transparent electrode form a first laminated structure, the source electrode and the drain electrode are oppositely arranged at a gap, the gap is defined as a channel region, the gate electrode is positioned in the channel region, and the source electrode, the drain electrode and the channel region form the set position;
and step five, further plating an oxide semiconductor film, and patterning the oxide semiconductor film into an active part on the set position, wherein the active part forms the connection of the source electrode and the drain electrode.
9. The method for manufacturing an oxide TFT thin film circuit according to claim 8, wherein: still further, a protective layer is covered on the active part, and the protective layer is a cured photosensitive resin coating.
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| CN202210525297.8A CN115000019A (en) | 2022-05-15 | 2022-05-15 | Manufacturing method of oxide TFT thin film circuit |
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| CN202210525297.8A CN115000019A (en) | 2022-05-15 | 2022-05-15 | Manufacturing method of oxide TFT thin film circuit |
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