CN114999417A - Display panel test set, mother board and display panel - Google Patents
Display panel test set, mother board and display panel Download PDFInfo
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- 238000012360 testing method Methods 0.000 title claims abstract description 266
- 239000000523 sample Substances 0.000 claims abstract description 26
- 230000003068 static effect Effects 0.000 claims abstract description 13
- 230000005611 electricity Effects 0.000 claims abstract description 9
- 238000004804 winding Methods 0.000 claims abstract description 5
- 238000007599 discharging Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 19
- 239000010409 thin film Substances 0.000 description 18
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 101100214488 Solanum lycopersicum TFT2 gene Proteins 0.000 description 2
- 101100214491 Solanum lycopersicum TFT3 gene Proteins 0.000 description 2
- 101100214494 Solanum lycopersicum TFT4 gene Proteins 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
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Abstract
The invention discloses a display panel test set, a motherboard and a display panel, wherein the display panel test set comprises: the display panel comprises a plurality of display panels arranged in an array, wherein the display panels are provided with a plurality of driving wires; at least one group of test voltage lines disposed at least one side of the plurality of display panels; the test pads are arranged between the display panels and the group of test voltage lines and are electrically connected with the driving lines in the display panels one by one, and the test pads are used for being contacted with probes of the lighting test equipment; the plurality of electrostatic discharge units are arranged on one sides of the plurality of test bonding pads, which are far away from the plurality of display panels, and are electrically connected with the plurality of test bonding pads one by one; each group of test voltage lines is provided with a first test voltage line between the test pads and the static electricity discharge units, the test pads and the static electricity discharge units are arranged in a staggered mode relative to the first test voltage line, and the wiring of the first test voltage line is arranged for avoiding the winding of the test pads.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel test set, a mother board and a display panel.
Background
In recent years, intelligent wearable equipment is developed rapidly, is one of the fastest-speed high-tech products in the world, and has huge development potential.
For the production of the display panel of the intelligent wearable device, about 1000 display panels can be arranged on each glass substrate, and the workload is extremely large for the personnel detecting the picture quality.
In order to reduce the workload of the person detecting the screen quality, it is generally necessary to perform Group (Group) mode lighting, for example, the display panels on the glass substrate are cut into a Group by 2 × 2 or 2 × 4, and lighting detection is performed for each display panel Group, thereby reducing the workload of the person detecting the screen quality.
However, the effective utilization rate of the glass substrate is increasing, so that the circuit arrangement on the motherboard on which a plurality of display panels are arranged is getting tighter and tighter, and the problem of the test pad being stuck and biased easily exists in the Group lighting process, so that the test pad is short-circuited with the nearby circuit, and the lighting test result is poor display of the display panel.
Disclosure of Invention
The embodiment of the invention provides a display panel test set, a mother board and a display panel, which are used for solving the problems in the prior art.
In a first aspect, to solve the above technical problem, an embodiment of the present invention provides a display panel testing set, including:
the display panel comprises a plurality of display panels arranged in an array, wherein the display panels are provided with a plurality of driving lines;
at least one group of test voltage lines disposed on at least one side of the plurality of display panels to extend in a first direction; the group of test voltage lines are used for providing test voltages for a group of display panels arranged along the first direction in the plurality of display panels;
the test pads are arranged between the display panels and the group of test voltage lines and are electrically connected with the drive lines in the display panels one by one, and the test pads are used for being in contact with probes of lighting test equipment;
the electrostatic discharge units are arranged on one side of the test bonding pads, which is far away from the display panels, and are electrically connected with the test bonding pads one by one;
wherein, have one in the test voltage line of a set of be located a plurality of test pads with first test voltage line between a plurality of static discharge unit, a plurality of test pads with a plurality of static discharge unit about first test voltage line dislocation arrangement, just the wiring of first test voltage line is for dodging the wire winding setting of test pad.
In one possible embodiment, the first test voltage line is a polygonal line of a square waveform.
In one possible implementation, the first test voltage line includes:
a plurality of first line segments and a plurality of second line segments extending along the first direction, the plurality of first line segments corresponding to the plurality of electrostatic discharge units one to one, the plurality of second line segments corresponding to the plurality of test pads one to one; in a second direction, the distance from the first line segment to the test pad is smaller than the distance from the second line segment to the test pad, and the second direction intersects with the first direction;
and each connecting line is connected between the first line segment and the second line segment.
In one possible embodiment, the length of the first line segment is greater than or equal to the length of the electrostatic discharge unit in the first direction;
the length of the second line segment is greater than the length of the test pad in the first direction.
In one possible embodiment, the distance between the first line segment and the second line segment is greater than the maximum alignment error of the probe with the corresponding test pad.
In a possible embodiment, each set of test voltage lines comprises the first test voltage line and a second test voltage line parallel to each other;
the second testing voltage line is arranged on one side, away from the first testing voltage line, of the plurality of static electricity releasing units, and the second testing voltage line is a straight line.
In a possible embodiment, when the test set of display panels has two rows or two columns of display panels, the at least one set of test voltage lines is composed of two sets of test voltage lines, and the two sets of test voltage lines are symmetrically disposed with respect to the plurality of display panels.
In one possible embodiment, the electrostatic discharge unit includes:
the first subunit and the second subunit are oppositely arranged; the first sub-unit is close to the first test voltage line, and the second sub-unit is close to the second test voltage line;
the input ends of the first subunit and the second subunit are electrically connected with a test pad;
the output end of the first subunit is electrically connected with the first test voltage line, and the output end of the second subunit is electrically connected with the second test voltage line.
In a second aspect, an embodiment of the present invention provides a motherboard, including a plurality of display panel test sets according to the first aspect arranged in an array.
In a third aspect, embodiments of the present invention provide a display panel manufactured by the display panel test set according to the first aspect.
The invention has the following beneficial effects:
in the embodiment of the invention, the plurality of test pads and the plurality of electrostatic discharge units in the display panel test set are arranged in a staggered manner relative to the first test voltage line, and the first test voltage line is arranged in a winding manner avoiding the test pads, so that the first test voltage line close to the test pads in the test voltage line set and the test pads can keep a relatively safe distance (namely, a distance which is not pricked) and the test pads, and the plurality of test pads and the plurality of electrostatic discharge units are arranged in a staggered manner relative to the first test voltage line, and the test pads and the adjacent electrostatic discharge units can keep a relatively safe distance, thereby preventing probes of the lighting test equipment from pricking the first test voltage line and the electrostatic discharge units to be short-circuited when the probes of the lighting test equipment are pricked, and further enabling the lighting test equipment to accurately detect the real image quality of each display panel in the display panel test set, the accuracy of detection is improved, and the display panel can be prevented from being damaged due to short circuit, so that the yield of the display panel is improved.
Drawings
FIG. 1 is a schematic diagram of the location of a test pad and associated line device in the related art;
FIG. 2 is a schematic structural diagram of a display panel test set according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a display panel test set according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a first test voltage line according to an embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a length relationship between the first line segment and the electrostatic discharge unit, and between the second line segment and the test pad according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a distance between a first line segment and a second line segment according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a group of test voltage lines according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an electrostatic discharge unit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of an electrostatic discharge unit according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a display panel test set, a mother board and a display panel, which are used for solving the problems in the prior art.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, the present invention is further described with reference to the accompanying drawings and examples. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their repetitive description will be omitted. The words expressing the position and direction described in the present invention are illustrated in the accompanying drawings, but may be changed as required and still be within the scope of the present invention. The drawings of the present invention are for illustrative purposes only and do not represent true scale.
It should be noted that in the following description, specific details are set forth in order to provide a thorough understanding of the present invention. The invention can be embodied in many different forms than those described herein and those skilled in the art will appreciate that the invention is susceptible to similar forms of embodiment without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. The description which follows is a preferred embodiment of the present application, but is made for the purpose of illustrating the general principles of the application and not for the purpose of limiting the scope of the application. The protection scope of the present application shall be subject to the definitions of the appended claims.
Fig. 1 is a schematic diagram illustrating the positions of a test pad and a related circuit device in the related art.
Fig. 1 shows a plurality of test pads 3 and test voltage lines VGH and VGL corresponding to one display panel 1, and a plurality of Electro-static discharge (ESD) units 4, where the test pads 3 are electrically connected to data lines and scan lines (not shown in fig. 1) in the display panel 1 one by one, the test pads 3 are electrically connected to the electrostatic discharge units 4 one by one, the electrostatic discharge units 4 have one input terminal and 2 output terminals, the input terminal of the electrostatic discharge unit 4 is electrically connected to the corresponding test pad 3, and the 2 output terminals of the electrostatic discharge unit 4 are electrically connected to VGH and VGL, respectively.
When the lighting test needs to be performed on the display panel 1, the probes of the lighting test equipment need to be aligned with the corresponding test pads 3, however, certain errors often exist in the alignment, and the probes are deviated due to incomplete alignment of the test pads 3. When the probe is stuck to the adjacent line or electrostatic discharge unit, the probe is easy to stick to the adjacent line or electrostatic discharge unit, so that the line or electrostatic discharge unit is short-circuited, and the display of the display panel is poor according to the test result, so that the test result is not accurate enough, and even the display panel is possibly damaged.
In order to solve the above problems, embodiments of the present invention provide a display panel test set, a motherboard, and a display panel, which include the following steps:
referring to fig. 2 and fig. 3, fig. 2 is a schematic structural diagram of a display panel test set according to an embodiment of the present invention, and fig. 3 is a schematic structural diagram of a display panel test set according to an embodiment of the present invention, where the display panel test set includes:
a plurality of display panels 1 arranged in an array, the display panels 1 having a plurality of driving lines (not shown in fig. 2 and 3); the driving lines include data lines and scanning lines in the display panel 1 for controlling each pixel to display; the display panel test set may have a 2 × 2 or 2 × 4 array of display panels, or may have an N × M array of display panels, and N, M is a natural number, or may be 4 × 1, and the specific examples are not limited to these, and the display panel test set may be freely set according to actual needs.
At least one set of test voltage lines 2 disposed on at least one side of the plurality of display panels 1 to extend in a first direction X; the group of test voltage lines 2 is used for providing test voltages for a group of display panels 1 arranged along a first direction X among the plurality of display panels 1;
a plurality of test pads 3 disposed between the plurality of display panels and the set of test voltage lines 2 and electrically connected to the plurality of driving lines in the plurality of display panels 1 one by one, the test pads 3 being used to contact probes of the lighting test apparatus; the lighting test equipment is used for detecting the image quality of the display panel, and before the lighting test equipment is used for testing, probes in the lighting test equipment and corresponding test pads 3 are generally required to be aligned, but the alignment accuracy is limited, and the probes are prone to be misaligned.
The plurality of electrostatic discharge units 4 are arranged on one sides of the plurality of test pads 3 far away from the plurality of display panels, and are electrically connected with the plurality of test pads 3 one by one; the static electricity discharging unit 4 discharges static electricity on the driving lines in the display panel 1 to prevent damage to the display panel.
The group of testing voltage lines 2 has a first testing voltage line 21 between the testing pads 3 and the static electricity discharging units 4, the testing pads 3 and the static electricity discharging units 4 are arranged in a staggered manner with respect to the first testing voltage line 21, and the wiring of the first testing voltage line 21 is arranged to avoid the winding of the testing pads 3.
In the embodiment of the present invention, the plurality of test pads 3 and the plurality of electrostatic discharge units 4 in the display panel test set are arranged in a staggered manner with respect to the first test voltage line 21, and the first test voltage line 21 is routed so as to avoid the routing of the test pad 3, so that the first test voltage line 21 close to the test pad 3 in the set of test voltage lines 2 and the test pad 3 can keep a relatively safe distance (i.e. a distance that the test pad 3 is not pricked) from the test pad 3, and the plurality of test pads 3 and the plurality of electrostatic discharge units 4 are arranged in a staggered manner with respect to the first test voltage line 21, so that the test pad 3 and the adjacent electrostatic discharge unit 4 can keep a relatively safe distance, thereby preventing a probe of the test equipment from pricking the first test voltage line 21 and the electrostatic discharge unit to cause short circuit when the probe of the test equipment pricks, and further enabling the test equipment to accurately detect the real lighting quality of each display panel in the display panel test set, the accuracy of detection is improved, and the display panel can be prevented from being damaged due to short circuit, so that the yield of the display panel is improved.
As shown in fig. 2 or 3, the first test voltage line 21 may be a polygonal line of a square waveform.
The first testing voltage line 21 is set to be a polygonal line of a square waveform, so that the first testing voltage line 21 can avoid the testing pad 3, the safe distance between the first testing voltage line 21 and the testing pad 3 is kept, meanwhile, the concave-convex characteristics of the polygonal line of the square waveform can be utilized, the electrostatic discharge unit 4 and the testing pad 3 respectively correspond to the concave position and the convex position of the first testing voltage line 21, and the staggered arrangement of the electrostatic discharge unit 4 and the testing pad 3 relative to the first testing voltage line 21 is realized; in addition, the area occupied by each group of test voltage lines 1 and the corresponding test pads 3 and static electricity discharge units 4 can be kept unchanged, and the slice arrangement rate of the display panel in the motherboard comprising the display panel test group is not reduced.
Fig. 4 is a schematic structural diagram of a first test voltage line according to an embodiment of the invention.
A first test voltage line 21 including:
a plurality of first line segments 211 and a plurality of second line segments 212 extending in the first direction X, the plurality of first line segments 211 corresponding to the plurality of electrostatic discharge units 4 one to one, the plurality of second line segments 212 corresponding to the plurality of test pads 3 one to one; in the second direction Y, the distance d1 from the first line segment 211 to the testing pad 4 is smaller than the distance from the second line segment 212 to the testing pad d2, and the second direction Y intersects with the first direction X;
a plurality of connection lines 213, each connection line 213 being connected between the first line segment 211 and the second line segment 212.
In the embodiment provided by the present invention, by setting the distance in the second direction Y of the second line segment 212 corresponding to the test pad 4 in the first test voltage line 21 to be greater than the distance in the second direction Y of the first line segment 211 corresponding to the electrostatic discharge unit 4, the first test voltage line 21 can be made to avoid the test pad 3 at the position corresponding to the test pad 3, thereby reducing the short circuit between the first test voltage line and the test pad 3 due to probe prick of the lighting device.
Fig. 5 is a schematic diagram showing the length relationship between the first line segment and the electrostatic discharge unit, and between the second line segment and the testing pad according to the embodiment of the present invention.
The length L of the first line segment 211 2 Is greater than or equal to the length L of the electrostatic discharge unit 4 in the first direction 1 I.e. L 2 ≥L 1 ；
The length L of the second line segment 212 4 Is greater than the length L of the test pad 3 in the first direction 3 I.e. L 4 >L 3 。
By varying the length L of the first segment 211 2 Is set to be greater than or equal to the length L of the electrostatic discharge unit 4 in the first direction 1 The length L of the second line segment 212 4 Is set to be greater than the length L of the test pad 3 in the first direction 3 The first testing voltage line 21 can bypass the testing pad 3, and the electrostatic discharge unit 4 can avoid the testing pad 3, so as to avoid the first testing voltage line 21 and/or the electrostatic discharge unit 4 from short circuit due to probe bias.
In other embodiments, the length L of the second line segment 212 is assumed to be Δ as the maximum alignment error of the probe with the corresponding test pad 3 4 ≥L 3 +2 Δ, the second segment 212 coincides with an extension of the center line of the corresponding test pad 3 in the second direction Y.
By setting the length of the second segment 212 to be greater than or equal to the sum of the length of the test pad 3 in the first direction X and the maximum alignment error between the probe and the corresponding test pad 3 to be 2 times Δ, the second segment 212 can be always located outside the offset range of the probe offset test pad 3, thereby preventing the first test voltage line 21 from being short-circuited due to probe offset.
Referring to fig. 6, a schematic diagram of a distance between a first line segment 211 and a second line segment 212 according to an embodiment of the present invention is shown, wherein the distance d is between the first line segment and the second line segment 5 Greater than the maximum alignment error delta of the probe with the corresponding test pad.
By the distance d between the first line segment 211 and the second line segment 212 5 The maximum alignment error delta between the probe and the corresponding testing pad is set to be larger than the maximum alignment error delta, so that the second line segment 212 can be positioned outside the deviation range of the probe deviation testing pad 3, thereby preventing the probe from deviatingThe first test voltage line 21 is short-circuited by the offset.
Fig. 7 is a schematic structural diagram of a group of test voltage lines according to an embodiment of the present invention.
Each set of test voltage lines 2 includes a first test voltage line 21 and a second test voltage line 22 which are parallel to each other;
wherein, the second testing voltage line 21 is disposed at a side of the plurality of electrostatic discharge units 4 away from the first testing voltage line 21, and the second testing voltage line 22 is a straight line.
Through letting the first test voltage line 21 of every group test voltage line 2 and the parallel arrangement of second test voltage line 22, and set up second test voltage line 22 into the straight line, can minimize the change to every group test voltage line 2, the wiring of being convenient for.
As shown in fig. 3, when the display panel test set has two rows or two columns of display panels 1, at least one set of test voltage lines 2 is composed of two sets of test voltage lines 2, and the two sets of test voltage lines 2 are symmetrically disposed with respect to the plurality of display panels.
By symmetrically disposing the two sets of test voltage lines 2 on both sides of the display panel 1 having two rows or two columns, it is convenient to arrange the test pads 3 and the electrostatic discharge units 4, and also to wire.
Fig. 8 is a schematic structural diagram of an electrostatic discharge unit according to an embodiment of the present invention.
The electrostatic discharge unit 4 includes:
a first subunit 41 and a second subunit 42 arranged oppositely; the first sub-unit 41 is close to the first test voltage line 21, and the second sub-unit 42 is close to the second test voltage line 22;
the input terminals of the first subunit 41 and the second subunit 42 are electrically connected to one test pad 3;
the output terminal of the first sub-unit 41 is electrically connected to the first test voltage line 21, and the output terminal of the second sub-unit 42 is electrically connected to the second test voltage line 22.
Fig. 9 is a schematic diagram of an electrostatic discharge unit according to an embodiment of the present invention.
The first subunit 41 includes: a first thin film transistor TFT1 and a second thin film transistor TFT 2; a gate and a first pole of the first thin film transistor TFT1 are electrically connected to the test pad 3, a second pole of the first thin film transistor TFT1 is electrically connected to the gate and the first pole of the second thin film transistor TFT2, and a second pole of the second thin film transistor TFT2 is electrically connected to the first test voltage line 21;
the second sub-unit 42 includes a third thin film transistor TFT3 and a fourth thin film transistor TFT 4; a first pole of the third thin film transistor TFT3 is electrically connected to the test pad 3, a gate and a second pole of the third thin film transistor are electrically connected to a first pole of the fourth thin film transistor TFT4, and a gate and a second pole of the fourth thin film transistor TFT4 are electrically connected to the second test voltage line 22.
The first thin film transistors TFT1 to the fourth thin film transistors are of the same type, such as all N-type thin film transistors or all P-type thin film transistors, and fig. 9 is a schematic diagram of all N-type thin film transistors, and when all P-type thin film transistors are used, the connection relationship can be adjusted adaptively.
Based on the same inventive concept, an embodiment of the present invention provides a motherboard, including: a plurality of the above-mentioned display panel test sets are arranged in an array.
Based on the same inventive concept, embodiments of the present invention provide a display panel manufactured by the display panel test set as described above.
The display panel can be a liquid crystal display panel or an OLED display panel, and the display panel can be applied to intelligent wearable equipment, small intelligent equipment and the like.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. The utility model provides a display panel test set, has a plurality of display panels that are array arrangement, many drive wires have among the display panel, its characterized in that includes:
at least one group of test voltage lines disposed on at least one side of the plurality of display panels and extending in a first direction; the group of test voltage lines are used for providing test voltages for a group of display panels arranged along the first direction in the plurality of display panels;
the test pads are arranged between the display panels and the group of test voltage lines and are electrically connected with the drive lines in the display panels one by one, and the test pads are used for being in contact with probes of lighting test equipment;
the electrostatic discharge units are arranged on one side of the test bonding pads, which is far away from the display panels, and are electrically connected with the test bonding pads one by one;
wherein, have one in the test voltage line of a set of be located a plurality of test pads with first test voltage line between a plurality of static discharge unit, a plurality of test pads with a plurality of static discharge unit about first test voltage line dislocation arrangement, just the wiring of first test voltage line is for dodging the wire winding setting of test pad.
2. The display panel test set of claim 1, wherein the first test voltage line is a meander line of a square waveform.
3. The display panel test set of claim 2, wherein the first test voltage line comprises:
a plurality of first line segments and a plurality of second line segments extending along the first direction, the plurality of first line segments corresponding to the plurality of electrostatic discharge units one to one, the plurality of second line segments corresponding to the plurality of test pads one to one; in a second direction, the distance from the first line segment to the test pad is smaller than the distance from the second line segment to the test pad, and the second direction intersects with the first direction;
and each connecting line is connected between the first line segment and the second line segment.
4. The display panel test set of claim 3, wherein the length of the first line segment is greater than or equal to the length of the electrostatic discharge unit in the first direction;
the length of the second line segment is greater than the length of the test pad in the first direction.
5. The panel testing group of claim 3, wherein a distance between the first line segment and the second line segment is greater than a maximum alignment error of the probe with a corresponding test pad.
6. The display panel test set of any of claims 1-5, wherein each set of test voltage lines comprises the first test voltage line and a second test voltage line that are parallel to each other;
wherein the second testing voltage line is disposed at a side of the plurality of static electricity discharging units away from the first testing voltage line, and the second testing voltage line is a straight line.
7. The display panel test set of claim 6, wherein when the display panel test set has two rows or two columns of display panels, the at least one set of test voltage lines consists of two sets of test voltage lines, and the two sets of test voltage lines are symmetrically disposed with respect to the plurality of display panels.
8. The display panel test set according to any one of claims 1 to 5, wherein the electrostatic discharge unit includes:
the first subunit and the second subunit are oppositely arranged; the first sub-unit is close to the first test voltage line, and the second sub-unit is close to the second test voltage line;
the input ends of the first subunit and the second subunit are electrically connected with a test pad;
the output end of the first subunit is electrically connected with the first test voltage line, and the output end of the second subunit is electrically connected with the second test voltage line.
9. A motherboard comprising a plurality of test sets of display panels as claimed in any one of claims 1 to 8 arranged in an array.
10. A display panel produced by the display panel test set according to any one of claims 1 to 8.
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