CN114996199A - Many-core route mapping method, device, equipment and medium - Google Patents
Many-core route mapping method, device, equipment and medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
Abstract
The embodiment of the invention discloses a many-core route mapping method, a device, equipment and a medium. The method comprises the following steps: determining a target transmission clock of routing data to be planned; determining at least one target time slice to which the target transmission clock belongs from a plurality of time slices; and determining a routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to perform routing mapping. According to the technical scheme, the routing paths are respectively planned according to the time slices, so that the utilization rate of network-on-chip routing resources is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of many-core chips, in particular to a many-core route mapping method, device, equipment and medium.
Background
In many-core (including multi-core) Chip design, NOC (Network On Chip) is a common scheme for realizing communication between cores, wherein NOC performance is a key for improving the performance of the whole Chip, and routing mapping has a great influence On the communication efficiency of NOC. How to improve the utilization rate of routing resources is an urgent problem to be solved by many-core routing mapping.
Disclosure of Invention
Embodiments of the present invention provide a many-core route mapping method, apparatus, device, and medium, so as to improve a utilization rate of a route resource when many-core routes are mapped.
In a first aspect, an embodiment of the present invention provides a many-core route mapping method, including:
determining a target transmission clock of routing data to be planned;
determining at least one target time slice to which the target transmission clock belongs from a plurality of time slices;
and determining a routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to perform routing mapping.
In a second aspect, an embodiment of the present invention further provides a many-core route mapping apparatus, including:
the transmission clock determining module is used for determining a target transmission clock of the routing data to be planned;
a time slice determining module, configured to determine, from a plurality of time slices, at least one target time slice to which the target transmission clock belongs;
and the routing path planning module is used for determining the routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to carry out routing mapping.
In a third aspect, an embodiment of the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the many-core route mapping method according to any embodiment of the present invention when executing the program.
In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the method for mapping routes of many cores according to any embodiment of the present invention.
In the technical scheme of the embodiment of the invention, at least one target time slice corresponding to the route data to be planned is determined according to the target transmission clock of the route data to be planned, and then the route path of the route data to be planned in each target time slice is determined according to the current planned route resource corresponding to each target time slice so as to carry out route mapping. In the technical scheme, the routing paths are respectively planned according to the time slices, so that the phenomena of partial path blockage and partial routing idleness caused by different routing times can be avoided, routing resources are fully utilized to the greatest extent, the utilization rate of network-on-chip routing resources is improved, and the routing efficiency can be improved.
Drawings
FIG. 1 is a schematic diagram of a network on chip in an embodiment of the invention;
FIG. 2 is a flowchart of a method for mapping routes of many cores according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of time slice division and routing path planning according to a first embodiment of the present invention;
FIG. 4 is a flowchart of a method for route mapping for many cores according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a many-core route mapping apparatus according to a third embodiment of the present invention;
fig. 6 is a schematic diagram of a hardware structure of an electronic device in the fourth embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Before discussing exemplary embodiments in greater detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the operations (or steps) as a sequential process, many of the operations can be performed in parallel, concurrently or simultaneously. In addition, the order of the operations may be re-arranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figure. The processes may correspond to methods, functions, procedures, subroutines, and the like.
In the related art, in the route planning process, the route of the route is usually planned based on the principle that the route amount of a single route is minimum on the premise of the shortest route. In the network on chip, there are usually multiple paths from a source core node to a target core node, where the shortest path between the source core node and the target core node refers to a path with the least hop count of the core node, and a single path refers to a path between two adjacent core nodes.
When the whole route is planned, the route quantity between every two core nodes is almost the same. However, once the routing path is determined, in the actual data transmission process, partial path blocking and partial routing idle may occur due to different routing times, so that the routing resources of the network on chip are not fully utilized, and the routing efficiency is low. Taking the network on chip shown in fig. 1 as an example, assuming that the planned path from the source core node A to the target core node D is (A-B-C-D each indicates A core node on A many-core chip), the planned path from the source core node S to the target core node D is S-A-H-G-D, and the planned path from the source core node A to the target core node E is A-H-I-F-E, if the route of the path A-B-C-D has completed all datA transmission in the first 100 clocks (clk), all the datA transmission is in an idle state in the following clocks, and the route of the path S-A-H-G-D and the route of the path A-H-I-F-E both transmit datA between the 200 th clock to the 300 th clock, two routes will be blocked between paths a-H while paths a-B-C-D are still idle and the routing resources are obviously not fully utilized. At this time, if the planned path from the source core node S to the target core node D is S-A-B-C-D, the utilization rate of the routing resources can be obviously improved, and path congestion is avoided.
The embodiment of the disclosure provides a many-core route mapping method, which comprises the steps of determining a target transmission clock of route data to be planned; determining at least one target time slice to which the target transmission clock belongs from a plurality of time slices; and determining a routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to perform routing mapping, so that the utilization rate of the routing resource is obviously improved, and the communication efficiency of the many-core system is improved.
Example one
Fig. 2 is a flowchart of a many-core route mapping method according to an embodiment of the present invention, where the present embodiment is applicable to a case where a route path of a many-core network-on-chip is planned, and the method may be executed by a many-core route mapping apparatus according to an embodiment of the present invention, where the apparatus may be implemented in a software and/or hardware manner, and may generally be integrated in an electronic device.
As shown in fig. 2, the method for mapping a many-core route provided in this embodiment includes:
s110, determining a target transmission clock of the routing data to be planned.
The routing data to be planned refers to data which is transmitted from a source core node to a target core node on a many-core chip and needs to be subjected to on-chip network routing path planning. The core node refers to a node corresponding to one core in the many-core chip, and the source core node and the target core node are start and stop core nodes of the routing data to be planned.
The target transmission clock of the route data to be planned refers to a clock range occupied by the route data to be planned when the route data to be planned is transmitted in the network on chip, and may be, for example, a transmission start-stop clock, a transmission start clock, and a transmission clock duration. The transmission clock duration may be determined according to a quotient of a data amount of the route data to be planned and the route bandwidth. Illustratively, a certain route to be planned starts to be transmitted when the clock (clk) is 20, and 20 clocks need to be transmitted.
And S120, determining at least one target time slice to which the target transmission clock belongs from the plurality of time slices.
The time slices are obtained by splitting the clock, and each time slice comprises at least one clock. For example, the plurality of time slices may be obtained by uniformly dividing all clocks, the number of time slices is related to the number of clocks included in each time slice, and the smaller the number of clocks included in each time slice is, the larger the number of time slices is.
In an alternative embodiment, the number of clocks included in different time slices is not exactly the same. In the plurality of time slices obtained by division, the number of clocks included in any two time slices may be the same or different.
After the clocks respectively included in each time slice are determined, the target transmission clock is compared with the clocks respectively included in each time slice, so that each time slice to which the target transmission clock belongs can be determined, and the time slice to which the target transmission clock belongs is called as a target time slice.
For example, the target transmission clocks are from 20 to 40, the first time slice includes clocks from 0 to 10, the second time slice includes clocks from 11 to 30, and the third time slice includes clocks from 31 to 40, so that the target time slices to which the target transmission clocks belong are the second time slice and the third time slice.
S130, according to the current planning routing resource corresponding to each target time slice, determining a routing path of the routing data to be planned in each target time slice so as to perform routing mapping.
When the route data to be planned is transmitted only in a part of clocks, only the route path of the route data to be planned is needed to be determined in the corresponding target time slice, the route path of the route data to be planned is not needed to be determined in the other time slices, and the route resources in the other time slices are not occupied.
And planning the routing path of the routing data to be planned respectively aiming at each target time slice. And synthesizing the planned routing paths in each target time slice, namely the finally determined routing path of the routing data to be planned.
Optionally, when the number of the target time slices is multiple, the routing paths of the route data to be planned in different target time slices are not completely the same. For a plurality of target time slices, the routing paths of the routing data to be planned in any two target time slices can be the same or different. For example, the route path of the route data to be planned from the source core node a to the target core node D in the second time slice is a-B-C-D, and the route path of the route data to be planned from the source core node a to the target core node D in the third time slice is a-H-G-D.
The route path of the route data to be planned in each target time slice is determined by referring to the current planned route resource in the target time slice. The current planned route resource refers to a situation that a route at the current moment is planned, and specifically refers to a planned route path and a route amount thereof.
That is, when determining the routing path of the routing data to be planned in a certain target time slice, only the current planned routing resource in the target time slice needs to be considered, and the current planned routing resource in other target time slices does not need to be considered.
When determining the routing path of the routing data to be planned in the target time slice according to the current planned routing resource corresponding to the target time slice, selecting the routing path by using the principle that the total amount of the routing data of a single path is the minimum, wherein the single path is the path between two adjacent cores.
Optionally, determining a routing path of the to-be-planned routing data in the target time slice according to the current planned routing resource corresponding to the target time slice may specifically be:
determining the total amount of the current planning routing data of each single path in the target time slice; and according to a target path selection strategy, determining the routing path of the routing data to be planned in the target time slice according to the total amount of the current planned routing data of each single path in the target time slice.
The total amount of currently planned routing data refers to the total amount of currently planned routing data, for example, if a piece of routing data with a data volume of 10 is planned on a single path between the core node a and the core node H, and a piece of routing data with a quantity of 15 is planned on the single path between the core node a and the core node H, the total amount of currently planned routing data of the single path between the core node a and the core node H is 25.
The target path selection policy may be any policy for performing path selection on a to-be-planned route in the network on chip, and is intended to improve the utilization rate of routing resources and avoid path congestion, which is not specifically limited in this embodiment.
For example, the target path selection policy may be based on the minimum number of node hops from the source core node to the target core node, and preferentially select a path with the minimum total amount of single path routing data. When the route between the source core node and the target core node is planned, the approximate direction of the route path can be determined according to the principle that the hop count between the source core node and the target core node is minimum, and then the final route path of the route data to be planned in the target time slice is determined according to the principle that the total amount of single path route data is minimum.
Specifically, each single path between the source core node and the target core node of the routing data to be planned in the network on chip may be sequentially determined according to the target path selection policy, and the single paths are integrated to serve as the routing path of the routing data to be planned in the target time slice.
Taking planning a route between a source core node A and a target core node D as an example, assuming that the hop count of the core node from the core node A to the core node D through the core node H is equal to and minimum of the hop count of the core node from the core node A to the core node D through the core node B, a route path from the core node A to the core node D through the core node H and a route path from the core node A to the core node D through the core node B can be selected; when determining whether to select a single path between the core node a and the core node H or a single path between the core node a and the core node B, preferentially selecting the single path with the smallest total amount of routing data, and if the total amount of routing data of the core node a via the single path between the core nodes B is the smallest, selecting the single path between the core node a and the core node B, that is, planning the routing path between the source core node a and the target core node D as the routing path between the core node a via the core node B to the core node D.
Further, according to a target path selection policy, determining a routing path of the to-be-planned routing data in the target time slice according to the total amount of the currently planned routing data of each single path in the target time slice, which may specifically be:
determining a horizontal single path and a vertical single path corresponding to a current core node aiming at the current core node related to a routing path of routing data to be planned in a target time slice;
if the total amount of the current planning routing data of the single path in the horizontal direction and the single path in the vertical direction is not equal, determining a next core node corresponding to the current core node according to the single path with the minimum total amount of the current planning routing data;
and if the total amount of the current planned routing data of the single path in the horizontal direction and the single path in the vertical direction is equal, determining a next core node corresponding to the current core node according to the single path in the horizontal direction or the single path in the vertical direction.
After determining the current core node of the routing data to be planned (the first current core node is the source core node of the routing data to be planned):
first, a horizontal single path and a vertical single path corresponding to a current core node are determined. The single path in the horizontal direction refers to a single horizontal left path or a single horizontal right path determined according to the principle that the hop count between the source core node and the target core node is minimum; the single vertical path refers to a single vertical upward path or a single vertical downward path determined according to the principle that the hop count between the source core node and the target core node is minimum.
Secondly, judging whether the total amount of the currently planned routing data of the horizontal single path and the vertical single path corresponding to the current core node is equal or not, if not, taking the single path with the minimum total amount of the currently planned routing data as a planned single path, determining a next core node corresponding to the current core node according to the single path, and taking the next core node as the current core node again; if so, selecting a horizontal single path or a vertical single path as a planned single path according to a preset priority, determining a next core node corresponding to the current core node according to the single path, and re-using the next core node as the current core node.
And repeatedly executing the process aiming at the redetermined current core node until the next core node corresponding to the current core node is determined to be the target core node of the routing data to be planned, so as to finish the planning of the routing path of the routing data to be planned in the target time slice.
Taking the network on chip shown in fig. 1 as an example, assume that a source core node of data to be planned is a core node a, a target core node is a core node D, a routing data amount is 20, and a total amount of currently planned routing data of each single path in a target time slice is: the total amount of the currently planned routing data of a single path from the core node S to the core node a is 10, the total amount of the currently planned routing data of a single path from the core node a to the core node H is 10, the total amount of the currently planned routing data of a single path from the core node H to the core node G is 10, and the total amount of the currently planned routing data of a single path from the core node G to the core node D is 10. The total amount of the currently planned routing data of a single path between the core node a and the core node B is 0, the total amount of the currently planned routing data of a single path between the core node B and the core node C is 0, and the total amount of the currently planned routing data of a single path between the core node C and the core node D is 0.
Firstly, taking a core node A as a current core node, and determining that a single path in the horizontal direction corresponding to the core node A is a single path from the core node A to a core node H and a single path in the vertical direction corresponding to the core node A is a single path from the core node A to a core node B according to the principle that the hop count between a source core node and a target core node is minimum (the node hop count is three hops).
Secondly, since the total amount of the currently planned routing data of the horizontal single path corresponding to the core node a is 10 and the total amount of the currently planned routing data of the vertical single path corresponding to the core node a is 0, it is determined that the total amounts of the currently planned routing data of the horizontal single path corresponding to the core node a and the current planned routing data of the vertical single path are not equal to each other, the vertical single path corresponding to the core node a is taken as the planned single path, a next core node B corresponding to the core node a is determined according to the single path, and the current core node is updated from the core node a to the core node B.
And circulating in this way, planning several single paths after the single path between the core node A and the core node B as the single path between the core node B and the core node C and the single path between the core node C and the core node D, and thus, the routing path of the routing data to be planned in the target time slice is the core node A-the core node B-the core node C-the core node D.
On the basis of the target path selection policy, the target path selection policy may further include: if the path with the minimum total amount of the route data of the single path is preferentially selected to meet the preset overload condition on the basis of the minimum node hop count between the source core node and the target core node, the node hop count and the total amount of the currently planned route data can be comprehensively considered, alternative route paths of the route data to be planned are re-determined, the alternative route paths are evaluated, and one route path with the optimal evaluation result is selected from the alternative route paths to serve as a final route path of the route data to be planned.
The overload condition may be, for example, that the total amount of the path routing data is greater than a set number threshold, or that a ratio of the total amount of the path routing data to the to-be-planned routing data reaches a set target value, and the like, which is not specifically limited in this embodiment.
For example, the evaluation of the alternative routing paths may be performed by scoring the alternative routing paths according to respective specific gravity of the node hop count and the total amount of currently planned routing data, and obtaining a routing path with an optimal evaluation result according to a scoring result; and evaluating the alternative routing paths, or scoring the alternative routing paths according to a preset evaluation function, and obtaining a routing path with an optimal evaluation result according to a scoring result. How to evaluate the alternative routing path may be determined according to practical applications, and this embodiment is not particularly limited.
Still taking the network on chip shown in fig. 1 as an example, assuming that a source core node of data to be planned is a core node a, a target core node is a core node D, and a path with the least node hop count between the source core node and the target core node is a path a-B-C-D and a path a-H-G-D, if one of the two paths determined according to the principle that the total amount of routing data of a single path is the smallest meets a preset overload condition, if the total amount of routing data of the path is greater than a set number threshold, it is necessary to re-determine an alternative routing path of the routing data to be planned by comprehensively considering the node hop count and the total amount of routing data of the currently planned path, at this time, a path with a smaller total amount of routing data of the single path can be selected as an alternative routing path, for example, a path with a total amount of routing data of the single path being zero on the premise of increasing the node hop count of the path, assuming that the selected alternative routing paths are path a-S-J-K-C-D and path a-H-I-F-E-D, the two paths can be evaluated, and the optimal path to be evaluated is taken as the final routing path of the routing data to be planned.
When a target transmission clock of the route data to be planned belongs to a plurality of target time slices, a route path of the route data to be planned in each target time slice needs to be determined in sequence as a data transmission path.
And after the routing path of the routing data to be planned is planned, continuing to plan the routing paths of other routing data to be planned until the planning of the routing paths of all the routing data to be planned is finished.
After the whole routing path planning is finished, the total amount of routing between every two core nodes in each time slice is almost, and after the total amount of routing is mapped to the many-core chip, the corresponding data packet can be transmitted according to the determined routing path.
Further, the plurality of time slices can be adjusted, and the clock included in each time slice is updated.
The smaller the time slice is, the more the number of the time slices is, the finer the routing path is planned, and the higher the routing utilization rate is. However, the number of time slices is directly related to the number of routing table entries, and the number of routing paths within each time slice is directly related to the number of routes in the routing table entries. Thus, the size of the memory occupied by the routing instructions and the size of the time slices can be balanced by adjusting the time slices.
In an alternative embodiment, adjusting the sliced time slice may include: and determining the target total number of the time slices according to the size of the routing table and/or the number of the routing strips, and splitting or combining the time slices obtained by splitting according to the target total number.
The target total number of the time slices can be determined according to the balance strategy of the size of the storage space occupied by the routing instruction and the size of the time slices, and the time slices obtained through segmentation are split or combined according to the difference value of the current number of the time slices and the target total number.
For example, two time slices with a smaller task amount may be combined into one time slice, or a larger time slice may be divided into a plurality of time slices.
In another alternative embodiment, adjusting the sliced time slice may include: and if the planned routing paths in the adjacent time slices are consistent, combining the adjacent time slices into one time slice.
If the routing paths in the adjacent time slices are selected to be completely consistent, the adjacent time slices can be combined into one time slice, so that the table entries of the routing table are reduced, the number of the routing entries is optimized, and the effect of reducing the size of the storage space occupied by the routing instruction is achieved.
In the technical scheme of the embodiment of the invention, at least one target time slice corresponding to the route data to be planned is determined according to the target transmission clock of the route data to be planned, and then the route path of the route data to be planned in each target time slice is determined according to the current planned route resource corresponding to each target time slice so as to carry out route mapping. In the technical scheme, the routing paths are respectively planned according to the time slices, so that the phenomena of partial path blockage and partial routing idleness caused by different routing times can be avoided, routing resources are fully utilized to the greatest extent, the utilization rate of network-on-chip routing resources is improved, and the routing efficiency can be improved.
For example, assuming that 10 time slices are divided, as shown in fig. 3 (only a part of the time slices are shown in the figure), the transmission data from the core node S to the core node D may be transmitted in the 1 st time slice, and the path in the last 9 time slices (not fully shown in the figure) in the prior art may be occupied, but actually the routing path in the following time slices is empty. Then, according to the total data volume of all time slices, the path in all time slices is exclusive, and the rest transmission data can only be transmitted by detour, which brings extra route resource consumption. In the technical solution provided in this embodiment, the routing path from the core node S to the core node D in the next 9 time slices is unoccupied, and other transmission data (assumed to be transmission data from the core node O to the core node P) passing through the core node S and the core node D can be used, so that the routing utilization rate is improved, and congestion is reduced. Furthermore, the technical scheme of the embodiment plans the routing path for each time slice independently, so that the routing efficiency is improved, detour and congestion are reduced, the total routing time is also reduced, and the information throughput rate is improved.
Example two
Fig. 4 is a flowchart of a many-core route mapping method according to a second embodiment of the present invention, which is embodied on the basis of the foregoing embodiment, where the method further includes: time slices are sliced and the clock included in each time slice is determined separately.
As shown in fig. 4, the method for mapping a many-core route provided in this embodiment includes:
s210, determining a target transmission clock of the routing data to be planned.
And S220, cutting the time slices, and respectively determining the clock included in each time slice.
Before determining the target time slice to which the target transmission clock belongs, the time slices may be first sliced, and the clock corresponding to each time slice is determined.
The clock can be evenly divided to obtain a plurality of time slices, and the number of the clocks in each time slice is the same; the clock can also be non-uniformly divided to obtain a plurality of time slices, and the number of the clocks included in different time slices is not completely the same.
In an alternative embodiment, the time slice may specifically be: and carrying out time slice segmentation according to the target transmission clock and the data volume of each piece of routing data to be planned.
The data to be routed can be counted, and the number of the time slices is determined according to the target transmission clock and the data volume of the data to be routed, so that the time slices are segmented.
For example, a piece of data to be routed with the largest data amount may be selected, and the target transmission clock of the piece of data to be routed may be sliced as one time slice or multiple time slices.
For another example, several pieces of data to be routed with smaller data amount may be selected, and if the target transmission clocks of the several pieces of data to be routed are close to or have overlapping clocks, the target transmission clocks of the several pieces of data to be routed are integrated as one time slice or multiple time slices for segmentation.
For another example, if the target transmission clock of the data to be routed from the core node a to the core node D is the first N clocks, the first N clocks may be divided into a time slice; the target transmission clock of the data to be routed from the core node S to the core node D is the last N clocks, and then the last N clocks can be sliced into a time slice.
The time slice splitting manner may be determined according to an actual situation according to the target transmission clock and the data amount of each piece of routing data to be planned, which is not specifically limited in this embodiment.
In another optional implementation manner, the time slice may be further specifically: and carrying out time slice segmentation according to the target transmission clock and the start-stop core node of each piece of routing data to be planned.
If multiple pieces of routing data to be planned with the same start-stop core node exist in the pieces of routing data to be planned, that is, multiple pieces of routing data to be planned with the same source core node and target core node, the time slice can be segmented according to the target transmission clocks of the multiple pieces of routing data to be planned.
For example, if the start-stop core nodes of two pieces of route data to be planned are the same, and there is no overlapping clock between the target transmission clocks of the two pieces of route data to be planned, the target transmission clocks of the two pieces of route data to be planned can be respectively split as a time slice.
Further, performing time slice segmentation according to the target transmission clock and the start-stop core node of each piece of routing data to be planned may include: and if the starting and stopping core nodes of the two pieces of routing data to be planned are the same, determining an overlapped clock according to the target transmission clocks of the two pieces of routing data to be planned, and dividing the overlapped clock into time slices.
If the start-stop core nodes of two pieces of routing data to be planned are the same and an overlapped clock exists between the target transmission clocks of the two pieces of routing data to be planned, the overlapped clock can be used as a time slice to be split. Furthermore, the non-overlapping clocks in the target transmission clocks of the two pieces of routing data to be planned can be respectively used as a time slice to be segmented.
For example, the starting and ending core nodes of two pieces of routing data to be planned are the core node S and the core node D, wherein the target transmission clock of one piece of routing data to be planned is the 20 th clock to the 40 th clock, and the target transmission clock of the other piece of routing data to be planned is the 30 th clock to the 50 th clock, so that the overlapped clocks of the target transmission clocks of the two pieces of routing data to be planned are the 30 th clock to the 40 th clock, and the 30 th clock to the 40 th clock can be divided as one time slice. In addition, the 20 th clock to the 30 th clock may be sliced as one time slice, and the 40 th clock to the 50 th clock may be sliced as one time slice.
That is, in time slice slicing, the principle is that the overlapping time of different routes passing through the same path is minimized. Furthermore, in the time slice corresponding to the 20 th clock to the 30 th clock and the time slice corresponding to the 40 th clock to the 50 th clock, the two pieces of data to be routed can multiplex the same optimal path in a time-sharing manner, in the time slice corresponding to the 30 th clock to the 40 th clock, only one piece of data to be routed plans the optimal path, and the other piece of data to be routed plans the suboptimal path again.
And S230, determining at least one target time slice to which the target transmission clock belongs from the plurality of time slices.
S240, according to the current planning route resource corresponding to each target time slice, determining the route path of the route data to be planned in each target time slice so as to carry out route mapping.
Furthermore, the time slice obtained by splitting can be adjusted to balance the size of the storage space occupied by the routing instruction and the size of the time slice.
For those parts of this embodiment that are not explained in detail, reference is made to the aforementioned embodiments, which are not repeated herein.
According to the technical scheme, the routing congestion can be reduced on the premise that each routing path is the shortest path, so that the routing efficiency is improved.
EXAMPLE III
Fig. 5 is a schematic structural diagram of a many-core route mapping apparatus according to a third embodiment of the present invention, which is applicable to a case of performing route planning on a many-core network-on-chip, and the apparatus may be implemented in a software and/or hardware manner, and may be generally integrated in an electronic device. As shown in fig. 5, the apparatus includes: a transmission clock determination module 310, a time slice determination module 320, and a routing path planning module 330.
Wherein, the first and the second end of the pipe are connected with each other,
a transmission clock determining module 310, configured to determine a target transmission clock of the to-be-planned routing data;
a time slice determining module 320, configured to determine at least one target time slice to which the target transmission clock belongs from a plurality of time slices;
and the routing path planning module 330 is configured to determine, according to the currently planned routing resource corresponding to each target time slice, a routing path of the to-be-planned routing data in each target time slice, so as to perform routing mapping.
In the technical scheme of the embodiment of the invention, at least one target time slice corresponding to the route data to be planned is determined according to the target transmission clock of the route data to be planned, and then the route path of the route data to be planned in each target time slice is determined according to the current planned route resource corresponding to each target time slice so as to carry out route mapping. In the technical scheme, the routing paths are respectively planned according to the time slices, so that the phenomena of partial path blockage and partial routing idleness caused by different routing times can be avoided, routing resources are fully utilized to the greatest extent, the utilization rate of network-on-chip routing resources is improved, and the routing efficiency can be improved.
Optionally, the number of the target time slices is multiple, where the routing paths of the to-be-planned routing data in different target time slices are not completely the same.
Optionally, the apparatus further comprises: and the time slice dividing module is used for dividing the time slices and respectively determining the clock included in each time slice.
Optionally, the number of clocks included in different time slices is not exactly the same.
Optionally, the time slice segmentation module is specifically configured to perform time slice segmentation according to a target transmission clock and a data size of each piece of routing data to be planned; and/or performing time slice segmentation according to the target transmission clock of each piece of routing data to be planned and the start-stop core node.
Optionally, the time slice splitting module is specifically configured to determine an overlapping clock according to the target transmission clocks of the two pieces of routing data to be planned if the start-stop core nodes of the two pieces of routing data to be planned are the same, and split the overlapping clock into one time slice.
Optionally, the apparatus further comprises: and the time slice adjusting module is used for adjusting the time slices and updating the clock included in each time slice.
Optionally, the time slice adjusting module is specifically configured to determine a target total number of time slices according to the size of the routing table and/or the number of routing strips, and split or combine the time slices obtained by splitting according to the target total number; and/or if the planned routing paths in the adjacent time slices are consistent, combining the adjacent time slices into one time slice.
Optionally, the route path planning module 330 is specifically configured to determine a total amount of currently planned route data of each single path in the target time slice; wherein the single path is a path between two adjacent cores; and according to a target path selection strategy, determining the routing path of the routing data to be planned in the target time slice according to the total amount of the current planned routing data of each single path in the target time slice.
Further, the routing path planning module 330 is specifically configured to determine, for a current core node related to a routing path of the routing data to be planned within the target time slice, a single horizontal-direction path and a single vertical-direction path corresponding to the current core node; if the total amount of the current planning routing data of the horizontal single path and the vertical single path is not equal, determining a next core node corresponding to the current core node according to the single path with the minimum total amount of the current planning routing data; and if the total amount of the current planned routing data of the single path in the horizontal direction and the single path in the vertical direction is equal, determining a next core node corresponding to the current core node according to the single path in the horizontal direction or the single path in the vertical direction.
The many-core route mapping device can execute the many-core route mapping method provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the executed many-core route mapping method.
Example four
Fig. 6 is a schematic diagram of a hardware structure of an electronic device according to a fourth embodiment of the present invention. As shown in fig. 6, the electronic apparatus includes:
one or more processors 410, one processor 410 being illustrated in FIG. 6;
and a memory 420.
The processor 410 and the memory 420 in the electronic device may be connected by a bus or other means, and fig. 6 illustrates the connection by the bus as an example.
The memory 420 is used as a non-transitory computer-readable storage medium, and can be used to store a software program, a computer-executable program, and program instructions corresponding to a multi-core route mapping method in the embodiment of the present invention, including:
determining a target transmission clock of the routing data to be planned;
determining at least one target time slice to which the target transmission clock belongs from a plurality of time slices;
and determining the routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to carry out routing mapping.
The processor 410 executes various functional applications of the chip and data processing by executing software program instructions stored in the memory 420, namely, implementing a many-core route mapping method in any embodiment of the above method.
The memory 420 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to use of the chip, and the like. Further, the memory 420 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device.
EXAMPLE five
An embodiment of the present invention further provides a storage medium containing computer-executable instructions, where the computer-executable instructions are executed by a processor to implement a many-core route mapping method, where the method includes:
determining a target transmission clock of routing data to be planned;
determining at least one target time slice to which the target transmission clock belongs from a plurality of time slices;
and determining the routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to carry out routing mapping.
Optionally, the computer-executable instruction, when executed by the processor, may be further used to implement a technical solution of a many-core route mapping method provided in any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes instructions for enabling a chip to execute the method according to the embodiments of the present invention.
It should be noted that, in the embodiment of the many-core route mapping apparatus, each unit and each module included in the many-core route mapping apparatus are only divided according to functional logic, but are not limited to the above division as long as the corresponding function can be implemented; in addition, specific names of the functional units are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (13)
1. A many-core route mapping method is characterized by comprising the following steps:
determining a target transmission clock of the routing data to be planned;
determining at least one target time slice to which the target transmission clock belongs from a plurality of time slices;
and determining a routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to perform routing mapping.
2. The method according to claim 1, wherein the number of the target time slices is multiple, and wherein the routing paths of the routing data to be planned in different target time slices are not identical.
3. The method of claim 1, further comprising:
time slices are sliced and the clock included in each time slice is determined separately.
4. The method of claim 3, wherein the number of clocks included in different time slices is not exactly the same.
5. The method of claim 3, wherein the slicing the time slice comprises:
carrying out time slice segmentation according to the target transmission clock and the data volume of each piece of routing data to be planned; and/or the presence of a gas in the atmosphere,
and carrying out time slice segmentation according to the target transmission clock and the start-stop core node of each piece of routing data to be planned.
6. The method of claim 5, wherein performing time slice slicing according to the target transmission clock and start-stop core nodes of each piece of the routing data to be planned comprises:
and if the starting and stopping core nodes of the two pieces of routing data to be planned are the same, determining an overlapped clock according to the target transmission clocks of the two pieces of routing data to be planned, and dividing the overlapped clock into time slices.
7. The method of claim 1, further comprising:
and adjusting the plurality of time slices and updating the clock included in each time slice.
8. The method of claim 7, wherein adjusting the sliced timeslices comprises:
determining the target total number of the time slices according to the size of the routing table and/or the number of the routing strips, and splitting or combining the time slices obtained by splitting according to the target total number; and/or the presence of a gas in the atmosphere,
and if the planned routing paths in the adjacent time slices are consistent, combining the adjacent time slices into one time slice.
9. The method of claim 1, wherein determining the routing path of the routing data to be planned within the target time slice according to the currently planned routing resource corresponding to the target time slice comprises:
determining the total amount of the current planning routing data of each single path in the target time slice; wherein the single path is a path between two adjacent cores;
and according to a target path selection strategy, determining the routing path of the routing data to be planned in the target time slice according to the total amount of the current planned routing data of each single path in the target time slice.
10. The method according to claim 9, wherein determining the routing path of the routing data to be planned in the target time slice according to the total amount of currently planned routing data of each single path in the target time slice according to a target path selection policy comprises:
determining a single path in the horizontal direction and a single path in the vertical direction corresponding to the current core node aiming at the current core node related to the routing path of the routing data to be planned in the target time slice;
if the total amount of the current planned routing data of the horizontal single path and the vertical single path is not equal, determining a next core node corresponding to the current core node according to the single path with the minimum total amount of the current planned routing data;
and if the total amount of the current planning routing data of the horizontal single path and the vertical single path is equal, determining a next core node corresponding to the current core node according to the horizontal single path or the vertical single path.
11. A many-core route mapping apparatus, comprising:
the transmission clock determining module is used for determining a target transmission clock of the routing data to be planned;
a time slice determining module, configured to determine, from a plurality of time slices, at least one target time slice to which the target transmission clock belongs;
and the routing path planning module is used for determining the routing path of the routing data to be planned in each target time slice according to the current planned routing resource corresponding to each target time slice so as to carry out routing mapping.
12. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1-10 when executing the program.
13. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-10.
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| US20080123682A1 (en) * | 2006-06-27 | 2008-05-29 | Justin Michael Yackoski | Method for scheduling transmissions in an ad hoc network |
| CN102799560A (en) * | 2012-09-07 | 2012-11-28 | 上海交通大学 | Dynamic reconfigurable subnetting method and system based on network on chip |
| CN106168940A (en) * | 2016-06-22 | 2016-11-30 | 中国科学院计算技术研究所 | The road network implementation method of high density network-on-chip and device |
| US10938715B2 (en) * | 2019-06-11 | 2021-03-02 | Mellanox Technologies Tlv Ltd. | Throughput in a crossbar network element by modifying mappings between time slots and ports |
| CN112003787B (en) * | 2020-08-14 | 2022-09-09 | 北京灵汐科技有限公司 | Routing path determining method, device, control equipment and storage medium |
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| CN116501504A (en) * | 2023-06-27 | 2023-07-28 | 上海燧原科技有限公司 | Space-time mapping method and device for data stream, electronic equipment and storage medium |
| CN116501504B (en) * | 2023-06-27 | 2023-09-12 | 上海燧原科技有限公司 | Space-time mapping method and device for data stream, electronic equipment and storage medium |
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