CN114995750A - Method, device, storage medium and storage equipment for improving reliability of flash memory data - Google Patents
Method, device, storage medium and storage equipment for improving reliability of flash memory data Download PDFInfo
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- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
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Abstract
The invention relates to the technical field of data storage, and provides a method, a device, a storage medium and a storage device for improving the reliability of flash memory data, wherein the method comprises the following steps: erasing a target storage unit to which data is to be written; when data writing is carried out on the erased target storage unit, if the current storage state to be written is the lowest state, the lowest state programming is carried out on the target storage unit by adopting a preset optimized programming verification voltage, and the optimized programming verification voltage is lower than the erasing verification voltage corresponding to the erasing operation. After the target storage unit of the data to be written is subjected to erasing operation, the storage unit with the lowest written data state is programmed by adopting the preset optimized programming verification voltage, so that the E state has no extremely low threshold voltage after the data is written, the problem that the data Retention time is influenced by the matching of the extremely low threshold voltage storage unit and the adjacent layer high storage state is solved, and the Retention characteristic of the data is improved.
Description
Technical Field
The present invention relates to the field of data storage technologies, and in particular, to a method, an apparatus, a storage medium, and a storage device for improving data reliability of a flash memory.
Background
The NAND flash memory, as a mainstream storage medium at present, has the advantages of high read-write speed, high storage capacity, small power consumption, and the like. Two main device structure types of 3D-NAND are Floating Gate (Floating Gate) and Charge Trap (Charge Trap) at present. The memory device is comprised of a conductive channel, a tunneling layer, a memory layer, a blocking layer, and a gate word line. The conductive channel is a circulation path for conducting electrons or holes, and the upper part and the lower part of the conductive channel are respectively communicated with a Drain end (Drain) and a Source end (Source) of the storage device; the tunneling layer and the blocking layer play a role in blocking the charges of the storage layer and prevent the charges of the storage layer from escaping towards the conducting channel or the grid electrode; and the storage layer is a carrier for NAND stored information, and represents different stored information by storing the amount of charges. The storage layers corresponding to each layer of word lines in the floating gate structure are mutually independent, and the storage layers between different word line layers in the charge trap structure are communicated. For the charge trap structure, shallow level traps are also present while deep level traps are present in the storage layer, and the stored charges trapped by the shallow level traps are easy to break away and bound to escape, and the escaped charges can drift to adjacent word lines through the connected storage layer. The result of the drift is that the stored information of this layer is lost and therefore the data Retention capability (retentivity) of the charge well structure is relatively poor. The flash memory represents different memory states according to the amount of the stored charge of the memory layer, and fig. 1 is a distribution diagram of threshold voltages of the flash memory for unit memory, two-bit memory and three-bit memory, as shown in fig. 1, only two memory states exist for unit memory (SLC: Single-Level Cell): an erased state (E) and a programmed state (P), the programmed state having a higher number of electrons in the memory layer than in the erased state; and two-bit memory (MLC: Multi-Level Cell) has 1 erased state (E) and 3 programmed states (P1, P2, P3), and the order of arrangement of electrons of the memory layer is P3> P2> P1> E; three-bit memory (TLC: Trinary-Level Cell) has 1 erased state (E) and 7 programmed states (P1, P2, P3, P4, P5, P6, P7), and the order of how many electrons are arranged in the memory layer is P7> P6> P5> P4> P3> P2> P1> E. The drift speed of the charge of the storage layer of the charge trap structure along the direction of the storage layer is greatly related to the storage state of an adjacent word line. Taking the three-bit storage mode as an example, the worst case is that the current storage layer is the highest state P7 state. And the upper and lower adjacent storage layers are in the lowest state E state, and because the adjacent storage layers have the largest concentration difference of stored charges and the largest potential difference of stored charges under the condition, the stored charges have the most serious drift. Fig. 2 is a schematic diagram showing the initial threshold voltage distribution of the NAND write TLC and the threshold voltage distribution after a period of data retention, as shown in fig. 2, the solid line is the initial threshold voltage distribution of the NAND write TLC, the dotted line is the threshold voltage distribution after a period of data retention, the shift of the P7 threshold voltage distribution to the low state is the most severe in the case that the lowest state E is collocated near the highest state P7, and the P7 state and the P6 state overlap after the shift, resulting in more failed bits.
The current flash memory writing method is as follows: before data writing, data erasing is carried out by taking a Block (Block) as a unit, the Block erasing adopts Step erasing operation (ISPE), each erasing Pulse is sent out and then is subjected to erasing verification, the threshold voltage of a verification storage unit is lower than the erasing verification voltage, the memory unit is successfully erased, and the erasing action is finished if all the memory units of the Block are successfully erased; after the erase is completed, the data is written in by using an Incremental Step Pulse Program (ISPP), and after the programming Pulse voltage operation, a Program verification operation is performed on the memory cell, and if the threshold voltage of the memory cell exceeds the Program verification voltage, the programming of the memory cell is completed. FIG. 3 is a distribution diagram of the read voltage and program verify voltage of TLC, as shown in FIG. 3, the read voltage of TLC is R1 to R7, the program verify voltage is V1 to V7, and the erase verify voltage is VE in FIG. 3.
It can be seen that in the conventional flash memory data random writing mode, the storage state of each memory cell before the flash memory data is erased is random, and the low-storage-state cell is lower than the erase verification voltage at the fastest speed when the low-storage-state cell is erased, because a block erase mode is adopted, the threshold voltage of the memory cell which is successfully erased preferentially can be further reduced in the subsequent erase process, as shown in fig. 3, the threshold voltage distribution of the erase state E is very wide, that is, there are many memory cells with extremely low threshold voltages. The existing TLC programs 7 verification voltages V1-V7 define threshold voltage distributions of P1-P7, even if an erase state with an extremely low threshold voltage still exists in an erase state at the end of data programming, the extremely low threshold voltage erase state is matched with a high storage state of an adjacent layer, so that the retention time of data is seriously reduced, and the reliability of the data is influenced.
Disclosure of Invention
In view of the above, the present invention has been made to provide a method, an apparatus, a storage medium and a storage device for improving reliability of flash data that overcome or at least partially solve the above problems.
In one aspect of the present invention, a method for improving data reliability of a flash memory is provided, the method comprising:
erasing a target storage unit to which data is to be written;
when data are written into the erased target storage unit, if the current storage state to be written is the lowest state, programming the lowest state of the target storage unit by adopting a preset optimized programming verification voltage, wherein the optimized programming verification voltage is lower than the erasing verification voltage corresponding to the erasing operation.
Further, before the target memory cell is programmed with the lowest state using the preset optimized program verify voltage, the method further includes:
acquiring a storage state of a storage unit adjacent to a target storage unit;
and when the storage state of the storage unit adjacent to the target storage unit is higher than the preset storage state threshold value, programming the lowest state of the target storage unit by adopting a preset optimized programming verification voltage.
Further, the method further comprises:
and pre-configuring a storage state list, wherein the storage state list is used for recording the storage state of the storage unit which is written with the latest data.
Further, the obtaining the storage state of the storage unit adjacent to the target storage unit comprises:
and searching the storage state list to acquire the storage state of the storage unit adjacent to the target storage unit.
Further, the method further comprises:
and updating the storage state list after finishing the data writing of the target storage unit so as to record the storage state of the target storage unit to the storage state list.
In a second aspect, the present invention further provides an apparatus for improving data reliability of a flash memory, the apparatus comprising:
the erasing module is used for erasing the target storage unit of the data to be written;
and the programming module is used for programming the target storage unit in the lowest state by adopting a preset optimized programming verification voltage if the current storage state to be written is the lowest state when data are written into the erased target storage unit, wherein the optimized programming verification voltage is lower than the erasing verification voltage corresponding to the erasing operation.
Further, the programming module is further configured to, before the target memory cell is programmed in the lowest state by using the preset optimal program verify voltage, obtain a memory state of a memory cell adjacent to the target memory cell, and perform an operation of programming the target memory cell in the lowest state by using the preset optimal program verify voltage when the memory state of the memory cell adjacent to the target memory cell is higher than a preset memory state threshold.
Further, the apparatus further comprises:
and the configuration module is used for configuring a storage state list in advance, and the storage state list is used for recording the storage state of the storage unit which completes the latest data writing.
Further, the programming module is configured to search the storage state list to obtain a storage state of a storage unit adjacent to the target storage unit.
In a third aspect, the present invention also provides a computer readable storage medium having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method of improving reliability of flash memory data as above.
In a fourth aspect, the present invention also provides a storage device comprising a storage controller, the storage controller comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method for improving reliability of flash memory data as above when executing the computer program.
According to the method, the device, the storage medium and the storage equipment for improving the data reliability of the flash memory provided by the embodiment of the invention, after the target storage unit of the data to be written is subjected to erasing operation, the storage unit with the lowest written data state is programmed by adopting the preset optimized programming verification voltage, so that the E state has no extremely low threshold voltage after the data is written, the problem that the data Retention time is influenced by the matching of the extremely low threshold voltage storage unit and the adjacent layer high storage state is solved, and the Retention characteristic of the data is improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of threshold voltage distributions of a flash memory for single bit storage, two bit storage and three bit storage;
FIG. 2 is a schematic diagram of initial threshold voltage distribution versus threshold voltage distribution after data retention for a period of time for NAND write TLC;
FIG. 3 is a schematic diagram of the distribution of read voltage and program verify voltage for TLC;
FIG. 4 is a flowchart of a method for improving data reliability of a flash memory according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a comparison of a prior art threshold voltage distribution and a voltage distribution for optimizing the program verify voltage write minimum state according to the present invention;
FIG. 6 is a flowchart of a method for improving data reliability of a flash memory according to another embodiment of the present invention;
fig. 7 is a block diagram of an apparatus for improving data reliability of a flash memory according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Example one
FIG. 4 is a flow chart that schematically illustrates a method for improving data reliability in a flash memory, in accordance with an embodiment of the present invention. Referring to fig. 4, the method for improving the reliability of flash memory data according to the embodiment of the present invention specifically includes the following steps:
s11, erasing the target storage unit of the data to be written;
s12, when data are written into the erased target storage unit, if the current storage state to be written is the lowest state, the target storage unit is programmed in the lowest state by adopting a preset optimized programming verification voltage, and the optimized programming verification voltage is lower than the erasing verification voltage corresponding to the erasing operation.
In the embodiment of the present invention, a three-bit memory (TLC) is taken as an example to illustrate, where the TLC flash has 1 erased state (E) and 7 programmed states (P1, P2, P3, P4, P5, P6, and P7), and the order of arrangement of electrons in the memory layer is P7> P6> P5> P4> P3> P2> P1> E, that is, P7 is the highest state, and E is the lowest state.
Taking NAND TLC distribution as an example, the conventional writing method has 7 program verify voltages V1 to V7, and the distribution of P1 to P7 is defined by using 7 program verify voltages V1 to V7. In the embodiment of the present invention, 1 optimized program verify voltage V0 is added on the basis of the existing 7 program verify voltages, and V0 is the program verify voltage for the lowest state distribution in the programming process, as shown in fig. 5, the upper part is the threshold voltage distribution written by the existing data, and the lower part is the threshold voltage distribution after the data is written in the present invention, the threshold voltage distribution of the lowest state is more convergent, and there are no memory cells with extremely low threshold voltages. Therefore, the problem that the data retention time is influenced by the matching of the ultra-low threshold voltage storage unit and the adjacent layer high storage state is solved.
Furthermore, in the embodiment of the present invention, the verification voltage V0 programming is performed only on the memory cell to be written with the data in the lowest state, and the verification voltage V0 programming is not required for all the memory cells to be written with the data, which not only improves the retentivity of the data, but also reduces the verification time of all the verifications.
According to the method for improving the data reliability of the flash memory, after the target storage unit of the data to be written is subjected to erasing operation, the storage unit with the lowest state of the written data is programmed by adopting the preset optimized programming verification voltage, so that the E state has no extremely low threshold voltage after the data is written, the problem that the data Retention time is influenced by the collocation of the storage unit with the extremely low threshold voltage and the high storage state of the adjacent layer is solved, and the Retention characteristic of the data is improved.
The data writing method of the NAND flash memory of the present invention is explained in detail by a specific example.
Receiving a data writing request of a host;
the storage system receives data and encodes the data;
performing block erasing on the memory unit to which the data is written;
writing to each of the memory states E, P1-P7 is programmed using the corresponding program verify voltages V0-V7;
the programming of the memory cell is terminated when the threshold voltage of the memory state exceeds the corresponding program verify voltage.
Example two
Fig. 6 schematically shows a flow chart of a method for improving data reliability of a flash memory according to another embodiment of the present invention. Referring to fig. 6, the method for improving the reliability of flash data according to the embodiment of the present invention specifically includes the following steps:
s21, erasing the target storage unit of the data to be written;
s22, when data are written into the erased target storage unit, if the current storage state to be written is the lowest state, the storage state of the storage unit adjacent to the target storage unit is obtained;
and S23, when the storage state of the storage unit adjacent to the target storage unit is higher than the preset storage state threshold value, performing minimum state programming on the target storage unit by adopting the preset optimized programming verification voltage.
In the embodiment of the present invention, since the data retention time is seriously reduced when the erase state with the extremely low threshold voltage is collocated with the high storage state of the adjacent layer, the data retention capability of the flash memory can be improved by obtaining the storage state of the memory cell adjacent to the target memory cell in advance, and if the storage state of the memory cell adjacent to the target memory cell is higher than the preset storage state threshold, for example, when the storage state of the adjacent memory cell is P7, performing the programming of the lowest state, that is, the E state, on the target memory cell by using the preset optimized program verification voltage.
In the embodiment of the invention, the storage state of each storage unit is recorded by pre-configuring the storage state list. The storage state list is used for recording the storage state of the storage unit which completes the data writing latest.
Further, the obtaining of the storage state of the storage unit adjacent to the target storage unit in step S22 is specifically implemented as follows: and searching the storage state list to acquire the storage state of the storage unit adjacent to the target storage unit.
Further, the method further comprises the steps of: and updating the storage state list after finishing the data writing of the target storage unit so as to record the storage state of the target storage unit to the storage state list.
It should be noted that the method for improving the reliability of flash data provided by the present invention is not limited to the TLC minimum state programming, and SLC, MLC, QLC and even PLC also belong to the protection scope of the present invention.
The method for improving the data reliability of the flash memory provided by the embodiment of the invention has the following beneficial effects:
in the invention, programming verification is also carried out on the memory state which is the lowest state, so that the threshold voltage distribution of the lowest state is improved; a memory cell with too low threshold voltage does not exist in the lowest state, so that the data retention capacity of the flash memory is improved;
the lowest state program verify voltage V0 is lower than the erase verify voltage VE, and the maximum value in the lowest state threshold voltage distribution written based on the program verify voltage V0 should not exceed the erase verify voltage VE in order to guarantee reliability;
the patent is not limited to the programming of TLC minimum state, and SLC, MLC, QLC and even PLC are in the protection scope of the patent.
For simplicity of explanation, the method embodiments are described as a series of acts or combinations, but those skilled in the art will appreciate that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the embodiments of the invention. Further, those of skill in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the embodiments of the invention.
EXAMPLE III
Fig. 7 is a schematic structural diagram of an apparatus for improving data reliability of a flash memory according to an embodiment of the present invention. Referring to fig. 7, the apparatus for improving the reliability of flash data according to the embodiment of the present invention specifically includes an erasing module 201 and a programming module 202, wherein:
an erasing module 201, configured to perform an erasing operation on a target storage unit to be written with data;
the programming module 202 is configured to, when data is written into the erased target memory cell, perform minimum state programming on the target memory cell by using a preset optimized programming verification voltage if the current memory state to be written is a minimum state, where the optimized programming verification voltage is lower than an erase verification voltage corresponding to an erase operation.
In this embodiment of the present invention, the programming module 202 is further configured to, before the target memory cell is programmed in the lowest state by using the preset optimal program verify voltage, obtain a memory state of a memory cell adjacent to the target memory cell, and execute an operation of programming the target memory cell in the lowest state by using the preset optimal program verify voltage when the memory state of the memory cell adjacent to the target memory cell is higher than a preset memory state threshold.
In this embodiment of the present invention, the apparatus further includes a configuration module not shown in the drawing, where the configuration module is configured to pre-configure a storage state list, and the storage state list is used to record a storage state of a storage unit in which data writing is completed most recently.
Further, the programming module 202 is configured to search the storage state list to obtain the storage state of the storage unit adjacent to the target storage unit.
Further, the configuration module is further configured to update the storage state list after the programming module 202 completes the data writing of the target memory cell, so as to record the storage state of the target memory cell into the storage state list.
For the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
Furthermore, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the method for improving the reliability of flash data as described above.
In this embodiment, if the method for improving the reliability of flash memory data is implemented in the form of a software functional unit and sold or used as an independent product, the method may be stored in a computer-readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
In addition, an embodiment of the present invention further provides a storage device, including a storage controller, where the storage controller includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the program, the processor implements the steps of the method for improving data reliability of a flash memory as described above. Such as steps S11-S12 shown in fig. 4.
In a specific embodiment, the storage device is a Solid State Disk (SSD).
According to the method, the device, the storage medium and the storage equipment for improving the data reliability of the flash memory provided by the embodiment of the invention, after the target storage unit of the data to be written is subjected to erasing operation, the storage unit with the lowest written data state is programmed by adopting the preset optimized programming verification voltage, so that the E state has no extremely low threshold voltage after the data is written, the problem that the data Retention time is influenced by the matching of the extremely low threshold voltage storage unit and the adjacent layer high storage state is solved, and the Retention characteristic of the data is improved.
Moreover, those of skill in the art will appreciate that while some embodiments herein include some features included in other embodiments, not others, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments may be used in any combination.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for improving data reliability of a flash memory, the method comprising:
erasing a target storage unit to which data is to be written;
when data writing is carried out on the erased target storage unit, if the current storage state to be written is the lowest state, the lowest state programming is carried out on the target storage unit by adopting a preset optimized programming verification voltage, and the optimized programming verification voltage is lower than the erasing verification voltage corresponding to the erasing operation.
2. The method of claim 1, wherein prior to programming the target memory cell with the lowest state using the preset optimal program verify voltage, the method further comprises:
acquiring a storage state of a storage unit adjacent to a target storage unit;
and when the storage state of the storage unit adjacent to the target storage unit is higher than the preset storage state threshold value, programming the lowest state of the target storage unit by adopting a preset optimized programming verification voltage.
3. The method of claim 2, further comprising:
and pre-configuring a storage state list, wherein the storage state list is used for recording the storage state of the storage unit which is written with the latest data.
4. The method of claim 3, wherein obtaining the storage state of the storage unit adjacent to the target storage unit comprises:
and searching the storage state list to acquire the storage state of the storage unit adjacent to the target storage unit.
5. The method of claim 4, further comprising:
and updating the storage state list after finishing the data writing of the target storage unit so as to record the storage state of the target storage unit to the storage state list.
6. An apparatus for improving data reliability of a flash memory, the apparatus comprising:
the erasing module is used for erasing the target storage unit of the data to be written;
and the programming module is used for programming the lowest state of the target storage unit by adopting a preset optimized programming verification voltage if the current storage state to be written is the lowest state when the erased target storage unit is subjected to data writing, wherein the optimized programming verification voltage is lower than the erasing verification voltage corresponding to the erasing operation.
7. The apparatus of claim 6, wherein the programming module is further configured to obtain a memory state of a memory cell adjacent to the target memory cell before the target memory cell is programmed with the lowest state by using a preset optimal program verify voltage, and perform the operation of programming the lowest state of the target memory cell by using the preset optimal program verify voltage when the memory state of the memory cell adjacent to the target memory cell is higher than a preset memory state threshold.
8. The apparatus of claim 7, further comprising:
the configuration module is used for configuring a storage state list in advance, and the storage state list is used for recording the storage state of a storage unit which completes the latest data writing;
further, the programming module is configured to search the storage state list to obtain a storage state of a storage unit adjacent to the target storage unit.
9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 5.
10. A storage device comprising a storage controller comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method as claimed in any one of claims 1 to 5 when the computer program is executed by the processor.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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