CN114400038A

CN114400038A - Three-dimensional memory and control method thereof

Info

Publication number: CN114400038A
Application number: CN202111631619.9A
Authority: CN
Inventors: 刘红涛; 黄莹; 靳磊; 赵向南; 关蕾; 魏文喆
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2022-04-26

Abstract

The application provides a three-dimensional memory and a control method thereof. The memory includes a memory cell array having a plurality of memory strings, each of the memory strings including a plurality of memory cells, the method comprising: in performing a read operation, a first read voltage is applied to a selected plurality of memory cells, and a first turn-on voltage is applied to an unselected plurality of memory cells, wherein the first turn-on voltage is lower than a preset turn-on voltage.

Description

Three-dimensional memory and control method thereof

Technical Field

The present invention relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory (3D NAND) and a control method thereof.

Background

The data stored in the volatile memory can be lost after power failure, while the data can still be retained in the nonvolatile memory, and the nonvolatile memory is suitable for the data needing to be stored for a long time. The nonvolatile memory includes a Flash memory (Flash memory), a read only memory ROM, an electrically erasable programmable read only memory EEPROM, a one-time programmable memory OTPROM, a mechanical hard disk, and the like, wherein the Flash memory includes a NAND type, a NOR type, and the like. The NAND type flash memory has the advantages of high writing speed, simple erasing operation and capability of realizing higher storage density by smaller memory cells. Therefore, a memory device having a NAND structure has been widely used.

It should be understood that the statements in this background section merely provide an aid in understanding the technical solutions disclosed herein and are not necessarily prior art to the filing date of the present application.

Disclosure of Invention

One aspect of the present disclosure provides a method for controlling a three-dimensional memory. The memory includes a memory cell array having a plurality of memory strings, each of the memory strings including a plurality of memory cells, the method comprising: in the read operation, a first read voltage is applied to at least one selected memory cell, and a first turn-on voltage is applied to at least one unselected memory cell, wherein the first turn-on voltage is lower than a preset turn-on voltage.

In one embodiment, the method further comprises: and in response to receiving the trigger rereading error correction, applying a second reading voltage to at least one selected memory cell, and applying a second breakover voltage higher than the preset breakover voltage to at least one unselected memory cell.

In one embodiment, the method further comprises: and in response to receiving the trigger reread error correction, applying an (N +1) th reading voltage to at least one selected memory cell, and applying an (N +1) th turn-on voltage higher than an Nth preset turn-on voltage to at least one unselected memory cell, the upper selection transistor and the lower selection transistor, wherein N is more than or equal to 2.

In one embodiment, the memory further includes a configuration block having a relationship table, the method further comprising: and determining the values of the second reading voltage and the (N +1) th reading voltage according to the relation table, wherein N is more than or equal to 2.

In one embodiment, the method further comprises: applying, by a controller, the first read voltage to the selected at least one of the memory cells and the first turn-on voltage to the unselected at least one of the memory cells.

In one embodiment, the method further comprises: and after triggering the rereading correction, applying the second reading voltage to at least one selected memory cell through the controller, and applying a second breakover voltage higher than the preset breakover voltage to at least one unselected memory cell.

In one embodiment, the method further comprises: after the rereading error correction is triggered, applying (N +1) th reading voltage to at least one selected storage unit through the controller, and applying (N +1) th conduction voltage higher than an Nth preset conduction voltage to at least one unselected storage unit through the controller, wherein N is larger than or equal to 2.

Another aspect of the present application provides a three-dimensional memory, including: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells; and the memory is controlled by the controller and is configured to apply a first reading voltage to a plurality of selected memory cells and a first turn-on voltage to at least one unselected memory cell in the read operation, wherein the first turn-on voltage is lower than a preset turn-on voltage.

In one embodiment, the memory is configured to apply a second read voltage to the selected at least one of the memory cells and apply a second turn-on voltage higher than the preset turn-on voltage to the unselected at least one of the memory cells, the upper selection transistor and the lower selection transistor after re-read error correction is triggered; and after applying the Nth reading voltage to trigger rereading error correction, applying an (N +1) th reading voltage to at least one selected memory cell, and applying an (N +1) th turn-on voltage higher than the Nth turn-on voltage to at least one unselected memory cell, the upper selection transistor and the lower selection transistor, wherein N is more than or equal to 2.

In one embodiment, the memory further has a configuration block of a relationship table, and the values of the second read voltage and the (N +1) th read voltage are determined according to the relationship table, where N ≧ 2.

In one embodiment, the memory further comprises a plurality of word lines respectively connected to the plurality of memory cells, including a redundant word line, a first word line, and a second word line,

wherein the selected memory cells are connected to the first word line of the plurality of word lines, and the unselected memory cells are connected to the redundant word line and the second word line, respectively.

In one embodiment, the plurality of word lines are respectively connected to gates of a plurality of the memory cells.

In one embodiment, the memory is a 3D NAND memory

Yet another aspect of the present application provides a three-dimensional memory system, including: at least one memory including at least one memory cell array, wherein the memory cell array includes a plurality of memory strings, each of the memory strings including a plurality of memory cells; and a controller electrically connected to the memory and controlling the memory, and a method of controlling the memory includes the control method of any one of the above embodiments.

The scheme of the application achieves the purpose of reducing the reading interference by reducing the breakover voltage under the default reading operation. Reducing the reading conduction voltage to be lower than the preset conduction voltage of the default reading operation, wherein although the reading window is relatively reduced under the condition of not triggering the rereading error correction, the reduced value of the reading window has little influence on reducing the Fault Bit Count (FBC), and the reduced reading window still can meet the reading requirement; after the re-reading error correction is triggered by the read operation, the read window can be improved by properly increasing the conducting voltage, so that the effects of reducing the FBC and improving the threshold drift and the expansion of the memory cell are achieved.

Drawings

Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments when taken in conjunction with the accompanying drawings. In the drawings:

FIG. 1 is a schematic diagram of threshold shift of a memory cell in a read phase of operation according to a related art embodiment;

FIG. 2 is a schematic diagram of threshold distributions of memory cells in a read phase of operation according to a related art embodiment;

FIG. 3 is a schematic structural diagram of a memory string of a three-dimensional memory according to the related art;

FIG. 4 is a circuit diagram of a memory cell array formed from a plurality of memory strings of FIG. 3;

FIG. 5 is a waveform schematic diagram of a read operation process of a three-dimensional memory according to some embodiments;

FIG. 6 is a different state of a same layer of memory cells of a three-dimensional memory after data writing according to some embodiments;

FIG. 7 shows the data states of the memory string during the program phase and the read phase;

FIG. 8 is a flow diagram illustrating a default read operation of a three-dimensional memory according to a related art embodiment;

FIG. 9 is a schematic diagram of a read operation of a three-dimensional memory according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a memory card having a three-dimensional memory and a three-dimensional memory system of an embodiment of the present application; and

FIG. 11 is a circuit block diagram of a memory according to an embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

It should be noted that in the present description, the expressions first, second, third, etc. are used only to distinguish one feature from another, and do not indicate any limitation on the features, and do not particularly indicate any precedence order. Thus, the first turn-on voltage discussed in this application may be referred to as the second turn-on voltage and the first word line may also be referred to as the second word line, or vice versa, without departing from the teachings of this application.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, the thicknesses of the functional layers drawn in the figures in this application are not to scale in actual production. As used herein, "substantially", "about" and similar terms are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than just individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

The features, principles and other aspects of the present application are described in detail below.

Fig. 1 is a schematic diagram of threshold shift of memory cells in a read operation phase according to an embodiment of the related art, and fig. 2 is a schematic diagram of threshold distribution of memory cells in a read operation phase according to an embodiment of the related art. As shown in FIG. 1, the solid line graph 10 represents the threshold voltage V of the memory cell 210 (FIG. 4) in the read phase_thThe dotted line graph 20 represents the threshold voltage V caused by a read operation_thAnd (4) drifting. After the memory cell 210 changes from the erased state to the programmed state, the threshold voltage V_thA positive movement occurs. FIG. 2 illustrates the threshold voltage V of the memory cell 210 caused by a change in the data state of the memory string 100 (FIG. 3)_thDrifting, the threshold voltage V of the memory cells 210 in the memory string 100 from the lowest level to the highest level (in the y-direction)_thAnd gradually increases.

The inventors of the present application have discovered that during programming and read operations of a 3D NAND, the threshold voltage V may be caused by a change in the data state of the memory string 100 (fig. 3)_thThe drain resistance of the memory cell 210 changes during the program verify phase and the read phase_thCausing a forward motion, thereby generating a bpd (back pattern disturb).

The inventors have also found that after the memory cell 210 changes from the erased state to the programmed state, it is at the same preset turn-on voltage V_passThe lower corresponding channel resistance will rise, resulting in a threshold voltage V for each state_thDrift up and the threshold voltage V of each state is different because different memory cells 210 drift by different amounts_thThe drift to the high place and the trend of broadening are simultaneously realized, so that the preset breakover voltage V is increased_passThe threshold V in this case can be improved_thDrift and spread.

Fig. 3 is a schematic structural diagram of a memory string 100 of a three-dimensional memory according to the related art. Illustratively, the memory string 100 may be used as an intermediate structure during the fabrication process of a three-dimensional memory, such as a 3D NAND memory. The memory string 100 includes a functional layer 110 having a memory function, a channel layer 114, and

gate conductors

101, 102, 103, 104, and 105 located outside (in the x-direction) the functional layer 110. Illustratively, the functional layer 110 may include a blocking layer 111, a charge trapping layer 112, and a tunneling layer 113 sequentially arranged from outside to inside (in a direction opposite to x), and the channel layer 114 is connected to the tunneling layer 113 in the functional layer 110. Illustratively, the blocking layer 111, the charge trapping layer 112, and the tunneling layer 113 may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure, and the material of the channel layer 114 includes polysilicon.

In some examples,

gate conductors

101, 102, 103, 104, and 105 are in a stacking order of transistors in memory string 100, with adjacent gate conductors being separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the gate conductor 103 and the channel layer 114 sandwich the blocking layer 111, the charge storage layer 112, and the tunneling layer 113, thereby forming a plurality of memory transistors. At both ends of the memory string 100, a barrier layer 111 is sandwiched between the

gate conductors

101, 105 and a channel layer 114, thereby forming an upper selection transistor and a lower selection transistor, respectively.

It is understood that the number of the memory cells in fig. 3 is merely an exemplary illustration, the present invention is not limited thereto, and the number of the memory cells in each memory string 100 may be any number, for example, 32 or 64.

Fig. 4 is a circuit diagram of a memory cell array 200 composed of a plurality of memory strings 100 in fig. 3, and as shown in fig. 4, the three-dimensional memory may include a plurality of memory strings 100, wherein the memory cell array 200 may include a plurality of memory cells 210, a string selection line 201, a ground selection line 207, and a plurality of word lines 208. Further, the memory cell 210 may be formed by the blocking layer 111, the charge storage layer 112, and the tunneling layer 113 between the gate conductor 103 and the channel layer 114 (shown within the dashed box in fig. 3). When a read operation is performed on a certain memory cell 210 in the memory, it is necessary to determine the memory string 100 in which the selected memory cell 210 is located and a specific word line in the plurality of word lines 208, for example, the word line in which the selected memory cell is located is the first word line 204. Word lines 208 may also include a redundant word line 202 located above (in the y-direction) first word line 204, a redundant word line 206 located below first word line 104, a second word line 203 located between first word line 204 and redundant word line 202, and a second word line 205 located between first word line 104 and redundant word line 206. It should be noted that the first word line 204 is shown in the middle, but the present application is not limited thereto, and the first word line 204 may be located at the uppermost side or the lowermost side of the plurality of word lines 208, and in this case, the

redundant word lines

202 or 206 may not be included above or below the first word line 204. In addition, the number of the word lines 208 in fig. 4 is an exemplary illustration, and is not a specific limitation on the number, and one skilled in the art can select an appropriate scheme to design according to the specific situation of different memories. Similarly, the specific number of the first word line 204, the second word lines 203 and 205, and the

redundant word lines

202 and 206 in the word line 208 can be adjusted differently according to different situations.

In some examples, the memory cells 210 selected during the read operation are located on first word line 204, while the unselected memory cells 210 may be located on, for example, redundant word lines 202, 206, and second word lines 203, 205.

In some examples, a plurality of word lines 208 are respectively connected to the gates of the plurality of memory cells 210, the gates of the upper select transistors are connected to the string select line 201, and the gates of the lower select transistors are connected to the ground select line 207.

FIG. 5 is a waveform diagram illustrating a read operation process of a three-dimensional memory according to some embodiments. As shown in FIG. 5, during a read operation, a read voltage V is applied to first word line 204_readTo the string selection line 201. A preset turn-on voltage V is applied to a ground selection line 207, a redundant word line 202 positioned on the upper side of a first word line 204, a redundant word line 206 positioned on the lower side of the first word line 204, a second word line 203 positioned between the first word line 204 and the redundant word line 202, and a second word line 205 positioned between the first word line 204 and the redundant word line 206_pass. Preset on-state voltage V_passGreater than the maximum threshold voltage V of the word line to which it is applied_thAnd a read voltage V on first word line 204_readLess than a predetermined on-state voltage V_pass。

In some examples, the channel is turned on during the read operation by a predetermined turn-on voltage V applied to the gates of the memory cells 210 in, for example, the first word line 204_passInverting the channel to N-type, with the highest threshold voltage V of the word line after data writing_thBy a certain amount.

As shown in FIG. 6, since the memory cells 210 of the same layer share the same word line (e.g., the first word line 204), the memory cells 210 of the same layer are in different states after data writing, and in extreme, the highest state after data writing and the predetermined turn-on voltage V are set to be the same_passDifference value V of₁Maximum, maximum channel on-resistance, lowest state after data writing and preset on-voltage V_passDifference value V of₂And at a minimum, its corresponding channel on-resistance is also at a minimum.

In FIG. 7, (a) is the program phase to store the data state of string 100, and (b) is the read phase to store the data state of string 100. As shown in FIG. 7, in a bottom-up programming sequence, for example, during a programming phase of a selected word line (first word line 204), memory cells 210 in first word line 204 and second word line 205 located on a lower side of first word line 204 are in a written state, while memory cells 210 in second word line 203 located on an upper side of first word line 204 are in an erased state. In the read operation phase, the memory cells 210 in the first word line 204 and the second word line 203 located above the first word line 204 and the second word line 205 located below the first word line 204 are all in the data writing state.

After the memory cells 210 in the second word line 203 on the upper side of the first word line 204 change from the erased state to the programmed state, theyAt the same preset turn-on voltage V_passThe lower corresponding channel resistance will rise, resulting in a threshold voltage V for each state of first word line 204_thDrift up and the threshold voltage V of each state is different because different memory cells 210 drift by different amounts_thThe drift to the high place and the trend of broadening are realized, and the preset breakover voltage V can be increased_passTo improve the threshold voltage V in this case_thDrift and spread. However, the preset on-voltage V is increased_passThis causes an increase in read disturb during a read operation, and thus the applied turn-on voltage needs to be reduced to reduce read disturb.

As shown in FIG. 8, for a default read operation of a 3D NAND memory, starting at block 810, a default read voltage V is first applied at block 820_readAnd a predetermined on-voltage V_passApplied to the first wordline 204, if the FBC is less than the Error correction capability of the Error correction control Code (ECC), the read operation may pass (block 830), and when the FBC is greater than the Error correction capability of the ECC, a reread Error correction (read) is triggered (block 840), which is typically performed by changing the read voltage V for the first wordline 204 according to a reread Error correction table written in the configuration block_readAnd other parameters are not changed, and the reading operation is carried out again until the reading operation is passed. The flow ends after the read operation passes (block 850).

Fig. 9 is a flow chart illustrating a read operation of a three-dimensional memory according to an embodiment of the present application. As shown in FIG. 9, in some examples, beginning at block 910, a read voltage V is applied to a plurality of memory cells in the first word line 204 during a read operation phase_readA voltage lower than a preset turn-on voltage V is applied to the string selection line 201, the ground selection line 207, the redundant word line 202 located on the upper side of the first word line 204, the redundant word line 206 located on the lower side of the first word line 204, the second word line 203 located between the first word line 204 and the redundant word line 202, and the second word line 205 located between the first word line 204 and the redundant word line 206_passFirst on-voltage V_pass-1(block 920). If the read operation passes (block 930), the read re-read error correction is not triggered (block 940), and the read operation ends (block 960). In this case, although readingThe window becomes relatively small, but the reduced value has little effect on reducing the Fail Bit Count (FBC), while the read window is still large enough; after the read turn-on voltage is lowered to trigger the read operation to re-read error correction (block 940), the read turn-on voltage may be raised appropriately (block 950) to raise the read window.

In other examples, the first turn-on voltage V is applied_pass-1An error correction procedure, such as rereading error correction (block 940), may then be triggered, at which point the first read voltage V applied to the first wordline 204 may be modified according to a relationship table, such as a rereading error correction (read) table, written in the configuration block_read-1For the second read voltage V_read-2And applies a second turn-on voltage V higher than the preset turn-on voltage to the string selection line 201, the ground selection line 207, the redundant word line 202 positioned at the upper side of the first word line 204, the redundant word line 206 positioned at the lower side of the first word line 204, the second word line 203 positioned between the first word line 204 and the redundant word line 202, and the second word line 205 positioned between the first word line 204 and the redundant word line 206_pass-2(block 950). If read re-read error correction is not triggered any more (block 940), the read operation ends (block 960).

In other examples, the second turn-on voltage V is applied_pass-2Thereafter, reread error correction may still be triggered (block 940), and steps such as those described above may be repeated to apply a third read voltage V_read-3And applying a voltage higher than the second turn-on voltage V_pass-2Third on-voltage V_pass-3(ii) a Applying a fourth read voltage V_read-4And applying a voltage higher than the third turn-on voltage V_pass-3Fourth on-voltage V_pass-4(ii) a … … applying the (N +1) th read voltage V_read-3And applying a higher than Nth turn-on voltage V_pass-n(N +1) th turn-on voltage V_pass-(n+1)(block 950), the read pass verification (block 9530) is performed in turn until the read pass is the end (block 960).

Another aspect of the present application provides a three-dimensional memory, and yet another aspect of the present application also provides a three-dimensional memory system. The three-dimensional memory and the three-dimensional memory system can be controlled by any of the control methods in the above embodiments. Fig. 10 is a schematic diagram of a memory card 300 having a three-dimensional memory and a three-dimensional memory system according to an embodiment of the present application. As shown in fig. 10, the memory card 300 may include a memory 301, a controller 302, and a connector 303. The memory card 300 may include a PC card, a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card, an SD card, a universal flash memory card (UFS), and the like. The memory card 300 may also include a memory card connector 303 that couples the memory card 300 with a host (not shown). In some examples, the controller 302 may be configured to control operations of the memory 301, such as read, program, and erase operations, and the like. The controller 302 may also be configured to manage various functions related to data stored or to be stored in the memory 301, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, and the like.

In some examples, the controller 302 is further configured to process error correction control coding (ECC) related to data read from the memory 301 or written to the memory 301. Any other suitable function may also be performed by the controller 302, such as formatting the memory 301. In some examples, the controller 302 is configured to perform, in whole or in part, the method of operation as described in detail below.

In some examples, the memory 301 may include a memory cell array 200 (shown with reference to fig. 3 and 4) having a plurality of memory strings 100, and each memory string 100 may include a plurality of memory cells 210 and may further include an upper selection transistor and a lower selection transistor.

In some examples, the memory 301 further includes a string select line 201 connected to the gate of the upper select transistor, a ground select line 207 connected to the gate of the lower select transistor, and a plurality of word lines 208 between the string select line 201 and the ground select line 207. The plurality of word lines 208 are respectively connected to a plurality of memory cells 210, and include a first word line 204, a redundant word line 202 located on an upper side of the first word line 204, a redundant word line 206 located on a lower side of the first word line 204, a second word line 203 located between the first word line 204 and the redundant word line 202, and a second word line 205 located between the first word line 204 and the redundant word line 206. With selected memory cells (e.g., memory cell 210) on a first wordline 204 of the plurality of wordlines 208 and unselected memory cells on

redundant wordlines

202 and 206 and second wordlines 203 and 205.

In some examples, memory 301 also includes a configuration block having a relationship table. Illustratively, the relational table may be, for example, a re-read error correction (read) table. The read voltage V applied to first word line 204 may be modified according to a re-read error correction table written in the configuration block_read。

In some examples, the memory 301, under the control of the controller 302, may be configured to apply a first read voltage V to a selected plurality of memory cells 210 in performing a read operation_read-1And applying a lower than preset turn-on voltage V to the unselected plurality of memory cells 210, the upper select transistor, and the lower select transistor_passFirst on-voltage V_pass-1。

In other examples, a first read voltage V is applied to a selected plurality of memory cells 210_read-1And applying a lower than preset turn-on voltage V to the unselected memory cells 210, the upper selection transistor and the lower selection transistor_passFirst on-voltage V_pass-1Thereafter, still triggering the re-read error correction, the controller 302 may control the memory 301 to apply the second read voltage V to the selected plurality of memory cells 210_read-2And applying a voltage higher than a preset turn-on voltage V to the unselected memory cells 210, the upper selection transistor and the lower selection transistor_passSecond on-voltage V_pass-2。

In other examples, the Nth read voltage V is applied_read-NAfter triggering the reread error correction, the controller 302 is further configured to apply an (N +1) th read voltage V to the selected plurality of memory cells 210 in the memory 301_read-(N+1)And applying a voltage higher than the Nth turn-on voltage V to the unselected memory cells 210, the upper selection transistor and the lower selection transistor_pass(N +1) th turn-on voltage V_pass-(N+1)Wherein N is more than or equal to 2.

FIG. 11 is a circuit block diagram of a memory according to an embodiment of the present application. Referring to FIG. 11, the memory 301 may include a memory cell array 200, a controller 310, a page buffer 304, a word line voltage generator 305, and word linesA decoder 306 and a voltage offset determination module 307. An exemplary structure of the memory cell array 200 can be seen in fig. 4, and is arranged in a plurality of rows and a plurality of columns, for example, each column of memory cells is connected to the page buffer 304 through a bit line BL, and the gates of the memory cells 210 in each row are connected to the word line decoder 306 through a word line WL. The page buffer 304 may be used to temporarily store data bits that have been read out of the memory array. Word line voltage generator 305 may generate a voltage for application to a word line, such as a programming voltage V_pgmA read voltage V_readAnd the like. The controller 310 is used to control the page buffer 304 and the word line voltage generator 305. In a read operation, the controller 310 applies a read voltage V to the first word line 204 (shown in FIG. 4) by controlling the word line voltage generator 305_readApplying a read-on voltage V to the unselected word lines, the string selection line 201 and the ground selection line 207_passThen, the page buffer 304 is controlled to sense the data stored in the memory cell 210 on the corresponding bit line BL according to different reading operation methods, so as to read the data stored in the nonvolatile memory.

It should be noted that the circuit block diagram of the memory shown in fig. 11 is only an exemplary one, and the present invention is not limited thereto, and those skilled in the art can select an appropriate scheme to design according to the specific situation of different memories.

Since the contents and structures referred to in the above description of the control method may be fully or partially applicable to the three-dimensional memory described herein, the contents related or similar thereto will not be described in detail.

The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims

1. A method of controlling a three-dimensional memory including a memory cell array having a plurality of memory strings, each of the memory strings including a plurality of memory cells, the method comprising:

in the read operation, a first read voltage is applied to at least one selected memory cell, and a first turn-on voltage is applied to at least one unselected memory cell, wherein the first turn-on voltage is lower than a preset turn-on voltage.

2. The method of claim 1, further comprising:

and in response to receiving the trigger rereading error correction, applying a second reading voltage to at least one selected memory cell, and applying a second breakover voltage higher than the preset breakover voltage to at least one unselected memory cell.

3. The method of claim 2, further comprising:

applying an (N +1) th read voltage to a selected at least one of the memory cells in response to receiving a trigger reread error correction, an

And applying (N +1) th turn-on voltage higher than the Nth preset turn-on voltage to at least one unselected memory cell, the upper selection transistor and the lower selection transistor, wherein N is more than or equal to 2.

4. The method of claim 3, wherein the memory further comprises a configuration block having a relationship table, the method further comprising:

and determining the values of the second reading voltage and the (N +1) th reading voltage according to the relation table, wherein N is more than or equal to 2.

5. The method of claim 1, further comprising:

applying, by a controller, the first read voltage to the selected at least one of the memory cells and the first turn-on voltage to the unselected at least one of the memory cells.

6. The method of claim 5, further comprising:

and after triggering the rereading correction, applying the second reading voltage to at least one selected memory cell through the controller, and applying a second breakover voltage higher than the preset breakover voltage to at least one unselected memory cell.

7. The method of claim 6, further comprising:

after the rereading error correction is triggered, applying (N +1) th reading voltage to at least one selected storage unit through the controller, and applying (N +1) th conduction voltage higher than an Nth preset conduction voltage to at least one unselected storage unit through the controller, wherein N is larger than or equal to 2.

8. A three-dimensional memory, comprising:

a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells; and

the memory is controlled by a controller and is configured to apply a first reading voltage to at least one selected memory cell and a first turn-on voltage to at least one unselected memory cell in a read operation, wherein the first turn-on voltage is lower than a preset turn-on voltage.

9. The memory of claim 8, wherein after re-read error correction is triggered, configured to apply a second read voltage to a selected at least one of the memory cells, and to apply a second turn-on voltage higher than the preset turn-on voltage to unselected at least one of the memory cells, the upper select transistor, and the lower select transistor; and

and the memory cell array is configured to apply an (N +1) th reading voltage to at least one selected memory cell after applying an Nth reading voltage to trigger rereading error correction, and apply an (N +1) th turn-on voltage higher than the Nth turn-on voltage to at least one unselected memory cell, the upper selection transistor and the lower selection transistor, wherein N is more than or equal to 2.

10. The memory of claim 9, further comprising:

11. The memory of claim 8, further comprising:

a plurality of word lines respectively connected to the plurality of memory cells, including a redundant word line, a first word line and a second word line,

12. The memory of claim 11, wherein the plurality of word lines are respectively connected to gates of a plurality of the memory cells.

13. The memory of claim 8, wherein the memory is a 3D NAND memory.

14. A three-dimensional memory system, comprising:

at least one memory including at least one memory cell array, wherein the memory cell array includes a plurality of memory strings, each of the memory strings including a plurality of memory cells; and

a controller electrically connected to and controlling the memory, and a method of controlling the memory including the control method of any one of claims 1 to 7.