CN114994497A - Chip pin test circuit and equipment - Google Patents

Chip pin test circuit and equipment Download PDF

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Publication number
CN114994497A
CN114994497A CN202210518119.2A CN202210518119A CN114994497A CN 114994497 A CN114994497 A CN 114994497A CN 202210518119 A CN202210518119 A CN 202210518119A CN 114994497 A CN114994497 A CN 114994497A
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China
Prior art keywords
unit
signal
output
module
terminal
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Inventor
颜军
王烈洋
李光
汤凡
占连样
陈像
罗仲涛
骆征兵
刘雯智
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Zhuhai Orbita Electronic Co ltd
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Zhuhai Orbita Electronic Co ltd
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Priority to CN202210518119.2A priority Critical patent/CN114994497A/en
Publication of CN114994497A publication Critical patent/CN114994497A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The invention discloses a chip pin test circuit and equipment, and relates to the technical field of integrated circuits. The circuit comprises a common resistor, a level output module and a connectivity test module; the first end of the common resistor is used as an IO port, and the second end of the common resistor is grounded; the first input end of the level output module is used for inputting a level control signal, and the output end of the level output module is connected with the IO port; the input end of the connectivity test module is used for inputting the switch control signal, the input end and the output end of the connectivity test module are connected with the IO port, and the output end of the connectivity test module is used for outputting a test result. According to the chip pin test circuit and the chip pin test equipment, the common resistor is used as the pull-down resistor of the level output module, and the common resistor is also used as one of the communication branches of the connectivity test module, so that the circuit structure can be simplified, and the cost can be reduced.

Description

Chip pin test circuit and equipment
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a chip pin test circuit and equipment.
Background
With the development of integrated circuit technology, integrated circuit chips are applied to various industries, and before the integrated circuit chips leave a factory, corresponding test equipment is required to test chip pins of the integrated circuit chips so as to remove defective products. However, the circuit structure of the current testing equipment is complex, resulting in high cost.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides a chip pin test circuit which can simplify the circuit.
The invention also provides a chip pin test device comprising the chip pin test circuit.
The chip pin test circuit comprises a common resistor, a level output module and a connectivity test module; a first end of the common resistor is used as an IO port, and a second end of the common resistor is grounded; a first input end of the level output module is used for inputting a level control signal, and an output end of the level output module is connected with the IO port; the input end of the connectivity test module is used for inputting a switch control signal, the input end and the output end of the connectivity test module are connected with the IO port, and the output end of the connectivity test module is used for outputting a test result.
The chip pin test circuit according to the embodiment of the invention at least has the following beneficial effects: the IO port is used for connecting chip pins; the level control signal is used for controlling the level output module to output a level driving signal to the chip pin; the connectivity test module is used for testing the connectivity of the chip pins; the common resistor is used as a pull-down resistor of the level output module and also used as a communication branch of the connectivity test module; the level output module and the connectivity test module share the common resistor, so that the level output module can output a driving level signal to the chip pins, the connectivity test module can carry out connectivity test on the chip pins, and meanwhile, the number of components is reduced, the circuit structure is simplified, and the cost is reduced.
According to some embodiments of the present invention, the connectivity test module includes a signal detection unit, a signal generation unit, and a switch control unit, an input end of the switch control unit is used as an input end of the connectivity test module, the switch control unit is configured to control the signal generation unit to output a test signal, an output end of the signal generation unit is connected to the IO port, an input end of the signal detection unit is connected to the IO port, and an output end of the signal detection unit is used as an output end of the connectivity test module, so that the connectivity test module tests a chip pin.
According to some embodiments of the present invention, the signal generating unit includes a sine wave generating circuit, and an output terminal of the sine wave generating circuit is connected to the IO port through the switch control unit, so that the signal detecting unit outputs a corresponding waveform, thereby facilitating confirmation of connectivity of chip pins.
According to some embodiments of the present invention, the signal generating unit includes a constant current source circuit, an output end of the constant current source circuit is connected to the IO port, and a controlled end of the constant current source circuit is connected to a control end of the switch control unit, so that the signal detecting unit outputs a corresponding voltage, thereby facilitating to confirm connectivity of chip pins.
According to some embodiments of the present invention, the level control signal includes a first level signal and a second level signal, the level output module includes a first comparing unit, a second comparing unit, and a wired-or unit, a first input terminal of the first comparing unit is used for inputting the first level signal, a second input terminal of the second comparing unit is used for inputting the second level signal, a second input terminal of the first comparing unit and a first input terminal of the second comparing unit are both used for inputting a first reference voltage signal, a negative power terminal of the first comparing unit and a negative power terminal of the second comparing unit are both used for inputting a first voltage signal with a voltage amplitude smaller than zero, an output terminal of the first comparing unit is connected to the first input terminal of the wired-or unit, and an output terminal of the second comparing unit is connected to the second input terminal of the wired-or unit, the output end of the wired-or unit is connected with the IO port so as to output a corresponding driving level signal.
According to some embodiments of the present invention, the positive power terminal of the first comparing unit is configured to input a second voltage signal, and the positive power terminal of the second comparing unit is configured to input a third voltage signal, where the amplitude of the second voltage signal is greater than or less than the amplitude of the third voltage signal, so as to implement output of tri-state logic.
According to some embodiments of the present invention, the chip further includes a logic receiving module, a first input end of the logic receiving module is connected to the IO port, a second input end of the logic receiving module is configured to input a second reference voltage signal, and an output end of the logic receiving module is configured to output a logic receiving result, so as to detect a logic output function of a chip pin.
According to some embodiments of the present invention, the second reference voltage signal includes a fourth voltage signal and a fifth voltage signal, the logic receiving result includes a first receiving result and a second receiving result, the logic receiving module includes a third comparing unit and a fourth comparing unit, a first input terminal of the third comparing unit and a first input terminal of the fourth comparing unit are both connected to the IO port, a second input terminal of the third comparing unit is used for inputting a fourth voltage signal, a second input terminal of the fourth comparing unit is used for inputting a fifth voltage signal, an output terminal of the third comparing unit is used for outputting the first receiving result, and an output terminal of the fourth comparing unit is used for outputting the second receiving result, so as to detect a logic output function of a chip pin.
According to some embodiments of the present invention, the logic receiving module further includes a first clamping unit and a second clamping unit, an output terminal of the third comparing unit outputs the first receiving result through the first clamping unit, and an output terminal of the fourth comparing unit is configured to output the second receiving result through the second clamping unit, so as to limit a magnitude of the first receiving result and the second receiving result.
According to another aspect of the invention, the chip pin testing device comprises the chip pin testing circuit.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a diagram illustrating a chip pin of an integrated circuit chip according to the related art;
FIG. 2 is a circuit diagram of a chip pin test circuit according to an embodiment of the present invention;
FIG. 3 is a circuit block diagram of a connectivity test module of the chip pin test circuit shown in FIG. 2;
FIG. 4 is a block circuit diagram of a connectivity test module of the chip pin test circuit according to some embodiments of the invention;
FIG. 5 is another block circuit diagram of the chip pin test circuit shown in FIG. 2;
FIG. 6 is a circuit schematic of the chip pin test circuit shown in FIG. 5;
FIG. 7 is a circuit schematic of a chip pin test circuit according to some embodiments of the invention;
FIG. 8 is a circuit schematic of a chip pin test circuit according to further embodiments of the present invention.
The reference numbers are as follows:
the circuit comprises a common resistor 100, a level output module 200, an wired-or unit 210, a connectivity test module 300, a signal detection unit 310, a constant current source circuit 321, a sine wave generation circuit 322, a switch control unit 330, a logic receiving module 400, a first clamping unit 410 and a second clamping unit 420.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and more than, less than, more than, etc. are understood as excluding the present number, and more than, less than, etc. are understood as including the present number. If there is a description of first and second for the purpose of distinguishing technical features only, this is not to be understood as indicating or implying a relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
High level means a high voltage as opposed to low level.
Low level means a low voltage as opposed to high level.
In the related art, referring to fig. 1, a chip pin of an integrated circuit chip is provided with a first diode connected in reverse with respect to ground, i.e., the anode of the first diode is grounded, and the cathode of the first diode is connected to the chip pin, for example, the diode D7 in fig. 1 is used as the first diode.
Referring to fig. 2, the chip pin testing circuit according to an embodiment of an aspect of the present invention includes a common resistor 100, a level output module 200, and a connectivity testing module 300; a first end of the common resistor 100 is used as an IO port, and a second end of the common resistor 100 is grounded; a first input end of the level output module 200 is used for inputting a level control signal, and an output end of the level output module 200 is connected with an IO port; the input end of the connectivity test module 300 is used for inputting a switch control signal, the input end and the output end of the connectivity test module 300 are connected with an IO port, and the output end of the connectivity test module 300 is used for outputting a test result.
The IO port is used for connecting chip pins; the level control signal is used for controlling the level output module 200 to output a level driving signal to the chip pin; the connectivity test module 300 is used for testing the connectivity of the chip pins; the common resistor 100 is used as a pull-down resistor of the level output module 200, so that the output end of the level output module 200 has a stable level state; the common resistor 100 is also used as one of the communication branches of the connectivity test module 300, and during the connectivity test, the voltages applied to the common resistor 100 are different based on whether the chip pins are faulty, so as to output the corresponding test result. The level output module 200 and the connectivity test module 300 share the common resistor 100, so that the level output module 200 can output a driving level signal to a chip pin, the connectivity test module 300 can perform connectivity test on the chip pin, and meanwhile, the number of components is reduced, thereby facilitating simplification of a circuit structure and reduction of cost, and in addition, the level output module 200 and the connectivity test module 300 are integrated conveniently, so that miniaturization and use are facilitated.
It should be noted that, referring to fig. 1 and fig. 2, in this embodiment, an input/output end of the connectivity test module 300 is connected to an IO port, and a chip pin to be tested is connected to the IO port, when the connectivity of the chip pin is normal, the chip pin is connected to the IO port, at this time, a connection branch is formed between the chip pin and the IO port, the connection branch is connected in parallel to the common resistor 100, a voltage is applied to the first diode and the common resistor 100, the IO port is in a first voltage state, and the connectivity test module 300 can output the first voltage state as a test result; when the connectivity of the chip pin is abnormal, the chip pin and the IO port are disconnected, a connection branch cannot be formed between the chip pin and the IO port, the voltage is loaded on the common resistor 100, the IO port is in the second voltage state, and the connectivity test module 300 may output the second voltage state as a test result. By using the common resistor 100 as one of the communication branches of the connectivity testing module 300, the IO port may be in the first voltage state or the second voltage state, and the connectivity testing module 300 outputs a corresponding testing result.
Referring to fig. 3 or 4, the connectivity test module 300 includes a signal detection unit 310, a signal generation unit (not shown in the figure), and a switch control unit 330, an input terminal of the switch control unit 330 is used as an input terminal of the connectivity test module 300, the switch control unit 330 is used to control the signal generation unit to output a test signal, an output terminal of the signal generation unit is connected to the IO port, an input terminal of the signal detection unit 310 is connected to the IO port, and an output terminal of the signal detection unit 310 is used as an output terminal of the connectivity test module 300. The signal generating unit is used for generating a test signal for testing a chip pin, such as a sine wave and a constant current; the switch control unit 330 is used for controlling the signal generation unit to output a test signal; the signal detection unit 310 is used to detect a voltage state of the IO port.
When connectivity test is required to be performed on the chip pin, the switch control unit 330 enables the signal generation unit to output a corresponding test signal, and the test signal passes through the chip pin or the common resistor 100, so that the IO port is in the first voltage state or the second voltage state, and the signal detection unit 310 outputs a corresponding test result to complete the connectivity test.
Referring to fig. 6, 7 or 8, the signal detection unit 310 includes a comparator U5, a resistor R3, a resistor R6 and a resistor R7, a first end of the resistor R3 is grounded, a second end of the resistor R3 is connected to a non-inverting input terminal of the comparator U5, a first end of the resistor R6 is connected to an output terminal of the comparator U5, a second end of the resistor R6 is connected to an inverting input terminal of the comparator U5, an output terminal of the comparator U5 is used as an output terminal of the signal detection unit 310, a first end of the resistor R7 is used as an input terminal of the signal detection unit 310, and a second end of the resistor R7 is connected to a non-inverting input terminal of the comparator U5 or an inverting input terminal of the comparator U5. The comparator U5 obtains the voltage state of the IO port through the resistor R7, and when the second end of the resistor R7 is connected to the inverting input terminal of the comparator U5, the comparator U5 inverts the voltage state and outputs the inverted voltage state as a test result; when the second terminal of the resistor R7 is connected to the non-inverting input terminal of the comparator U5, the comparator U5 outputs the voltage status as the test result.
Referring to fig. 3 and fig. 6, a specific example is illustrated, and the signal generating unit includes a constant current source circuit 321, an output terminal of the constant current source circuit 321 is connected to the IO port, and a controlled terminal of the constant current source is connected to a control terminal of the switch control unit 330.
Specifically, the constant current source circuit 321 includes a transistor Q1, a transistor Q2, and a resistor R8, wherein a collector of the transistor Q1 is used as an output terminal of the constant current source circuit 321, a base of the transistor Q1 is respectively connected to a base of the transistor Q2, a collector of the transistor Q2, and a first end of the resistor R8, a second end of the resistor R8 is grounded, and an emitter of the transistor Q1 and an emitter of the transistor Q2 are both used for inputting the sixth voltage signal.
The switch control unit 330 includes a transistor Q3, a transistor Q4, a resistor R9, a resistor R10, and a resistor R11, an emitter of the transistor Q4 is used to input a seventh voltage signal, a base of the transistor Q4 is connected to the first end of the resistor R11, a second end of the resistor R11 is used to input a switch control signal, a collector of the transistor Q4 is connected to the first end of the resistor R10 and the first end of the resistor R9, a second end of the resistor R9 is connected to the base of the transistor Q3, both the emitter of the transistor Q3 and the second end of the resistor R10 are used to input a sixth voltage signal, and a collector of the transistor Q3 is connected to the first end of the resistor R8.
The amplitude of the sixth voltage signal may be-5V, the amplitude of the seventh voltage signal may be 3.3V, and the output end of the constant current source circuit 321 is configured to output a constant current. When the switch control signal is a low level signal, the transistor Q3 and the transistor Q4 are turned on, the transistor Q1 and the transistor Q2 are turned off, and the collector of the transistor Q1 is in a high resistance state, that is, the constant current source circuit 321 is turned off by the switch control unit 330, and stops outputting the constant current, and the connectivity test module 300 stops working at this time; when the switch control signal is a high level signal, the transistor Q3 and the transistor Q4 are turned off, the transistor Q1 and the transistor Q2 are turned on, and the constant current flowing through the collector of the transistor Q2 is the same as the constant current flowing through the collector of the transistor Q1.
When the constant current source circuit 321 can output a constant current and the connectivity of the chip pins is normal, the constant current can flow from the anode of the first diode, i.e., the ground terminal, to the emitter of the triode Q1 through the cathode of the first diode and the collector of the triode Q1 in sequence; in this example, the voltage amplitude of the emitter of the transistor Q1 is-5V, and the voltage drop of the first diode may be between 0.4V and 0.8V, then the voltage amplitude of the input terminal of the signal detection unit 310 is between-0.8V and-0.4V.
When the constant current source can output a constant current and the connectivity of the chip pins is abnormal, the constant current can flow from the second end of the common resistor 100, namely the ground end, to the emitter of the triode Q1 through the first end of the common resistor 100 and the collector of the triode Q1 in sequence; in this example, the voltage amplitude of the emitter of the transistor Q1 is-5V, and the constant current flowing through the common resistor 100 will generate a large voltage drop, for example, a voltage drop of 4.9V, on the common resistor 100, and the voltage amplitude of the first terminal of the common resistor 100 is smaller than-0.8V and close to-5V, so that the voltage amplitude of the input terminal of the signal detection unit 310 is between-5V and-0.8V.
In the above example, the signal detection unit 310 may output the input in an inverted state, that is, when the test result output by the output terminal of the signal detection unit 310 is between 0.4V and 0.8V, the connectivity of the chip pin is normal, and when the test result output by the output terminal of the signal detection unit 310 is between 0.8V and 5V, the connectivity of the chip pin is abnormal. In the above example, the circuit structure of the connectivity testing module 300 is simple, and the common resistor 100 can be shared with the level output module 200, so that the common resistor 100 is used as one of the communication branches of the connectivity testing module 300, which is beneficial to simplifying the circuit and reducing the cost.
Referring to fig. 4 and 7, a signal generation unit including a sine wave generation circuit 322 is illustrated as another specific example, and an output terminal of the sine wave generation circuit 322 is connected to an IO port through a switch control unit 330.
Specifically, the switch control unit 330 includes a relay K1, a transistor Q5, and a resistor R12, a base of the transistor Q5 is connected to a first end of the resistor R12, a second end of the resistor R12 is used for inputting a switch control signal, an emitter of the transistor Q5 is grounded, a collector of the transistor Q5 is connected to a first end of a coil of the relay K1, a second end of the coil of the relay K1 is used for connecting a power supply, a first end of a switch of the relay K1 is connected to an output end of the sine wave generation circuit 322, and a second end of a switch of the relay K1 is connected to an IO port.
The sine wave generating circuit 322 is used for generating a sine wave signal; when the switch control signal is a low level signal, the switch of the relay K1 is turned on, and the connectivity test module 300 stops working; when the switch control signal is a high level signal, the switch of the relay K1 is closed, the sine wave signal generated by the sine wave generating circuit 322 can be loaded to the chip pin, and the connectivity test module 300 works normally.
When the connectivity test module 300 works normally and the connectivity of the chip pins is normal, in a positive half cycle of the sine wave signal, the sine wave signal flows from the output terminal of the sine wave generation circuit 322 to the second terminal of the common resistor 100 through the first terminal of the switch of the relay K1, the second terminal of the switch of the relay K1 and the first terminal of the common resistor 100 in sequence, and at this time, the input terminal of the signal detection unit 310 inputs the positive half cycle of the sine wave; in the negative half period of the sine wave signal, the sine wave signal flows from the anode of the first diode, i.e. the ground terminal, to the output terminal of the sine wave generating circuit 322 sequentially through the cathode of the first diode, the second terminal of the switch of the relay K1, and the first terminal of the switch of the relay K1, at this time, because the voltage drop of the first diode is small, the voltage amplitude of the first diode is close to the voltage amplitude of the ground terminal, i.e. the voltage amplitude of the first diode is close to zero, and then the voltage amplitude of the input terminal of the signal detecting unit 310 is close to zero.
When the connectivity test module 300 works normally and the connectivity of the chip pin is abnormal, the flow path of the sine wave signal changes in the negative half cycle of the sine wave signal, and the sine wave signal flows from the second end of the common resistor 100, i.e. the ground end, to the output end of the sine wave generation circuit 322 through the first end of the common resistor 100, the second end of the switch of the relay K1, and the first end of the switch of the relay K1 in sequence, at this time, because the voltage drop of the common resistor 100 is large, the voltage amplitude of the first end of the common resistor 100 is close to the voltage amplitude of the output end of the sine wave generation circuit 322, the input of the input end of the signal detection unit 310 is the negative half cycle of the sine wave, i.e. the signal detection unit 310 can output a complete sine wave in one cycle of the sine wave signal.
It should be noted that, in some embodiments, referring to fig. 8, the relay K1 may be replaced by an analog switch M1.
In the above example, the signal detection unit 310 may output the input in phase, that is, when the output end of the signal detection unit 310 outputs the positive half cycle of the sine wave signal in the positive half cycle of the sine wave signal, and outputs the voltage amplitude close to zero or outputs the voltage amplitude zero in the negative half cycle of the sine wave signal, the connectivity of the chip pins is normal; when the output end of the signal detection unit 310 outputs a complete sine wave within a cycle of a sine wave signal, the connectivity of the chip pins is abnormal. In the above example, the circuit structure of the connectivity testing module 300 is simple, and the common resistor 100 can be shared with the level output module 200, so that the common resistor 100 is used as one of the communication branches of the connectivity testing module 300, which is beneficial to simplifying the circuit and reducing the cost.
Referring to fig. 6, 7 or 8, the level control signal includes a first level signal and a second level signal, the level output module 200 includes a first comparing unit (not shown), a second comparing unit (not shown in the figure) and an or unit 210, wherein a first input end of the first comparing unit is used for inputting a first level signal, a second input end of the second comparing unit is used for inputting a second level signal, a second input end of the first comparing unit and a first input end of the second comparing unit are both used for inputting a first reference voltage signal, a negative power end of the first comparing unit and a negative power end of the second comparing unit are both used for inputting a first voltage signal with a voltage amplitude smaller than zero, an output end of the first comparing unit is connected with the first input end of the or unit 210, an output end of the second comparing unit is connected with the second input end of the or unit 210, and an output end of the or unit 210 is connected with an IO port.
The first level signal is used for controlling the output of the first comparison unit; the second level signal is used for controlling the output of the second comparison unit; the wired-or unit 210 is used for wired-or processing the output of the first comparing unit and the output of the second comparing unit to obtain a level driving signal.
When the positive power terminal of the first comparing unit and the positive power terminal of the second comparing unit input the same voltage signal, and the voltage signal can be a low level signal, the output terminal of the or unit 210 can output the low level signal, or the output terminal of the or unit 210 can be in a high resistance state; when the positive power supply terminals of the first and second comparison units input the same voltage signal, and the voltage signal may be a high level signal, the output terminal of the or unit 210 may output the high level signal, or the output terminal of the or unit 210 may be in a high resistance state.
Through the level output module 200, the IO port can be in a high impedance state, or the IO port can output a high level signal or a low level signal, so as to test the logic function of the chip pin, and the level output module 200 and the connectivity test module 300 share the common resistor 100, so that the common resistor 100 is used as a pull-down resistor when the level output module 200 works, which is beneficial to simplifying the circuit structure and reducing the cost.
The first reference voltage signal is used as a reference voltage of the first comparing unit and the second comparing unit, and the first reference voltage signal is used for comparing with an input first level signal or a second level signal; the voltage amplitude of the first reference voltage signal is less than zero; the absolute value of the voltage amplitude of the first reference voltage signal is greater than the voltage amplitude of the low level signal and less than the voltage amplitude of the high level signal.
The first comparing unit and the second comparing unit may each employ a voltage comparator, for example, referring to fig. 6 to 8, the voltage comparator U1 is used as the first comparing unit, and the voltage comparator U2 is used as the second comparing unit; the first input end of the first comparing unit may be used as the non-inverting input end of the first comparing unit, and may also be used as the inverting input end of the first comparing unit; a second input end of the second comparing unit may be used as a non-inverting input end of the second comparing unit, and may also be used as an inverting input end of the second comparing unit; when the first input terminal of the first comparing unit is used as the non-inverting input terminal of the first comparing unit, the second input terminal of the second comparing unit may also be used as the non-inverting input terminal of the second comparing unit; when the first input terminal of the first comparing unit is used as the inverting input terminal of the first comparing unit, the second input terminal of the second comparing unit may also be used as the inverting input terminal of the second comparing unit.
It should be noted that the first comparing unit and the second comparing unit may also be integrated chips with comparing functions, for example, integrated chips such as LM324, LM339, or LM 393.
Referring to fig. 6 to 8, the positive power terminal of the first comparing unit is used to input a second voltage signal, the positive power terminal of the second comparing unit is used to input a third voltage signal, and the voltage amplitude of the second voltage signal is greater than or less than that of the third voltage signal. Wherein the voltage amplitude of the second voltage signal is different from the voltage amplitude of the third voltage signal, so that the wired-or unit 210 can output a high level signal or a low level signal.
First level signal Second level signal Output terminal voltage state of wired-OR unit
Low level of electricity Low level of electricity High resistance state
High level Low level of electricity High level
Low level of electricity High level of voltage Low level of electricity
High level of voltage High level High level
TABLE 1
For example, referring to table 1 above, in table 1, the voltage amplitude of the second voltage signal is greater than the voltage amplitude of the third voltage signal, and the second voltage signal may be a high level signal, and the third voltage signal may be a low level signal, the or unit 210 may output the high level signal or the low level signal, or the output terminal of the or unit 210 may be in a high impedance state.
The voltage state of the output end of the wired-or unit 210 can be switched among a high level, a low level and a high impedance state, so that the IO port realizes the output of the tri-state logic, and thus the chip pin is driven to be in the high level state, the low level state or the high impedance state, so as to test the logic function of the chip pin.
It should be noted that, referring to fig. 6 and 7, the wired-or unit 210 includes a diode D1 and a diode D2, an anode of the diode D1 serves as a first input terminal of the wired-or unit 210, an anode of the diode D2 serves as a second input terminal of the wired-or unit 210, a cathode of the diode D1 is connected to a cathode of the diode D2, and a cathode of the diode D1 and a cathode of the diode D2 together serve as an output terminal of the wired-or unit 210.
It is noted that, referring to fig. 8, in some embodiments, or unit 210 includes transistor Q6 and transistor Q7, the base of transistor Q6 is connected to the collector of transistor Q6, and the base of transistor Q6 and the collector of transistor Q6 together serve as a first input of or unit 210, the base of transistor Q7 is connected to the collector of transistor Q7, and the base of transistor Q7 and the collector of transistor Q7 together serve as a second input of or unit 210, the emitter of transistor Q6 is connected to the emitter of transistor Q7, and the emitter of transistor Q6 and the emitter of transistor Q7 together serve as an output of or unit 210.
Referring to fig. 5, the chip pin test circuit further includes a logic receiving module 400, a first input terminal of the logic receiving module 400 is connected to the IO port, a second input terminal of the logic receiving module 400 is used for inputting a second reference voltage signal, and an output terminal of the logic receiving module 400 is used for outputting a logic receiving result. The logic receiving module 400 is configured to receive a logic signal output by a chip pin and output a logic receiving result, where the logic receiving result is used to indicate a voltage state of the chip pin; specifically, a signal input from the first input terminal of the logic receiving module 400 is compared with a second reference voltage signal input from the second input terminal of the logic receiving module 400, and the comparison result is used as the logic receiving result. The logic signal is converted into a logic receiving result by the logic receiving module 400, so as to detect the voltage state of the chip pin. In addition, the common resistor 100 can be used as a voltage dividing resistor of the logic receiving module 400, which is beneficial to simplifying the circuit structure and reducing the cost.
It should be noted that the voltage state of the chip pin may be a high level state, a low level state, or a high impedance state. Before the voltage state of the chip pin is detected by the logic receiving module 400, the output terminal of the level output module 200 is in a high impedance state under the control of the level control signal, so that the voltage state of the input terminal of the logic receiving module 400 is determined by the voltage state of the chip pin.
Referring to fig. 6 to 8, the second reference voltage signal includes a fourth voltage signal and a fifth voltage signal, the logic reception result includes a first reception result and a second reception result, the logic reception module 400 includes a third comparison unit (not shown) and a fourth comparison unit (not shown), a first input terminal of the third comparison unit and a first input terminal of the fourth comparison unit are both connected to the IO port, a second input terminal of the third comparison unit is used for inputting the fourth voltage signal, a second input terminal of the fourth comparison unit is used for inputting the fifth voltage signal, an output terminal of the third comparison unit is used for outputting the first reception result, and an output terminal of the fourth comparison unit is used for outputting the second reception result.
The third comparison unit is used for comparing the fourth voltage signal with a logic signal output by a chip pin to obtain and output a first receiving result; the fourth comparing unit is used for comparing the fifth voltage signal with the logic signal output by the chip pin to obtain and output a second receiving result. The first receiving result is used for indicating a comparison result between the fourth voltage signal and a logic signal output by a chip pin; the second receiving result is used for indicating a comparison result between the fifth voltage signal and the logic signal output by the chip pin; the first reception result and the second reception result constitute a logic reception result, so that the logic reception result can indicate the voltage state of the chip pin, that is, the logic reception result indicates that the voltage state of the chip pin is a high level state, a low level state, or a high impedance state.
Voltage state of chip pin First received result Second reception result
High level High level High level
Low level of electricity Low level of electricity Low level of electricity
High resistance state Low level of electricity High level
TABLE 2
Referring to fig. 6 and table 2 described above, OUT1 represents the first reception result in table 2, and OUT2 represents the second reception result in table 2.
In addition, the common resistor 100 may be used as a voltage dividing resistor of the third comparing unit and the fourth comparing unit, which is beneficial to simplifying the circuit structure and reducing the cost.
It should be noted that, the third comparing unit and the fourth comparing unit may each adopt a voltage comparator, for example, referring to fig. 6 to 8, the voltage comparator U3 is used as the third comparing unit, and the voltage comparator U4 is used as the fourth comparing unit; the third comparing unit and the fourth comparing unit may also be integrated chips with comparing function, for example, integrated chips such as LM324, LM339, or LM 393.
Referring to fig. 6 to 8, the logic receiving module 400 further includes a first clamping unit 410 and a second clamping unit 420, wherein an output terminal of the third comparing unit outputs a first receiving result through the first clamping unit 410, and an output terminal of the fourth comparing unit is configured to output a second receiving result through the second clamping unit 420. The first clamping unit 410 is configured to clamp an output of the third comparing unit, so that a voltage amplitude of the first receiving result is within a suitable voltage range, so as to avoid that the voltage amplitude of the first receiving result is too high, for example, so that the voltage amplitude of the first receiving result is within 3.3V; the second clamping unit 420 is used for clamping the output of the fourth comparing unit so that the voltage amplitude of the second receiving result is within a suitable voltage range to avoid the voltage amplitude of the second receiving result being too high, for example, so that the voltage amplitude of the second receiving result is within 3.3V. Through the first clamping unit 410 and the second clamping unit 420, the voltage amplitude of the first clamping unit 410 and the voltage amplitude of the second clamping unit 420 are both within a proper voltage range, so that the corresponding circuit module can be accessed to read the logic receiving result according to actual requirements in the following process, that is, the circuit module accessed according to actual requirements in the following process is prevented from being damaged due to overhigh voltage amplitude of the logic receiving result.
It should be noted that, referring to fig. 6 and 7, the first clamping unit 410 includes a diode D3 and a resistor R1, a first end of the resistor R1 is used for inputting a clamping voltage, a second end of the resistor R1 is connected to an anode of the diode D3, a cathode of the diode D3 is connected to an output end of the third comparing unit, a second end of the resistor R1 and an anode of the diode D3 jointly serve as an output end of the first clamping unit 410, and a circuit structure of the second clamping unit 420 may be the same as that of the first clamping unit 410. The clamp voltage may be 3.3V or 5V.
It should be noted that, referring to fig. 8, in some embodiments, the first clamping unit 410 includes a transistor Q8 and a resistor R13, a first end of the resistor R13 is used for inputting a clamping voltage, a second end of the resistor R13 is connected to a base of the transistor Q8 and a collector of the transistor Q8, a second end of the resistor R13 is used as an output end of the first clamping unit 410, an emitter of the transistor Q8 is connected to an output end of the third comparing unit, and a circuit structure of the second clamping unit 420 may be the same as that of the first clamping unit 410.
In another aspect, an embodiment of the present invention provides a chip pin testing apparatus, including the chip pin testing circuit.
The contents in the chip pin test circuit embodiment are all applicable to the chip pin test device embodiment, the functions specifically realized by the chip pin test device embodiment are the same as those realized in the chip pin test circuit embodiment, and the beneficial effects achieved by the chip pin test circuit embodiment are also the same as those achieved by the chip pin test circuit embodiment.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.

Claims (10)

1. A chip pin test circuit, comprising:
a first end of the common resistor is used as an IO port, and a second end of the common resistor is grounded;
a first input end of the level output module is used for inputting a level control signal, and an output end of the level output module is connected with the IO port;
and the input end of the connectivity test module is used for inputting a switch control signal, the input end and the output end of the connectivity test module are connected with the IO port, and the output end of the connectivity test module is used for outputting a test result.
2. The chip pin testing circuit according to claim 1, wherein the connectivity testing module comprises a signal detecting unit, a signal generating unit and a switch control unit, an input terminal of the switch control unit is used as an input terminal of the connectivity testing module, the switch control unit is used to control the signal generating unit to output a testing signal, an output terminal of the signal generating unit is connected to the IO port, an input terminal of the signal detecting unit is connected to the IO port, and an output terminal of the signal detecting unit is used as an output terminal of the connectivity testing module.
3. The CSP circuit of claim 2, wherein the signal generation unit comprises a sine wave generation circuit, and an output terminal of the sine wave generation circuit is connected to the IO port through the switch control unit.
4. The chip pin test circuit according to claim 2, wherein the signal generating unit comprises a constant current source circuit, an output terminal of the constant current source circuit is connected to the IO port, and a controlled terminal of the constant current source is connected to the control terminal of the switch control unit.
5. The chip pin test circuit according to claim 1, wherein the level control signal comprises a first level signal and a second level signal, the level output module comprises a first comparison unit, a second comparison unit and a wired-or unit, a first input terminal of the first comparison unit is used for inputting the first level signal, a second input terminal of the second comparison unit is used for inputting the second level signal, a second input terminal of the first comparison unit and a first input terminal of the second comparison unit are both used for inputting a first reference voltage signal, a negative power terminal of the first comparison unit and a negative power terminal of the second comparison unit are both used for inputting a first voltage signal with a voltage amplitude smaller than zero, an output terminal of the first comparison unit is connected with the first input terminal of the wired-or unit, and an output terminal of the second comparison unit is connected with the second input terminal of the wired-or unit, and the output end of the wired-or unit is connected with the IO port.
6. The chip pin test circuit according to claim 5, wherein the positive power terminal of the first comparing unit is used for inputting a second voltage signal, the positive power terminal of the second comparing unit is used for inputting a third voltage signal, and the voltage amplitude of the second voltage signal is greater than or less than the voltage amplitude of the third voltage signal.
7. The chip pin test circuit according to claim 1, further comprising a logic receiving module, wherein a first input terminal of the logic receiving module is connected to the IO port, a second input terminal of the logic receiving module is configured to input a second reference voltage signal, and an output terminal of the logic receiving module is configured to output a logic receiving result.
8. The chip pin test circuit according to claim 7, wherein the second reference voltage signal includes a fourth voltage signal and a fifth voltage signal, the logic reception result includes a first reception result and a second reception result, the logic reception module includes a third comparison unit and a fourth comparison unit, a first input terminal of the third comparison unit and a first input terminal of the fourth comparison unit are both connected to the IO port, a second input terminal of the third comparison unit is used for inputting the fourth voltage signal, a second input terminal of the fourth comparison unit is used for inputting the fifth voltage signal, an output terminal of the third comparison unit is used for outputting the first reception result, and an output terminal of the fourth comparison unit is used for outputting the second reception result.
9. The chip pin test circuit according to claim 8, wherein the logic receiving module further comprises a first clamping unit and a second clamping unit, an output terminal of the third comparing unit outputs the first receiving result through the first clamping unit, and an output terminal of the fourth comparing unit is configured to output the second receiving result through the second clamping unit.
10. A chip pin test apparatus comprising the chip pin test circuit according to any one of claims 1 to 9.
CN202210518119.2A 2022-05-12 2022-05-12 Chip pin test circuit and equipment Pending CN114994497A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116165510A (en) * 2022-12-29 2023-05-26 无锡晟朗微电子有限公司 Communication device for chip test
CN117031255A (en) * 2023-08-30 2023-11-10 北京中科格励微科技有限公司 Chip test system sharing chip function pins
CN117347839A (en) * 2023-12-05 2024-01-05 飞腾信息技术有限公司 Chip test circuit and chip

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116165510A (en) * 2022-12-29 2023-05-26 无锡晟朗微电子有限公司 Communication device for chip test
CN116165510B (en) * 2022-12-29 2023-11-24 无锡晟朗微电子有限公司 Communication device for chip test
CN117031255A (en) * 2023-08-30 2023-11-10 北京中科格励微科技有限公司 Chip test system sharing chip function pins
CN117347839A (en) * 2023-12-05 2024-01-05 飞腾信息技术有限公司 Chip test circuit and chip
CN117347839B (en) * 2023-12-05 2024-03-12 飞腾信息技术有限公司 Chip test circuit and chip

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