CN114979166A

CN114979166A - Consensus node determination method, device and storage medium

Info

Publication number: CN114979166A
Application number: CN202210647305.6A
Authority: CN
Inventors: 任杰; 薛淼; 任梦璇; 刘千仞; 王光全
Original assignee: China United Network Communications Group Co Ltd
Current assignee: China United Network Communications Group Co Ltd
Priority date: 2022-06-09
Filing date: 2022-06-09
Publication date: 2022-08-30
Anticipated expiration: 2042-06-09
Also published as: CN114979166B

Abstract

The application provides a consensus node determination method, a consensus node determination device and a storage medium, relates to the technical field of block chains, and can solve the problem of low consensus efficiency in the related technology. The method comprises the following steps: determining a first vertex array and vertex parameters of m vertexes; the first vertex array comprises the identifiers of m vertexes, and the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights; sending a first vertex array to a nodes; receiving a second vertex arrays; a second vertex array is generated by randomly ordering nodes corresponding to the second vertex array according to the first vertex array; sending vertex parameters of m vertexes to a nodes; receiving a shortest paths; a shortest path is determined by a node corresponding to the shortest path according to the directed acyclic graph; the target node is a node corresponding to the directed acyclic graph; and determining a consensus node according to the a shortest paths, wherein the consensus node is used for performing block writing. The present application can provide consensus efficiency.

Description

Consensus node determination method, device and storage medium

Technical Field

The present application relates to the field of block chain technologies, and in particular, to a method, an apparatus, and a storage medium for determining a consensus node.

Background

Consensus (consensus) algorithms are the mechanism of algorithms in block chain (block chain) systems that allow each node to agree on a consensus. Since the blockchain is a distributed system, each node in the blockchain needs to have a common knowledge to determine the node to perform a new block write.

Current consensus algorithms are generally classified into a contention-type consensus algorithm and a negotiation-type consensus algorithm, wherein the contention-type consensus algorithm usually consumes a large amount of resources (e.g., power resources, computing resources) to achieve consensus. The negotiation-type consensus algorithm typically requires each node to perceive the results of other node responses to consensus information (e.g., block write operations) to achieve consensus. This results in an excessively high communication complexity of the method, and the more nodes in the blockchain system, the longer it takes to achieve consensus. Therefore, the current consensus algorithm has the problem of low consensus efficiency.

Disclosure of Invention

The application provides a consensus node determination method, a consensus node determination device and a storage medium, which can improve consensus efficiency.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, the present application provides a consensus node determining method, including: determining a first vertex array and vertex parameters of m vertexes; the first vertex array comprises m vertex identifiers, and the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights; m is a positive integer; sending a first vertex array to a nodes; a is a positive integer; receiving a second vertex arrays; the a second vertex arrays correspond to the a nodes one by one; a second vertex array is generated by randomly ordering nodes corresponding to the second vertex array according to the first vertex array; sending vertex parameters of m vertexes to a nodes; receiving a shortest paths; a shortest paths correspond to a nodes one by one; a shortest path is determined by a node corresponding to the shortest path according to the directed acyclic graph; a directed acyclic graph is generated by the target node according to the second vertex array corresponding to the target node and the vertex parameters of the m vertexes; the target node is a node corresponding to the directed acyclic graph; and determining a consensus node according to the a shortest paths, wherein the consensus node is used for performing block writing.

The scheme at least has the following beneficial effects: the consensus module determines a first vertex array and related vertex parameters required by generating the directed acyclic graph, indicates that vertices in the first vertex array determined by the a node pairs are randomly sequenced, and sends the related vertex parameters to the a nodes after generating a second vertex array, so that the a nodes generate respective directed acyclic graphs according to the second vertex array and the vertex parameters respectively, and determine the shortest path of the directed acyclic graph. Since the vertex ordering of each node is random, the shortest path of each directed acyclic graph that is finally determined is also random. The consensus module takes the node corresponding to the directed acyclic graph with the minimum shortest path as the node for performing block writing, so that the nodes in the block chain can achieve consensus. Compared with a competitive consensus algorithm in the related art, the method for obtaining the nodes for executing block writing based on the shortest path of the directed acyclic graph does not need to consume excessive power and calculation resources. Compared with a negotiation type consensus algorithm in the related technology, the technical scheme provided by the application only relates to concurrent communication between the consensus module and the node, the communication complexity is maintained at O (n), and the time required by consensus is greatly reduced. Therefore, the technical scheme effectively improves the consensus efficiency.

With reference to the first aspect, in a possible implementation manner, the method includes: and determining the node with the minimum shortest path in the a nodes as a consensus node.

With reference to the first aspect, in a possible implementation manner, the method includes: receiving a directed acyclic graphs; a directed acyclic graph corresponds to a nodes one by one; sending first data verification information of a nodes to a verification node; the first data verification information comprises at least one of a second vertex arrays, a directed acyclic graphs and a shortest paths; verifying that the node is one or more nodes in a nodes; receiving data verification results of a nodes sent by a verification node; the data verification result comprises data verification passing or data verification failing; determining a node meeting a first preset condition in the a nodes as a consensus node; the first preset condition includes: and the data verification result is that the data passes the verification and the shortest path is the minimum.

With reference to the first aspect, in a possible implementation manner, the method includes: receiving a directed acyclic graphs; a directed acyclic graph corresponds to a nodes one by one; removing nodes with the numerical value of the shortest path being larger than a preset threshold value from the a nodes to obtain b nodes; b is a positive integer less than or equal to a; sending second data verification information of the b nodes to the verification node; the second data verification information comprises at least one of b second vertex arrays, b directed acyclic graphs and b shortest paths; verifying that the node is one or more nodes in a nodes; receiving data verification results of b nodes sent by a verification node; the data verification result comprises data verification passing or data verification failing; determining nodes meeting a first preset condition in the b nodes as consensus nodes; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

With reference to the foregoing first aspect, in a possible implementation manner, the method includes: randomly extracting m blocks; the m blocks correspond to m vertexes included in the first vertex array one by one; determining vertex parameters of m vertexes according to the block information of the m blocks; the block information includes at least one of a block id and block writing node information.

With reference to the first aspect, in a possible implementation manner, the method includes: determining the weight of the vertex according to the block identifier under the condition that the block information comprises the block identifier; in the case where the block information includes block writing node information, the degree of the vertex is determined according to the block writing node information.

In a second aspect, the present application provides a consensus node determining method, including: receiving a first vertex array sent by a consensus module; the first vertex array comprises identifications of m vertices; m is a positive integer; randomly ordering the identifiers of m vertexes in the first vertex array to generate a second vertex array; sending a second vertex array to the consensus module; receiving vertex parameters of m vertexes sent by the consensus module; the vertex parameters comprise at least one of the degree of the vertex, the weight of the vertex and the block height; generating a directed acyclic graph according to the second vertex array and the vertex parameters of the m vertexes; determining a shortest path according to the directed acyclic graph, and sending the shortest path to the consensus module; the shortest path is used for the consensus module to determine a consensus node, and the consensus node is used for performing block writing.

With reference to the second aspect, in a possible implementation manner, the method further includes: sending a directed acyclic graph to a consensus module; under the condition that first data verification information of a nodes sent by a consensus module is received, verifying the first data verification information to obtain data verification results of the a nodes; the first data verification information comprises at least one of a second vertex arrays, a directed acyclic graphs and a shortest paths; the data verification result comprises data verification passing or data verification failing; a is a positive integer; and sending the data verification results of the a nodes to the consensus module.

With reference to the second aspect, in a possible implementation manner, the method further includes: sending a directed acyclic graph to a consensus module; under the condition of receiving second data verification information of the b nodes sent by the consensus module, verifying the second data verification information to obtain data verification results of the b nodes; the second data verification information comprises at least one of b second vertex arrays, b directed acyclic graphs and b shortest paths; the data verification result comprises data verification passing or data verification failing; and sending the data verification results of the b nodes to the consensus module.

With reference to the second aspect, in a possible implementation manner, the method further includes: determining whether the corresponding directed acyclic graph is correct or not according to a second vertex array in the target data verification information; and/or determining whether the corresponding shortest path is correct according to the directed acyclic graph in the target data verification information; the target data verification information is first data verification information or second data verification information.

In a third aspect, the present application provides a consensus node determination apparatus, which includes a communication unit and a processing unit; the processing unit is used for determining the first vertex array and vertex parameters of the m vertexes; the first vertex array comprises m vertex identifications, and the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights; m is a positive integer; a communication unit, configured to send a first vertex array to a nodes; a is a positive integer; the communication unit is also used for receiving a second vertex arrays; the a second vertex arrays correspond to the a nodes one by one; a second vertex array is generated by randomly sequencing nodes corresponding to the second vertex array according to the first vertex array; the communication unit is also used for sending the vertex parameters of the m vertexes to the a nodes; a communication unit, further configured to receive a shortest paths; a shortest paths correspond to a nodes one by one; a shortest path is determined by a node corresponding to the shortest path according to the directed acyclic graph; a directed acyclic graph is generated by the target node according to the second vertex array corresponding to the target node and the vertex parameters of the m vertexes; the target node is a node corresponding to the directed acyclic graph; and the processing unit is also used for determining a consensus node according to the a shortest paths, and the consensus node is used for executing block writing.

With reference to the third aspect, in a possible implementation manner, the processing unit is further configured to determine a node with a shortest path among the a nodes as a consensus node.

With reference to the third aspect, in a possible implementation manner, the communication unit is further configured to receive a directed acyclic graph; a directed acyclic graph corresponds to a nodes one by one; the communication unit is also used for sending first data verification information of a nodes to the verification node; the first data verification information comprises at least one of a second vertex arrays, a directed acyclic graphs and a shortest paths; verifying that the node is one or more nodes in a nodes; the communication unit is also used for receiving the data verification results of the a nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing; the processing unit is further used for determining a node meeting a first preset condition in the a nodes as a consensus node; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

With reference to the third aspect, in a possible implementation manner, the communication unit is further configured to receive a directed acyclic graph; a directed acyclic graph corresponds to a nodes one by one; the processing unit is also used for removing the nodes of which the numerical value of the shortest path is greater than a preset threshold value from the a nodes to obtain b nodes; b is a positive integer less than or equal to a; the communication unit is also used for sending second data verification information of the b nodes to the verification node; the second data verification information comprises at least one of b second vertex arrays, b directed acyclic graphs and b shortest paths; verifying that the node is one or more nodes in a nodes; the communication unit is also used for receiving the data verification results of the b nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing; the processing unit is further used for determining the nodes meeting the first preset condition in the b nodes as consensus nodes; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

With reference to the third aspect, in a possible implementation manner, the processing unit is further configured to randomly extract m blocks; the m blocks correspond to m vertexes included in the first vertex array one by one; determining vertex parameters of m vertexes according to the block information of the m blocks; the block information includes at least one of a block id and block writing node information.

With reference to the third aspect, in a possible implementation manner, the processing unit is further configured to determine, when the block information includes a block identifier, a weight of the vertex according to the block identifier; in the case where the block information includes block writing node information, the degree of the vertex is determined according to the block writing node information.

In a fourth aspect, the present application provides a consensus node determination apparatus, which includes a communication unit and a processing unit; the communication unit is used for receiving the first vertex array sent by the consensus module; the first vertex array comprises identifications of m vertices; m is a positive integer; the processing unit is used for randomly sequencing the identifiers of the m vertexes in the first vertex array to generate a second vertex array; the communication unit is also used for sending the second vertex array to the consensus module; the communication unit is also used for receiving the vertex parameters of the m vertexes sent by the consensus module; the vertex parameters comprise at least one of the degree of the vertex, the weight of the vertex and the block height; the processing unit is further used for generating a directed acyclic graph according to the second vertex array and the vertex parameters of the m vertexes; the processing unit is also used for determining the shortest path according to the directed acyclic graph; the shortest path is used for the consensus module to determine a consensus node, and the consensus node is used for executing block writing; and the communication unit is also used for sending the shortest path to the consensus module.

With reference to the fourth aspect, in a possible implementation manner, the communication unit is further configured to send a directed acyclic graph to the consensus module; the processing unit is further used for verifying the first data verification information under the condition that the first data verification information of the a nodes sent by the consensus module is received, and obtaining data verification results of the a nodes; the first data verification information comprises at least one of a second vertex arrays, a directed acyclic graphs and a shortest paths; the data verification result comprises data verification passing or data verification failing; a is a positive integer; and the communication unit is also used for sending the data verification results of the a nodes to the consensus module.

With reference to the fourth aspect, in a possible implementation manner, the communication unit is further configured to send the directed acyclic graph to the consensus module; the processing unit is further used for verifying the second data verification information under the condition that the second data verification information of the b nodes sent by the consensus module is received, and obtaining data verification results of the b nodes; the second data verification information comprises at least one of b second vertex arrays, b directed acyclic graphs and b shortest paths; the data verification result comprises data verification passing or data verification failing; and the communication unit is also used for sending the data verification results of the b nodes to the consensus module.

With reference to the fourth aspect, in a possible implementation manner, the processing unit is further configured to determine whether the corresponding directed acyclic graph is correct according to the second vertex array in the target data verification information; and/or determining whether the corresponding shortest path is correct according to the directed acyclic graph in the target data verification information; the target data verification information is first data verification information or second data verification information.

In a fifth aspect, the present application provides a consensus node determining apparatus, including: a processor and a communication interface; the communication interface is coupled to a processor for executing a computer program or instructions for implementing the consensus node determination method as described in the first aspect and any of the possible implementations of the first aspect or for implementing the consensus node determination method as described in the second aspect and any of the possible implementations of the second aspect.

In a sixth aspect, the present application provides a computer-readable storage medium having stored therein instructions that, when executed on a terminal, cause the terminal to perform a consensus node determination method as described in the first aspect and any one of the possible implementations of the first aspect or to perform a consensus node determination method as described in the second aspect and any one of the possible implementations of the second aspect.

In a seventh aspect, the present application provides a computer program product comprising instructions that, when run on a consensus node determination apparatus, cause the consensus node determination apparatus to perform the consensus node determination method as described in the first aspect and any one of the possible implementations of the first aspect or to perform the consensus node determination method as described in the second aspect and any one of the possible implementations of the second aspect.

In an eighth aspect, the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a computer program or instructions to implement the consensus node determination method as described in the first aspect and any one of the possible implementations of the first aspect, or to implement the consensus node determination method as described in the second aspect and any one of the possible implementations of the second aspect.

In particular, the chip provided herein further comprises a memory for storing computer programs or instructions.

It should be noted that all or part of the computer instructions may be stored on the computer readable storage medium. The computer readable storage medium may be packaged with or without a processor of the apparatus, and is not limited in this application.

In a ninth aspect, the present application provides a consensus node determining system, including: a first consensus node determining apparatus and at least one second consensus node determining apparatus, wherein the first consensus node determining apparatus is configured to perform the consensus node determining method as described in the first aspect and any one of the possible implementations of the first aspect, and the second consensus node determining apparatus is configured to perform the consensus node determining method as described in the second aspect and any one of the possible implementations of the second aspect.

For the description of the second aspect to the ninth aspect in the present invention, reference may be made to the detailed description of the first aspect; in addition, for the beneficial effects described in the second to ninth aspects, reference may be made to the beneficial effect analysis of the first aspect, which is not described herein again.

In the present application, the names of the above-mentioned consensus node determining means do not constitute a limitation on the devices or functional modules themselves, which may appear by other names in an actual implementation. Insofar as the functions of the respective devices or functional blocks are similar to those of the present invention, they are within the scope of the claims of the present invention and their equivalents.

These and other aspects of the invention will be more readily apparent from the following description.

Drawings

Fig. 1 is a schematic architecture diagram of a consensus node determination system according to an embodiment of the present disclosure;

fig. 2 is a flowchart of a method for determining a consensus node according to an embodiment of the present disclosure;

FIG. 3 is a flowchart illustrating a first objective operation provided by an embodiment of the present application;

FIG. 4 is a flowchart illustrating a second objective operation provided by embodiments of the present application;

FIG. 5 is a graph of a directed acyclic graph according to an embodiment of the present disclosure;

fig. 6 is a flowchart of another method for determining a consensus node according to an embodiment of the present disclosure;

fig. 7 is a flowchart of another method for determining a consensus node according to an embodiment of the present application;

fig. 8 is a flowchart of another method for determining a consensus node according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a consensus node determining apparatus according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of another consensus node determining apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.

The terms "first" and "second" and the like in the description and drawings of the present application are used for distinguishing different objects or for distinguishing different processes for the same object, and are not used for describing a specific order of the objects.

Furthermore, the terms "including" and "having," and any variations thereof, as referred to in the description of the present application, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements but may alternatively include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the description of the present application, the meaning of "a plurality" means two or more unless otherwise specified.

Hereinafter, terms related to the embodiments of the present application are explained for the convenience of the reader.

(1) Directed Acyclic Graph (DAG)

A directed acyclic graph is a data structure of a graph, consisting of a plurality of vertices and paths between the vertices. The directed graph refers to a direction in which paths between vertexes exist in the directed acyclic graph, and the acyclic graph refers to a point which is returned to any vertex in the directed acyclic graph after any vertex cannot pass through a plurality of paths.

(2) Consensus algorithm

The consensus algorithm is an algorithm mechanism that allows each node to achieve consensus in a blockchain system. Since the blockchain is a distributed system, each node in the blockchain needs to have a common knowledge to determine the node to perform a new block write.

Current consensus algorithms are generally classified into a competitive consensus algorithm and a negotiation consensus algorithm, wherein for the competitive consensus algorithm, such as a proof of work (POW) algorithm, each node needs to obtain a value satisfying a specified condition (e.g., a hash algorithm) through a large amount of calculation, and the node calculated first obtains an authority (accounting authority) to write into a block. However, this method results in a large amount of resources (e.g., power resources, computing resources) being consumed, and costsToo high. For a negotiation type consensus algorithm, for example, a PBFT (physical Byzantine fault tolerance) algorithm, the algorithm sends consensus information (e.g., block write operation) to other nodes through a master node, the other nodes respond to the consensus information and send response results to nodes other than the master node, and each node achieves consensus based on the response results of all the nodes and feeds back the consensus to the master node. The algorithm needs each node to be able to sense the response result of other nodes to the consensus information, resulting in communication complexity (complexity is O (n) ² ) Too high, the more nodes in the blockchain system, the longer it takes to achieve consensus. Therefore, the current consensus algorithm has the problem of low consensus efficiency.

In view of this, the present application provides a consensus node determining method, in which a consensus module determines vertices and related vertex parameters required for generating a directed acyclic graph, randomly sorts the vertices of nodes, generates respective directed acyclic graphs according to the vertex parameters, and determines a shortest path of the directed acyclic graphs. Since the vertex ordering of each node is random, the resulting shortest path is also random. The consensus module takes the node with the minimum value of the shortest path as the node for performing the block writing. According to the scheme, on the premise of ensuring the randomness and the fairness of the consensus process, a large amount of resources are not required to be consumed, meanwhile, the communication complexity is low, excessive time is not required to be consumed, and therefore the consensus efficiency is improved.

The following detailed description of embodiments of the present application will be made with reference to the accompanying drawings.

Fig. 1 is an architecture diagram of a consensus node determination system 10 according to an embodiment of the present disclosure. As shown in fig. 1, the consensus node determination system 10 includes: one or more nodes 101, one or more consensus modules 102, and a blockchain 103. Wherein, the nodes 101 are connected through a communication link.

It should be noted that a distributed architecture is adopted between each node 101. The block chain 103 is stored in a storage unit of each node 101. Meanwhile, the blockchain 103 stored in each node 101 is the same. The relevant operations of node 101 are stored in blockchain 103 and synchronized to each node 101 in the consensus node determination system 10.

In addition, each node 101 includes a consensus module 102, and each node 101 performs a consensus operation through the consensus module 102, and when the nodes 101 in the system 10 are determined to have consensus, the nodes 101 determined to have consensus perform a new block write operation and synchronize to each node 101.

It should be noted that although the physical structures of the node 101 and the common module 102 may be the same device, in the actual execution process, the node 101 cannot acquire the operation information executed by the common module 102 included in the node 101, and correspondingly, the common module 102 cannot acquire the operation information executed by the node 101. The node 101 and the consensus module 102 may be logically implemented as two distinct execution entities.

The consensus module 102 may be an application program executing the consensus node determination method, a processing chip provided in each node 101 executing the consensus node determination method, or a consensus node determination apparatus executing the consensus node determination method.

In a possible implementation manner, the consensus module 102 may also be an independent consensus node determining device, and the consensus node determining device and each node 101 determine the node 101 performing block writing according to the consensus node determining method provided in this application.

The consensus module 102 is configured to determine a first vertex array and vertex parameters of m vertices of the directed acyclic graph.

The first vertex array comprises identifications of m vertices, the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights, and m is a positive integer.

The degree of a vertex refers to the number of paths connecting to the vertex. For example, vertex 1 is connected to vertex 2 and vertex 3 is connected to vertex 2. The degree of vertex 2 is 2, and the degrees of vertex 1 and vertex 3 are both 1. For a directed graph, the degrees of the vertices again include in-degrees and out-degrees. The in-degree of the vertex refers to the number of paths in which the direction of the connection path points to itself. Out-degrees of vertices refer to the number of paths connecting the path directions to other vertices.

For example, in the case that the consensus module 102 is an execution module in each node 101, the above scheme may be steps executed by the consensus module 102 in any one node 101.

Consensus module 102 is also configured to send a first vertex array to each node 101. Accordingly, each node 101 is configured to receive the first vertex array sent by the consensus module 102.

The node 101 is configured to randomly sort the identifiers of the m vertices in the first vertex array, generate a second vertex array, and send the second vertex array to the consensus module 102. Accordingly, the consensus module 102 is configured to receive the second vertex parameter sent by the node 101.

It should be noted that the ordering of the vertices in the second vertex array generated by each node 101 is completely random, and therefore, the directed acyclic graph determined based on the second vertex array in the subsequent operation and the corresponding shortest path are also completely random. In this way, the technical solution provided by the present application can ensure that the probability that each node 101 becomes a node of a write block in the consensus process is the same, and the solution provided by the present application is more fair compared to a solution in which the higher the node computation power is, the higher the probability that the node becomes a node of a write block is in the related art.

The consensus module 102 is further configured to send vertex parameters for the m vertices to each node 101. Accordingly, the node 101 is configured to receive the vertex parameters of the m vertices sent by the consensus module 102.

It should be noted that after the vertex parameters of m vertices are obtained, the node 101 may calculate all possible situations of the directed acyclic graph and the corresponding shortest paths through traversal, so as to obtain an optimal solution. To avoid the node 101 performing the above-mentioned violation, the consensus module 102 sends the vertex parameters of the m vertices to the node 101 after receiving the second vertex array fed back by the node 101. In this way, after the node 101 generates the second vertex array, the corresponding directed acyclic graph of the node 101 is already determined, and the consensus module 102 may verify whether the node 101 violates the operation based on the second vertex array sent by the node 101 and the subsequently generated directed acyclic graph, thereby ensuring fairness of the consensus scheme.

Node 101 is further configured to generate a directed acyclic graph from the second vertex array and the vertex parameters of the m vertices and determine a shortest path in the directed acyclic graph.

The node 101 is also configured to send the shortest path to the consensus module 102. Accordingly, the consensus module 102 is configured to receive the shortest path sent by the node 101.

The consensus module 102 is further configured to determine a node performing block writing according to the shortest path sent by each node 101.

It should be noted that, according to the above technical solution, the node finally determined by the consensus module 102 to perform the block writing is obtained after each node 101 achieves the consensus, that is, each node 101 recognizes the determined node to perform the block writing operation.

The node 101 in this application may be a server, including:

the processor may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more ics for controlling the execution of programs in accordance with the present disclosure.

A transceiver, which may be any device using any transceiver or the like, for communicating with other devices or communication networks, such as ethernet, Radio Access Network (RAN), Wireless Local Area Networks (WLAN), etc.

Memory, which may be, but is not limited to, read-only memory (ROM) or other type of static storage device that may store static information and instructions, Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disk, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be separate and coupled to the processor via a communication link. The memory may also be integral to the processor.

It should be noted that the embodiments of the present application may be referred to or referred to with respect to each other, for example, the same or similar steps, method embodiments, system embodiments, and apparatus embodiments may be referred to with respect to each other, without limitation.

Fig. 2 is a flowchart of a method for determining a consensus node according to an embodiment of the present disclosure. As shown in fig. 2, the method comprises the steps of:

step 201, the consensus module determines the first vertex array and the vertex parameters of the m vertices.

The first vertex array comprises m vertex identifiers, and the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights; m is a positive integer. The degree of a vertex refers to the number of paths connected to the vertex. The weight of a vertex is a path value that points to a path in the acyclic graph that points in the direction of the vertex. The block height is used to characterize the position of the block in the block chain. For example, the block height of the nth block is n-1.

In a possible implementation manner, the consensus module may randomly extract m blocks, and determine vertex parameters of m vertices according to block information of the m blocks.

Wherein, the m blocks correspond to the m vertexes included in the first vertex array one by one; the block information includes at least one of a block id and block writing node information. The chunk identity for each chunk is unique, typically represented by a hash value. The block write node information of a block is used to represent the identity information (i.e., accounting node) of the node writing the block.

Illustratively, the first vertex array is [ V ] ₁ ，V ₂ ，V ₃ ，……V _m ]. The vertex parameters include vertex degree, weight and block heightIn this case, the fixed point parameter of the ith vertex can be expressed as:

wherein, V _i Is the identity of the ith vertex, H _i Is the block height corresponding to the ith vertex, D _i Degree of the ith vertex, W _i Is the weight of the ith vertex.

In a possible implementation manner, the consensus module may further randomly sort the identifiers of the vertices in the first vertex array to obtain an updated first vertex array.

Illustratively, the first vertex array is [ V ] ₁ ，V ₂ ，V ₃ ，V ₄ ，V ₅ ，V ₆ ]. The consensus module randomly orders the identification of the top point in the first top point array to obtain the updated first top point array as V ₆ ，V ₁ ，V ₅ ，V ₄ ，V ₂ ，V ₃ ]。

Step 202, the consensus module sends the first vertex array to the a nodes. Correspondingly, the a nodes respectively receive the first vertex arrays sent by the consensus module.

Wherein a is a positive integer.

It should be noted that step 202 may be specifically implemented in the following manner:

step 2021, the consensus module sends the first vertex array to the 1 st node. Correspondingly, the 1 st node receives the first vertex array sent by the consensus module.

Step 2022, the consensus module sends the first vertex array to the 2 nd node. The 2 nd node receives the first vertex array sent by the consensus module.

……

Step 202a, the consensus module sends the first vertex array to the a-th node. The a-th node receives the first vertex array sent by the consensus module.

The a nodes may determine all nodes in the system for the consensus node, or may determine some nodes in the system for the consensus node.

In one possible implementation, before step 202, the consensus module sends status detection information to each node in the consensus node determination system. Correspondingly, each node in the consensus node determination system receives the state detection information sent by the consensus module and sends state response information to the consensus module.

And in a first preset time length T after the state detection information is sent, the consensus module takes the node corresponding to the received state response information as a node participating in consensus. At this time, the a nodes in step 202 are the nodes participating in consensus. Therefore, the consensus module can control the time consumed by executing the steps, can also eliminate the nodes with problems, and avoids the problem nodes from influencing the subsequent consensus operation. The first preset time period may be set according to actual conditions, which is not limited in this application.

And step 203, randomly ordering the identifiers of the m vertexes in the first vertex array by the a nodes respectively to generate a second vertex array.

The node is the node that receives the first vertex array sent by the consensus module in step 202. The second vertex array includes the identities of the m vertices.

It should be noted that each node randomly generates the second vertex array, and therefore, the generated second vertex arrays may be in the same order or in different orders. Meanwhile, the node only acquires the first vertex array at the moment, namely only the identification information of each vertex. Therefore, the node cannot determine which sort mode is beneficial to the node in advance, and fairness and justness of the consensus node determination method are guaranteed.

Illustratively, the first vertex array is [ V ] ₁ ，V ₂ ，V ₃ ，V ₄ ，V ₅ ，V ₆ ]. The node 1 randomly orders the identification of the top points in the first top point array to obtain a second top point array of V ₄ ，V ₂ ，V ₆ ，V ₁ ，V ₃ ，V ₅ ]。

And step 204, the a nodes send a second vertex array to the consensus module. Correspondingly, the consensus module receives the second vertex array sent by the a nodes.

The second vertex arrays are in one-to-one correspondence with the nodes, and one second vertex array is generated by the nodes corresponding to the second vertex array according to the random ordering of the first vertex array.

It should be noted that step 204 may be specifically implemented by the following steps:

step 2041, the 1 st node sends the second vertex array to the consensus module. Correspondingly, the consensus module receives the second vertex array sent by the 1 st node.

Step 2042, the 2 nd node sends the second vertex array to the consensus module. Correspondingly, the consensus module receives the second vertex array sent by the 2 nd node.

……

Step 204a, the a-th node sends a second vertex array to the consensus module. Correspondingly, the consensus module receives the second vertex array sent by the a-th node.

In a possible implementation manner, within a second preset time period after the consensus module sends the first vertex array to the node, the consensus module takes the node corresponding to the received second vertex array as the node participating in the consensus. Therefore, the consensus module can control the time consumed by executing the steps, and can also eliminate the nodes with problems, so that the problem nodes are prevented from influencing the subsequent consensus operation.

It should be noted that after the problem node is eliminated, the subsequent consensus operation is only performed on the nodes participating in the consensus. For convenience of understanding, the solution provided by the present application is described only in a scenario where no problem node exists, and the technical solution in the present application is also applicable to a scenario where a problem node exists.

Step 205, the consensus module sends the vertex parameters of the m vertices to the a nodes respectively. Correspondingly, the a nodes receive the vertex parameters of the m vertices sent by the consensus module.

The vertex parameters comprise at least one of the degree of the vertex, the weight of the vertex and the block height.

It should be noted that, the implementation manner in step 205 may refer to the relevant description in step 202, and is not described herein again.

And step 206, generating the directed acyclic graph by the a nodes according to the second vertex array and the vertex parameters of the m vertices.

In one possible implementation, the node performs a first target operation on each vertex in the second vertex array, and determines a connection relationship of each vertex.

Wherein, as shown in fig. 3, the first target operation includes:

step 2061, the node determines the in-degree and out-degree of the ith vertex.

The in-degree of a vertex refers to the number of paths in which the direction of a connection path points to the vertex. Out-degrees of vertices refer to the number of paths connecting the path directions to other vertices. The degree of the vertex is the sum of the out degree and the in degree of the vertex.

Illustratively, the directed acyclic graph further includes a start vertex and an end vertex for representing a start point and an end point of the directed acyclic graph. The starting vertex is connected with the 1 st vertex in the second vertex array, and the path direction of the connection points to the 1 st vertex. The mth vertex in the second vertex array is connected with the termination vertex, and the path direction of the connection points to the mth vertex. That is, the in-degree of the 1 st vertex may be 1, and the out-degree of the m-th vertex may be 1.

It should be noted that each vertex in the second vertex array includes at least one in degree and at least one out degree, thereby ensuring that at least one path exists between a start vertex and a stop vertex in the generated directed acyclic graph.

In a possible implementation manner, the node takes the number of paths in which the connection path direction points to the ith vertex as the in-degree of the ith vertex, and determines the out-degree of the ith vertex according to the in-degree of the ith vertex and the degree of the ith vertex. Wherein i is a positive integer less than or equal to m.

Illustratively, the out-degree of the ith vertex satisfies the following equation 1:

wherein D is _i Degree of the ith vertex, D _out-i Is the out degree of the ith vertex, D _in-i Is the in degree of the ith vertex.

Step 2062, the node determines the target number of the target vertexes according to the out-degree of the ith vertex, and sequentially executes a second target operation on each target vertex to determine the connection relation between the ith vertex and each target vertex until a second preset condition is met.

Wherein the target vertex is a vertex after the ith vertex. The second preset condition is that the number of the determined target vertexes connected with the ith vertex reaches the target number, or the second target operation has been performed on all vertexes after the ith vertex.

It should be noted that, in a case where the node has performed the second target operation on all vertices subsequent to the ith vertex, when the number of target vertices specified by the node and connected to the ith vertex does not reach the target number, the node takes the number of specified target vertices connected to the ith vertex as the out-degree of the ith vertex.

Wherein, as shown in fig. 4, the second target operation includes:

step 2063, the node determines the degree of the jth target vertex and the current in degree.

In a possible implementation manner, the node takes the number of paths in which the currently connected path direction points to the jth vertex as the current in-degree of the jth vertex.

Step 2064, under the condition that the degree of the jth target vertex and the current in-degree meet the third preset condition, the node determines that the ith vertex is connected with the jth target vertex.

Wherein the connected path direction points to the jth target vertex.

For example, the third preset condition may be the following formula 2:

D _in-j ≤D _j -1 equation 2

Wherein D is _in-j Is currently entered for the jth target vertexDegree D _j Is the degree of the jth target vertex.

In a possible implementation manner, the node may further use the vertex order of the second vertex array as an abscissa of each vertex, and use the vertex order of the first vertex array as an ordinate of each vertex, so as to generate the coordinate graph of the directed acyclic graph according to the abscissa and the ordinate of each vertex.

An example, the second vertex array is [ V ] ₄ ，V ₂ ，V ₆ ，V ₁ ，V ₃ ，V ₅ ]. Wherein the 1 st vertex V ₄ Degree of (2) is 3, 2 nd vertex V ₂ Degree of (3) is 4, the 3 rd vertex V ₆ Degree of (4) is 3, the 4 th vertex V ₁ Degree of (5) is 4, the 5 th vertex V ₃ Degree of (3) and the 6 th vertex V ₅ The degree of (d) is 3.

1. For the 1 st vertex V ₄ And the node determines that the in degree of the vertex is 1 and the out degree is 2.

Vertex V ₂ The degree of (1) is 4, the current degree of income is 0, and a third preset condition is met. Thus, the node determines the 1 st vertex V ₄ And vertex V ₂ And (4) connecting.

Vertex V ₆ The degree of (1) is 3, the current degree of income is 0, and a third preset condition is met. Thus, the node determines the 1 st vertex V ₄ And vertex V ₆ And (4) connecting.

And at the moment, a second preset condition is met, and the node determines the connection relation of the next vertex.

2. For the 2 nd vertex V ₂ The node determines that the in-degree of the vertex is 1 and the out-degree is 3.

Vertex V ₆ The degree of (1) is 3, the current degree of in is 1, and a third preset condition is met. Thus, the node determines the 2 nd vertex V ₂ And vertex V ₆ And (4) connecting.

Vertex V ₁ The degree of (1) is 4, the current degree of in is 0, and a third preset condition is met. Thus, the node determines the 2 nd vertex V ₂ And vertex V ₁ And (4) connecting.

Vertex V ₃ The degree of (1) is 3, the current degree of income is 0, and a third preset condition is met. Thus, the node determines the 2 ndVertex V ₂ And vertex V ₃ And (4) connecting.

3. For the 3 rd vertex V ₆ And the node determines that the in-degree of the vertex is 2 and the out-degree of the vertex is 1.

Vertex V ₁ The degree of (1) is 4, the current degree of income is 1, and a third preset condition is met. Thus, the node determines the 3 rd vertex V ₆ And vertex V ₁ And (4) connecting.

4. For the 4 th vertex V ₁ And the node determines that the in degree of the vertex is 2 and the out degree is 2.

Vertex V ₃ The degree of (1) is 3, the current degree of income is 1, and a third preset condition is met. Thus, the node determines the 4 th vertex V ₁ And vertex V ₃ And (4) connecting.

Vertex V ₅ The degree of (1) is 3, the current degree of income is 0, and a third preset condition is met. Thus, the node determines the 4 th vertex V ₁ And vertex V ₅ And (4) connecting.

5. For the 5 th vertex V ₃ And the node determines that the in-degree of the vertex is 2 and the out-degree of the vertex is 1.

Vertex V ₅ The degree of (1) is 3, the current degree of income is 1, and a third preset condition is met. Thus, the node determines the 5 th vertex V ₃ And vertex V ₅ And (4) connecting.

And when the second preset condition is met, the node determines the connection relation of the next vertex.

6. Vertex 6V ₅ The last vertex in the second vertex array is connected with the terminating vertex.

Thus, the nodes determine the connection relationship of each vertex.

As yet another example, the second vertex array is [ V ] ₄ ，V ₂ ，V ₆ ，V ₁ ，V ₃ ，V ₅ ]First, aThe vertex array is [ V ] ₆ ，V ₁ ，V ₅ ，V ₄ ，V ₂ ，V ₃ ]. The coordinates of each vertex are therefore: { V ₄ (1，4)，V ₂ (2，5)，V ₆ (3，1)，V ₁ (4，2)，V ₃ (5，6)，V ₅ (6,3)}. The graph of the generated directed acyclic graph is shown in fig. 5. Wherein, V _S As a starting vertex, V _E Is the terminating vertex.

And step 207, determining the shortest path by the a nodes according to the directed acyclic graph.

Wherein, the shortest path is the path with the smallest path value in at least one target path. The target path is a path from a starting vertex to an ending vertex in the directed acyclic graph.

In a possible implementation manner, the node takes the weight of the vertex as the path value of the path of which the connected path direction points to the vertex, and determines the shortest path of the directed acyclic graph through a preset algorithm.

Illustratively, the preset algorithm may be a shortest path search algorithm, such as a Depth First Search (DFS) algorithm, a Breadth First Search (BFS) algorithm, a Minimum Spanning Tree (MST) algorithm, or a Bellman-Ford (Bellman-Ford) algorithm. This is not a limitation of the present application.

And step 208, the a nodes send the shortest path to the consensus module. Correspondingly, the consensus module receives the shortest path sent by the a nodes.

Wherein, a shortest paths correspond to a nodes one by one. And one shortest path is determined by the node corresponding to the shortest path according to the directed acyclic graph. And a directed acyclic graph is generated by the target node according to the second vertex array corresponding to the target node and the vertex parameters of the m vertexes, and the target node is a node corresponding to the directed acyclic graph. The shortest path is used for the consensus module to determine a consensus node, and the consensus node is used for performing block writing.

It should be noted that, the implementation manner in step 208 may refer to the relevant description in step 204, and is not described herein again.

And step 209, the consensus module determines consensus nodes according to the a shortest paths.

The common node is used for performing block writing.

In a possible implementation manner, the consensus module determines a node with the smallest shortest path among the a nodes as the consensus node.

In yet another possible implementation manner, the consensus module may instruct the verification node to verify the data verification information of a nodes, and determine a node performing the block writing from the nodes passing the verification.

Wherein the data validation information includes at least one of a second vertex array, a directed acyclic graph, and a shortest path.

The scheme at least has the following beneficial effects: the consensus module determines a first vertex array and related vertex parameters required by generating the directed acyclic graph, indicates that vertices in the first vertex array determined by the a nodes are randomly sequenced, and sends the related vertex parameters to the a nodes after generating a second vertex array, so that the a nodes generate respective directed acyclic graphs according to the second vertex array and the vertex parameters respectively, and determine the shortest path of the directed acyclic graph. Since the vertex ordering of each node is random, the shortest path of each directed acyclic graph that is finally determined is also random. The consensus module takes the node corresponding to the directed acyclic graph with the minimum shortest path as the node for performing block writing, so that the nodes in the block chain can achieve consensus. Compared with a competitive consensus algorithm in the related art, the method for obtaining the nodes for executing block writing based on the shortest path of the directed acyclic graph does not need to consume excessive power and calculation resources. Compared with a negotiation type consensus algorithm in the related art, the technical scheme provided by the application only relates to concurrent communication between the consensus module and the node, the communication complexity is maintained at O (n), and the time required by consensus is greatly reduced. Therefore, the technical scheme effectively improves the consensus efficiency.

The following describes the process by which the consensus module determines the node to perform a block write.

As a possible embodiment of the present application, in conjunction with fig. 2, as shown in fig. 6, the above step 209 may also be implemented by the following steps 601 to 605.

Step 601, a nodes respectively send directed acyclic graphs to the consensus module. Correspondingly, the consensus module receives the directed acyclic graph sent by the a nodes.

Wherein, a directed acyclic graphs correspond to a nodes one by one.

It should be noted that, the implementation manner in step 601 may refer to the relevant description in step 204, and details are not described here.

Step 601 may be executed at any time after the node generates the directed acyclic graph in step 206 and before the consensus module in step 209 determines the node to execute the block writing, and fig. 6 is only one possible execution sequence, which is not limited in this application.

Step 602, the consensus module sends the first data verification information of the a nodes to the verification node. Correspondingly, the verification node receives the first data verification information of the a nodes sent by the consensus module.

Wherein the first data verification information includes at least one of a second vertex arrays, a directed acyclic graph, and a shortest paths. The verification node is one or more of the a nodes.

The first data verification information of the a nodes may be embodied as one verification message or a plurality of verification messages, which is not limited in this application.

When the verification node is a plurality of nodes among the a nodes, the implementation manner of step 602 may refer to the relevant description in step 202, and details are not described herein again.

It should be noted that the first data verification information sent by the consensus module does not include related information for identifying the node. Therefore, the verification node cannot determine the node corresponding to the data to be verified according to the first data verification information.

Step 603, the verification node verifies the first data verification information of the a nodes to obtain data verification results of the a nodes.

And the data verification result comprises data verification passing or data verification failing.

In a possible implementation manner, the verification node determines whether the corresponding directed acyclic graph is correct according to the second vertex array in the first data verification information; and/or determining whether the corresponding shortest path is correct according to the directed acyclic graph in the first data verification information.

Illustratively, the verification node determines the in-degree and the out-degree of each vertex in the second vertex array according to the second vertex array, and then calculates the degree of each vertex. The specific scheme can refer to the related scheme in step 206. And will not be described in detail herein.

As for the verification node, whether the directed acyclic graph generated by the a nodes is correct or not is verified, as can be seen from the related content in step 206, when the node has performed the second target operation on all vertices subsequent to the ith vertex, and the number of target vertices connected to the ith vertex determined by the node does not reach the target number, the node takes the determined number of target vertices connected to the ith vertex as the out-degree of the ith vertex. That is, in this case, the out-degree of the vertex actually determined becomes small.

Thus, in the event that the degree of each vertex computed by the validation node is less than or equal to the degree of the vertex determined by the consensus module, the validation node determines that the data is correct according to the directed acyclic graph.

In the event that the degree of each vertex computed by the validation node is greater than the degree of the vertex determined by the consensus module, the validation node determines that the data according to the directed acyclic graph is incorrect.

For the verification node to verify whether the shortest path determined by the a nodes is correct, the verification node may verify whether the path value of the shortest path is correct and/or verify whether the route of the shortest path is correct.

In one possible implementation, the verification node calculates the path value of the shortest path according to the directed acyclic graph of each node and the weight of the top point.

When the calculated shortest path value is the same as the shortest path value corresponding to the first data verification information, the verification node determines that the shortest path value data is correct.

On the contrary, when the calculated shortest path value is not the same as the corresponding shortest path value in the first data verification information, the verification node determines that the path value data of the shortest path is incorrect.

In yet another possible implementation, the verification node may further determine a route of the shortest path according to the directed acyclic graph of each node.

The specific scheme can refer to the related scheme in step 207. And will not be described in detail herein.

And under the condition that the route of the shortest path determined by the verification node is the same as the corresponding route of the shortest path in the first data verification information, the verification node determines that the route data of the shortest path is correct.

On the contrary, when the shortest route determined by the verification node is not the same as the corresponding shortest route in the first data verification information, the verification node determines that the shortest route data is incorrect.

It should be noted that, the data information that the verification node needs to verify may be set according to actual situations. And under the condition that the verification node verifies a plurality of items of data information and each item of data information is correct, the verification node determines that the data verification result is that the data verification is passed. And when the verification node verifies a plurality of items of data information and at least one item of data information is incorrect, the verification node determines that the data verification result is that the data verification is not passed.

And step 604, the verification node sends the data verification results of the a nodes to the consensus module. Correspondingly, the consensus module receives the data verification results of the a nodes sent by the verification node.

When the verification node is a plurality of nodes in the a nodes, the implementation manner of step 604 may refer to the related description in step 204, and is not described herein again.

Step 605, the consensus module determines a node satisfying a first preset condition among the a nodes as a consensus node.

Wherein, the first preset condition comprises: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

In a possible implementation manner, for any one of the a nodes, the consensus module determines that the data of the node in the a nodes passes the verification when the data verification result obtained by the node exceeding the preset proportion in the verification nodes is that the data passes the verification.

For example, the preset ratio may be a ratio greater than or equal to 50%, for example, two-thirds, specifically set according to the actual situation, and the present application is not limited thereto.

Through the technical scheme, the consensus module can take the related information of the shortest path of the directed acyclic graph calculated by the a nodes as the first data verification information and indicate one or more nodes in the block chain to verify, so that the data security problem of the block chain caused by the fact that the nodes in the a nodes tamper data is avoided.

As another possible embodiment of the present application, in conjunction with fig. 2, as shown in fig. 7, the above step 209 may also be implemented by the following steps 701 to 706.

And step 701, the a nodes respectively send the directed acyclic graph to the consensus module. Correspondingly, the consensus module receives the directed acyclic graph sent by the a nodes.

Wherein, a directed acyclic graphs correspond to a nodes one by one.

It should be noted that, the implementation manner in step 701 may refer to the relevant description in step 204, and is not described herein again.

Step 702, the consensus module removes the nodes with the shortest path value larger than a preset threshold value from the a nodes to obtain b nodes.

Wherein b is a positive integer less than or equal to a. The preset threshold may be a median of the shortest paths of the a nodes, an average of the shortest paths of the a nodes, or may be set according to actual conditions. This is not a limitation of the present application.

It should be noted that, by excluding one or more nodes with a larger shortest path among the a nodes, the verification calculation amount in the subsequent operation can be reduced, and further, the resource overhead of the consensus node determination method provided by the present application is reduced.

And step 703, the consensus module sends the second data verification information of the b nodes to the verification node. Correspondingly, the verification node receives the second data verification information of the b nodes sent by the consensus module.

Wherein the second data verification information comprises at least one of b second vertex arrays, b directed acyclic graphs, and b shortest paths. The verification node is one or more of the a nodes.

For related contents, reference may be made to the description in step 602 above, and details are not repeated here.

Step 704, the verification node verifies the second data verification information of the b nodes to obtain the data verification result of the b nodes.

For related content, reference may be made to the description in step 603, and details are not repeated here.

Step 705, the verification node sends the data verification results of the b nodes to the consensus module. Correspondingly, the consensus module receives the data verification results of the b nodes sent by the verification node.

When the verification node is a plurality of nodes in the a nodes, the implementation manner of step 705 may refer to the related description in step 204, and is not described herein again.

Step 706, the consensus module determines that the node meeting the first preset condition among the b nodes is a consensus node.

For related content, reference may be made to the description in step 605, which is not repeated herein.

Through the technical scheme, the consensus module excludes one or more nodes with overlarge shortest paths from the a nodes, then uses the related information of the shortest paths of the directed acyclic graph calculated by the remaining nodes as second data verification information, and indicates one or more nodes in the block chain to perform verification, so that the resource overhead in the verification process is reduced, and the consensus efficiency is further improved.

The following describes the process of the consensus module determining the vertex parameters of the first vertex array and the m vertices.

As a possible embodiment of the present application, in conjunction with fig. 2, as shown in fig. 8, the above step 201 can also be implemented by the following steps 801 to 803.

Step 801, the consensus module randomly extracts m blocks.

Wherein, the m blocks correspond to the m vertexes included in the first vertex array one by one; the block information includes at least one of a block id and block writing node information. The m blocks correspond to the m vertices one to one.

It should be noted that the consensus module randomly extracts m blocks from the block chain, which may be extraction with replacement or extraction without replacement. The extraction with replacement means that after the consensus module randomly extracts a block from the block chain, the block is extracted from the original block chain again. Therefore, the extracted blocks may be the same or different blocks. The extraction without replacement means that after the consensus module randomly extracts one block from the block chain, the consensus module extracts the block from the blocks of the block chain except the block. The extracted blocks are therefore different blocks.

Illustratively, the current blockchain includes n blocks, where n is a positive integer. Consensus modules from [1, n]Randomly generating a value m, and optionally selecting m blocks from the n blocks. Wherein, m blocks correspond to m vertexes one by one. The consensus module marks the identifiers of the vertexes corresponding to the selected blocks as V in sequence according to the selection sequence ₁ ，V ₂ ，V ₃ ，……V _m 。

By controlling the number of the extracted blocks, the consensus module can also indirectly control the time consumed by consensus, and the consensus efficiency is guaranteed.

Step 802, the consensus module determines the weight of the top point according to the block identifier.

In one possible implementation, the consensus module generates a random number c, and determines the weight of the vertex corresponding to the block according to the random number c and the block identifier.

Illustratively, the chunk identifier may be a hexadecimal hash value, and c is a random number generated in the range of [1, 15 ]. And for each block, converting each digit of the block identifier into a decimal number by the consensus module, and determining the corresponding sub-weight of each digit according to the c and the block identifier. Wherein the sub-weights satisfy the following formula 3:

wherein, W _i Identifying the sub-weights of the ith bit for a block, hash _i The value of the ith bit is identified for the block.

The consensus module takes the sum of the sub-weights of each bit of the block as the weight of the corresponding top point of the block. The weight of the top point may be positive, negative, or zero.

In yet another possible implementation manner, the consensus module may further send random number generation indication information to each node in the block chain, where the random number generation indication information is used to indicate that the node randomly generates one random number c _i . The consensus module is based on the received random number c _i And determining the weight of the top point corresponding to the block according to the block identification.

Illustratively, the consensus module may match the received random number c _i The average value of c is used as the random number c, so as to determine the weight of the top point.

It should be noted that, by means of the scheme, the vertex weight may be determined based on the random number information generated by each node in the block chain, so that the scheme is more random. Meanwhile, the consensus module can also determine the state of the node in the block chain according to the condition of receiving the information. For example, the consensus module takes the node corresponding to the received information within the third preset time after the random number generation indication information is sent as the node participating in the consensus. Therefore, the consensus module can control the time consumed by executing the steps, and can also eliminate the nodes with problems, so that the problem nodes are prevented from influencing the subsequent consensus operation.

Step 803, the consensus module determines the degree of the vertex according to the block write node information.

In one possible implementation manner, the consensus module determines the occurrence number of the nodes in the block writing node information of each block in the block writing node information of m blocks, and determines the degree of the vertex corresponding to the block according to the occurrence number.

Illustratively, the degree of the ith vertex satisfies the following equation 4:

D _i ＝d _i +2 formula 4

Wherein D is _i Degree of the ith vertex, d _i The number of occurrences of the node in the block write node information for the ith block in the block write node information for the m blocks.

Based on the above technical solution, in the present application, the consensus module may randomly extract a plurality of blocks from the block chain, and determine vertex parameters such as the weight and the degree of the vertex according to the block information of the plurality of blocks. The blocks extracted by the consensus module are random, and the vertex parameters determined based on the block information are also random, so that the technical scheme of the application can ensure the randomness and the fairness of the consensus module in the process of determining the first vertex array and the vertex parameters of the m vertexes.

In the embodiment of the present application, the common identification module and the node apparatus may be divided into the functional modules or the functional units according to the above method examples, for example, each functional module or functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module may be implemented in a form of hardware, or may be implemented in a form of a software functional module or a functional unit. The division of the modules or units in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

As shown in fig. 9, a schematic structural diagram of an apparatus 90 for determining a consensus node according to an embodiment of the present application is provided, where the apparatus includes:

a processing unit 901, configured to determine a first vertex array and vertex parameters of m vertices; the first vertex array comprises m vertex identifiers, and the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights; m is a positive integer.

A communication unit 902, configured to send a first vertex array to a nodes; a is a positive integer.

A communication unit 902, further configured to receive a second vertex arrays; the a second vertex arrays correspond to the a nodes one by one; a second vertex array is generated by randomly ordering nodes corresponding to the second vertex array according to the first vertex array.

The communication unit 902 is further configured to send vertex parameters of the m vertices to the a nodes.

A communication unit 902, further configured to receive a shortest paths; a shortest paths correspond to a nodes one by one; a shortest path is determined by a node corresponding to the shortest path according to the directed acyclic graph; a directed acyclic graph is generated by the target node according to the second vertex array corresponding to the target node and the vertex parameters of the m vertexes; the target node is a node corresponding to the directed acyclic graph.

The processing unit 901 is further configured to determine a consensus node according to the a shortest paths, where the consensus node is used to perform block writing.

In a possible implementation manner, the processing unit 901 is further configured to determine a node with the smallest shortest path among the a nodes as a consensus node.

In a possible implementation manner, the communication unit 902 is further configured to receive a directed acyclic graph; a directed acyclic graph corresponds to a nodes one by one; a communication unit 902, further configured to send first data authentication information of a nodes to an authentication node; the first data verification information comprises at least one of a second vertex arrays, a directed acyclic graphs and a shortest paths; verifying that the node is one or more nodes in a nodes; a communication unit 902, further configured to receive data verification results of a nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing; the processing unit 901 is further configured to determine, as a consensus node, a node that meets a first preset condition among the a nodes; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

In a possible implementation manner, the communication unit 902 is further configured to receive a directed acyclic graph; a directed acyclic graph corresponds to a nodes one by one; the processing unit 901 is further configured to remove a node, of which the numerical value of the shortest path is greater than a preset threshold, from the a nodes to obtain b nodes; b is a positive integer less than or equal to a; a communication unit 902, further configured to send second data authentication information of the b nodes to the authentication node; the second data verification information comprises at least one of b second vertex arrays, b directed acyclic graphs and b shortest paths; verifying that the node is one or more nodes in a nodes; a communication unit 902, further configured to receive data verification results of b nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing; the processing unit 901 is further configured to determine a node, which meets a first preset condition, of the b nodes as a consensus node; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

In a possible implementation manner, the processing unit 901 is further configured to randomly extract m blocks; the m blocks correspond to m vertexes included in the first vertex array one by one; determining vertex parameters of m vertexes according to the block information of the m blocks; the block information includes at least one of a block id and block writing node information.

In a possible implementation manner, the processing unit 901 is further configured to, in a case that the block information includes a block identifier, determine a weight of the vertex according to the block identifier; in the case where the block information includes block writing node information, the degree of the vertex is determined according to the block writing node information.

a communication unit 902, configured to receive a first vertex array sent by a consensus module; the first vertex array comprises identifications of m vertexes; m is a positive integer.

The processing unit 901 is configured to randomly sort the identifiers of the m vertices in the first vertex array, and generate a second vertex array.

The communication unit 902 is further configured to send the second vertex array to the consensus module.

A communication unit 902, further configured to receive vertex parameters of the m vertices sent by the consensus module; the vertex parameters include at least one of degree of vertex, weight of vertex, and block height.

The processing unit 901 is further configured to generate a directed acyclic graph according to the second vertex array and the vertex parameters of the m vertices.

The processing unit 901 is further configured to determine a shortest path according to the directed acyclic graph; the shortest path is used for the consensus module to determine a consensus node, and the consensus node is used for performing block writing.

The communication unit 902 is further configured to send the shortest path to the consensus module.

In a possible implementation manner, the communication unit 902 is further configured to send a directed acyclic graph to the consensus module; the processing unit 901 is further configured to verify the first data verification information to obtain data verification results of a nodes, when the first data verification information of a nodes sent by the consensus module is received; the first data verification information comprises at least one of a second vertex arrays, a directed acyclic graphs and a shortest paths; the data verification result comprises data verification passing or data verification failing; a is a positive integer; the communication unit 902 is further configured to send the data verification results of the a nodes to the consensus module.

In a possible implementation manner, the communication unit 902 is further configured to send a directed acyclic graph to the consensus module; the processing unit 901 is further configured to verify the second data verification information to obtain data verification results of the b nodes when the second data verification information of the b nodes sent by the consensus module is received; the second data verification information comprises at least one of b second vertex arrays, b directed acyclic graphs and b shortest paths; the data verification result comprises data verification passing or data verification failing; the communication unit 902 is further configured to send the data verification results of the b nodes to the consensus module.

In a possible implementation manner, the processing unit 901 is further configured to determine whether the corresponding directed acyclic graph is correct according to a second vertex array in the target data verification information; and/or determining whether the corresponding shortest path is correct according to the directed acyclic graph in the target data verification information; the target data verification information is first data verification information or second data verification information.

When implemented by hardware, the communication unit 902 in the embodiment of the present application may be integrated on a communication interface, and the processing unit 901 may be integrated on a processor. The specific implementation is shown in fig. 10.

Fig. 10 shows a schematic structural diagram of still another possible consensus node determining apparatus involved in the above embodiments. The consensus node determining apparatus 100 includes: a processor 1002, and a communication interface 1003. The processor 1002 is configured to control and manage actions of the consensus node determination apparatus 100, for example, to perform the steps performed by the processing unit 901 described above, and/or to perform other processes for the techniques described herein. The communication interface 1003 is used for supporting the communication between the consensus node determining apparatus 100 and other network entities, for example, performing the steps performed by the communication unit 902 described above. The consensus node determining apparatus 100 may further include a memory 1001 and a bus 1004, the memory 1001 being used for storing program codes and data of the consensus node determining apparatus 100.

The memory 1001 may be a memory in the common node determining apparatus 100, and the memory may include a volatile memory, such as a random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, a hard disk, or a solid state disk; the memory may also comprise a combination of memories of the kind described above.

The processor 1002 may be any means that can implement or execute the various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein. The processor may be a central processing unit, general purpose processor, digital signal processor, application specific integrated circuit, field programmable gate array or other programmable logic device, transistor logic device, hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others.

The bus 1004 may be an Extended Industry Standard Architecture (EISA) bus or the like. The bus 1004 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 10, but this is not intended to represent only one bus or type of bus.

The network access device in fig. 10 may also be a chip. The chip includes one or more (including two) processors 1002 and a communication interface 1003.

In some embodiments, the chip also includes a memory 1001, and memory 1001 may include both read-only memory and random access memory and provide operating instructions and data to processor 1002. A portion of memory 1001 may also include non-volatile random access memory (NVRAM).

In some embodiments, memory 1001 stores elements, execution modules or data structures, or a subset thereof, or an expanded set thereof.

In the embodiment of the present application, by calling an operation instruction stored in the memory 1001 (the operation instruction may be stored in an operating system), a corresponding operation is performed.

The processor 1002 may implement or execute the various illustrative logical blocks, units, and circuits described in connection with the disclosure herein. The processor may be a central processing unit, general purpose processor, digital signal processor, application specific integrated circuit, field programmable gate array or other programmable logic device, transistor logic device, hardware component, or any combination thereof. Which may implement or perform the various illustrative logical blocks, units, and circuits described in connection with the disclosure. The processor may also be a combination of computing functions, e.g., comprising one or more microprocessors, DSPs, and microprocessors, among others.

Memory 1001 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, a hard disk, or a solid state disk; the memory may also comprise a combination of memories of the kind described above.

The bus 1004 may be an Extended Industry Standard Architecture (EISA) bus or the like. The bus 1004 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in FIG. 10, but it is not intended that there be only one bus or one type of bus.

Through the above description of the embodiments, it is clear to those skilled in the art that, for convenience and simplicity of description, the foregoing division of the functional modules is merely used as an example, and in practical applications, the above function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions. For the specific working processes of the system, the apparatus and the unit described above, reference may be made to the corresponding processes in the foregoing method embodiments, and details are not described here again.

The present application provides a computer program product containing instructions, which when run on a computer, causes the computer to execute the consensus node determination method in the above method embodiments.

The embodiment of the present application further provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the instructions are run on a computer, the computer is enabled to execute the method for determining the consensus node in the method flow shown in the foregoing method embodiment.

The computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a Read-Only Memory (ROM), an Erasable Programmable Read-Only Memory (EPROM), a register, a hard disk, an optical fiber, a portable Compact Disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, any suitable combination of the above, or any other form of computer readable storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuit (ASIC). In embodiments of the present application, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

Since the consensus node determining apparatus, the computer-readable storage medium, and the computer program product in the embodiments of the present invention may be applied to the method described above, the technical effect obtained by the method may also refer to the method embodiments described above, and the details of the embodiments of the present invention are not repeated herein.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above is only an embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for determining a consensus node, the method comprising:

determining a first vertex array and vertex parameters of m vertexes; wherein the first vertex array comprises the identifiers of the m vertices, and the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights; m is a positive integer;

sending the first vertex array to a nodes; a is a positive integer;

receiving a second vertex arrays; the a second vertex arrays correspond to the a nodes one by one; a second vertex array is generated by nodes corresponding to the second vertex array according to the random ordering of the first vertex array;

sending vertex parameters of the m vertices to the a nodes;

receiving a shortest paths; the a shortest paths correspond to the a nodes one by one; one shortest path is determined by the node corresponding to the shortest path according to the directed acyclic graph; a directed acyclic graph is generated by a target node according to a second vertex array corresponding to the target node and the vertex parameters of the m vertexes; the target node is a node corresponding to the directed acyclic graph;

and determining a consensus node according to the a shortest paths, wherein the consensus node is used for performing block writing.

2. The method of claim 1, wherein the determining a consensus node based on the a shortest paths comprises:

and determining the node with the minimum shortest path in the a nodes as the consensus node.

3. The method of claim 1, wherein the determining a consensus node based on the a shortest paths comprises:

receiving a directed acyclic graphs; the a directed acyclic graphs correspond to the a nodes one by one;

sending first data verification information of the a nodes to a verification node; the first data validation information comprises at least one of the a second vertex arrays, the a directed acyclic graphs, and the a shortest paths; the verification node is one or more nodes in the a nodes;

receiving the data verification results of the a nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing;

determining a node meeting a first preset condition in the a nodes as the consensus node; the first preset condition comprises the following steps: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

4. The method of claim 1, wherein the determining a consensus node based on the a shortest paths comprises:

removing nodes of which the numerical value of the shortest path is greater than a preset threshold value from the a nodes to obtain b nodes; b is a positive integer less than or equal to a;

sending second data verification information of the b nodes to a verification node; the second data validation information comprises at least one of b second vertex arrays, b directed acyclic graphs, and b shortest paths; the verification node is one or more nodes in the a nodes;

receiving data verification results of the b nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing;

determining a node meeting a first preset condition in the b nodes as the consensus node; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

5. The method of any of claims 1-4, wherein determining vertex parameters for the first array of vertices and the m vertices comprises:

randomly extracting m blocks; the m blocks correspond to the m vertexes included in the first vertex array one by one;

determining vertex parameters of the m vertexes according to the block information of the m blocks; the block information includes at least one of block identification and block writing node information.

6. The method of claim 5, wherein the determining the vertex parameters of the m vertices according to the block information of the m blocks comprises:

determining the weight of the vertex according to the block identifier under the condition that the block information comprises the block identifier;

determining the degree of the vertex according to the block writing node information in a case where the block information includes the block writing node information.

7. A method for determining a consensus node, the method comprising:

receiving a first vertex array sent by a consensus module; the first vertex array comprises identifications of m vertexes; m is a positive integer;

randomly ordering the identifiers of the m vertexes in the first vertex array to generate a second vertex array;

sending the second vertex array to the consensus module;

receiving the vertex parameters of the m vertexes sent by the consensus module; the vertex parameters comprise at least one of vertex degree, vertex weight and block height;

generating a directed acyclic graph according to the second vertex array and the vertex parameters of the m vertexes;

determining a shortest path according to the directed acyclic graph, and sending the shortest path to the consensus module; the shortest path is used for a consensus module to determine a consensus node, which is used to perform a block write.

8. The method of claim 7, further comprising:

sending the directed acyclic graph to the consensus module;

under the condition of receiving first data verification information of a nodes sent by a consensus module, verifying the first data verification information to obtain data verification results of the a nodes; the first data validation information comprises at least one of a second vertex arrays, a directed acyclic graphs, and a shortest paths; the data verification result comprises data verification passing or data verification failing; a is a positive integer;

and sending the data verification results of the a nodes to the consensus module.

9. The method of claim 7, further comprising:

sending the directed acyclic graph to the consensus module;

under the condition of receiving second data verification information of b nodes sent by the consensus module, verifying the second data verification information to obtain data verification results of the b nodes; the second data validation information comprises at least one of b second vertex arrays, b directed acyclic graphs, and b shortest paths; the data verification result comprises data verification passing or data verification failing;

and sending the data verification results of the b nodes to the consensus module.

10. The method according to claim 8 or 9, characterized in that the method further comprises:

determining whether the corresponding directed acyclic graph is correct or not according to a second vertex array in the target data verification information; and/or

Determining whether the corresponding shortest path is correct or not according to the directed acyclic graph in the target data verification information;

the target data verification information is first data verification information or second data verification information.

11. An consensus node determination apparatus comprising a communication unit and a processing unit;

the processing unit is used for determining a first vertex array and vertex parameters of m vertexes; wherein the first vertex array comprises the identifiers of the m vertices, and the vertex parameters comprise at least one of vertex degrees, vertex weights and block heights; m is a positive integer;

the communication unit is used for sending the first vertex array to a nodes; a is a positive integer;

the communication unit is further used for receiving a second vertex arrays; the a second vertex arrays correspond to the a nodes one by one; a second vertex array is generated by nodes corresponding to the second vertex array according to the random ordering of the first vertex array;

the communication unit is further configured to send vertex parameters of the m vertices to the a nodes;

the communication unit is also used for receiving a shortest paths; the a shortest paths correspond to the a nodes one by one; one shortest path is determined by the node corresponding to the shortest path according to the directed acyclic graph; a directed acyclic graph is generated by a target node according to a second vertex array corresponding to the target node and the vertex parameters of the m vertexes; the target node is a node corresponding to the directed acyclic graph;

the processing unit is further configured to determine a consensus node according to the a shortest paths, where the consensus node is used to perform block writing.

12. The apparatus of claim 11, wherein the processing unit is further configured to determine a node of the a nodes with the smallest shortest path as the consensus node.

13. The apparatus of claim 11, wherein the communication unit is further configured to receive a directed acyclic graph; the a directed acyclic graphs correspond to the a nodes one by one;

the communication unit is further used for sending the first data verification information of the a nodes to a verification node; the first data validation information comprises at least one of the a second vertex arrays, the a directed acyclic graphs, and the a shortest paths; the verification node is one or more nodes in the a nodes;

the communication unit is further configured to receive the data verification result of the a nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing;

the processing unit is further configured to determine, as the consensus node, a node that satisfies a first preset condition among the a nodes; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

14. The apparatus of claim 11, wherein the communication unit is further configured to receive a directed acyclic graph; the a directed acyclic graphs correspond to the a nodes one by one;

the processing unit is further configured to remove a node, of which a shortest path value is greater than a preset threshold, from the a nodes to obtain b nodes; b is a positive integer less than or equal to a;

the communication unit is further configured to send second data verification information of the b nodes to a verification node; the second data validation information comprises at least one of b second vertex arrays, b directed acyclic graphs, and b shortest paths; the verification node is one or more nodes in the a nodes;

the communication unit is further configured to receive data verification results of the b nodes sent by the verification node; the data verification result comprises data verification passing or data verification failing;

the processing unit is further configured to determine, as the consensus node, a node that satisfies a first preset condition among the b nodes; the first preset condition includes: and the data verification result is that the data passes the verification, and the shortest path is the minimum.

15. The apparatus according to any of claims 11-14, wherein the processing unit is configured to:

16. The apparatus of claim 15, wherein the processing unit is configured to:

17. An consensus node determination apparatus comprising a communication unit and a processing unit;

the communication unit is used for receiving the first vertex array sent by the consensus module; the first vertex array comprises identifications of m vertices; m is a positive integer;

the processing unit is used for randomly sequencing the identifiers of the m vertexes in the first vertex array to generate a second vertex array;

the communication unit is further configured to send the second vertex array to the consensus module;

the communication unit is further configured to receive the vertex parameters of the m vertices sent by the consensus module; the vertex parameters comprise at least one of vertex degree, vertex weight and block height;

the processing unit is further configured to generate a directed acyclic graph according to the second vertex array and the vertex parameters of the m vertices;

the processing unit is further configured to determine a shortest path according to the directed acyclic graph; the shortest path is used for a consensus module to determine a consensus node, and the consensus node is used for performing block writing;

the communication unit is further configured to send the shortest path to the consensus module.

18. The apparatus of claim 17, wherein the communication unit is further configured to send the directed acyclic graph to the consensus module;

the processing unit is further configured to verify first data verification information of a nodes sent by the consensus module to obtain data verification results of the a nodes when the first data verification information of the a nodes is received; the first data validation information comprises at least one of a second vertex arrays, a directed acyclic graphs, and a shortest paths; the data verification result comprises data verification passing or data verification failing; a is a positive integer;

the communication unit is further configured to send the data verification result of the a nodes to the consensus module.

19. The apparatus of claim 17, wherein the communication unit is further configured to send the directed acyclic graph to the consensus module;

the processing unit is further configured to verify second data verification information of the b nodes sent by the consensus module under the condition that the second data verification information is received, so as to obtain data verification results of the b nodes; the second data validation information comprises at least one of b second vertex arrays, b directed acyclic graphs, and b shortest paths; the data verification result comprises data verification passing or data verification failing;

the communication unit is further configured to send the data verification results of the b nodes to the consensus module.

20. The apparatus according to claim 18 or 19, wherein the processing unit is configured to:

21. An apparatus for determining a consensus node, comprising: a processor and a communication interface; the communication interface is coupled to the processor for executing a computer program or instructions for implementing the consensus node determination method as claimed in any of claims 1-6 or for implementing the consensus node determination method as claimed in any of claims 7-10.

22. A computer-readable storage medium, wherein instructions are stored therein, and when executed by a computer, the computer performs the consensus node determination method of any one of claims 1-6 above, or performs the consensus node determination method of any one of claims 7-10 above.