CN114978403B - Method and device for measuring clock holding phase deviation value - Google Patents
Method and device for measuring clock holding phase deviation value Download PDFInfo
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- CN114978403B CN114978403B CN202210902107.XA CN202210902107A CN114978403B CN 114978403 B CN114978403 B CN 114978403B CN 202210902107 A CN202210902107 A CN 202210902107A CN 114978403 B CN114978403 B CN 114978403B
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
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Abstract
The invention provides a method and a device for measuring a clock holding phase deviation value, wherein the method comprises the following steps: acquiring a first frequency locking curve of a clock system before a T1 moment and determining a first frequency compensation curve; obtaining a second frequency locking curve of the clock system between the time T1 and the time T1+ T2; determining a first frequency deviation value accumulation from the time T1 to the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve; obtaining a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M; acquiring a fourth frequency locking curve of the clock system before the time T1+ M, and determining a second frequency compensation curve; determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment according to the third frequency locking curve and the second frequency compensation curve; determining a clock holding phase deviation value range from the time T1-M to the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation; the invention can shorten the measuring time and improve the measuring efficiency.
Description
Technical Field
The invention relates to the technical field of data measurement, in particular to a method and a device for measuring a clock holding phase deviation value.
Background
At present, in a clock timekeeping and time service system, a local source is required to track a GPS for a period of time to achieve clock frequency synchronization so as to tame the local source, and when a GPS signal is lost, the local source can maintain the stability of the clock system according to the tamed holding frequency.
Because the frequencies of the clock systems entering the hold at different time points are different, in order to measure the accuracy of the hold frequency, in the prior art, each time point entering the hold needs to be measured respectively to obtain the hold frequency, and then the hold frequency is converted into a phase to be judged, for example, in order to measure the hold results of the clock system after being locked for 24 hours after being locked for 7 days and for 24 hours after being locked for 1 hour after being locked for 7 days, the hold phase offset value of 24 hours after being locked for 7 days and the hold phase offset value of 24 hours after being locked for 1 hour after being locked for 7 days need to be measured respectively, which further results in longer test time and lower efficiency.
The above is only for the purpose of assisting understanding of the technical aspects of the present invention, and does not represent an admission that the above is prior art.
Disclosure of Invention
The invention mainly aims to provide a method and a device for measuring a clock holding phase deviation value, and aims to solve the technical problems of long time for holding a result and low efficiency of a clock system test in the prior art.
In order to achieve the above object, the present invention provides a method for measuring a clock holding phase offset value, the method comprising the steps of:
acquiring a first frequency locking curve of a clock system before a T1 moment, and determining a first frequency compensation curve according to the first frequency locking curve;
continuing to lock the clock system for the duration of T2, and obtaining a second frequency locking curve of the clock system between the time T1 and the time T1+ T2;
determining a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve;
continuing to lock the clock system for M duration to obtain a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M;
acquiring a fourth frequency locking curve of the clock system before the T1+ M moment, and determining a second frequency compensation curve according to the fourth frequency locking curve;
determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment according to the third frequency locking curve and the second frequency compensation curve;
and determining a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation.
Optionally, the step of determining a clock holding phase offset value range of the clock system between time T1-M to time T1+ M according to the first frequency offset value accumulation and the second frequency offset value accumulation includes:
determining a first clock holding phase deviation value range of the clock system between the time T1 and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation;
determining a second range of clock maintenance phase offset values for the clock system between time T1-M to time T1 based on the first range of clock maintenance phase offset values;
and integrating the first clock holding phase deviation value range and the second clock holding phase deviation value range, and taking the integration result as the clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M.
Optionally, before the step of determining a second clock holding phase offset value range of the clock system between time T1-M to time T1 based on the first clock holding phase offset value range, the method further comprises:
acquiring an adjusting time interval of the digital-to-analog converter;
cumulatively determining a range of frequency-phase offset values per unit time based on the adjustment time interval and the second frequency offset value at the time T1+ M;
accordingly, the step of determining a second range of clock hold phase offset values for the clock system between times T1-M to time T1 based on the first range of clock hold phase offset values comprises:
determining a second clock holding phase offset value range of the clock system between time T1-M to time T1 based on the unit time frequency phase offset value range.
Optionally, after the step of determining a clock holding phase offset value range of the clock system between the time T1-M to the time T1+ M according to the first frequency offset value accumulation and the second frequency offset value accumulation, the method further includes:
continuing to keep the time length of T2 for the clock system, and obtaining a phase deviation value of the clock system at the moment of T1+ T2+ M + T2;
judging whether the phase deviation value of the time T1+ T2+ M + T2 is in a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M;
if yes, the product is judged to meet the preset standard.
Optionally, the step of acquiring a first frequency locking curve of the clock system before the time T1 and determining a first frequency compensation curve according to the first frequency locking curve includes:
acquiring a first frequency locking curve of a clock system before a T1 moment;
a first frequency compensation curve is obtained from the first frequency lock curve based on a compensation hold algorithm.
Optionally, the step of determining a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve comprises:
determining a first frequency deviation value accumulation between the T1 moment and the T1+ T2 moment through a first preset formula based on the second frequency locking curve and the first frequency compensation curve;
wherein the first preset formula is as follows:
wherein T1 is the time T1, H T1 Accumulating for the first frequency deviation value, DAC2 for the second frequency lock curve, and DAC1' for the first frequency deviation valueA first frequency compensation curve.
Optionally, the step of determining a second frequency deviation value accumulation from the time T1+ M to the time T1+ T2+ M according to the third frequency locking curve and the second frequency compensation curve includes;
determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment through a second preset formula according to the third frequency locking curve and the second frequency compensation curve;
wherein the second preset formula is as follows:
wherein T1+ M is the time of T1+ M, H T1+M And accumulating the second frequency deviation value, wherein the DAC3 is the third frequency locking curve, and the DAC3' is the second frequency compensation curve.
Further, in order to achieve the above object, the present invention provides a clock holding phase offset value measuring device, including:
the first frequency compensation curve acquisition module is used for acquiring a first frequency locking curve of a clock system before the time T1 and determining a first frequency compensation curve according to the first frequency locking curve;
a second frequency locking curve obtaining module, configured to continue to lock the clock system for the duration of T2, and obtain a second frequency locking curve of the clock system between the time T1 and the time T1+ T2;
a first frequency deviation value accumulation determining module, configured to determine a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve;
the third frequency locking curve acquisition module is used for continuously locking the clock system for M time length to acquire a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M;
a second frequency compensation curve determining module, configured to acquire a fourth frequency locking curve of the clock system before the time T1+ M, and determine a second frequency compensation curve according to the fourth frequency locking curve;
a second frequency deviation value accumulation determining module, configured to determine, according to the third frequency locking curve and the second frequency compensation curve, a second frequency deviation value accumulation from the time T1+ M to the time T1+ T2+ M;
and the phase deviation value range determining module is used for determining a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation.
Optionally, the phase offset value range determining module is further configured to determine, according to the first frequency offset value accumulation and the second frequency offset value accumulation, a range of a phase offset value to be maintained by the clock system at a first clock between the time T1 and the time T1+ M; determining a second range of clock hold phase offset values for the clock system between time T1-M to the time T1 based on the first range of clock hold phase offset values; and integrating the first clock holding phase deviation value range and the second clock holding phase deviation value range, and taking the integration result as the clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M.
Optionally, the phase offset value range determining module is further configured to obtain an adjustment time interval of the digital-to-analog converter; cumulatively determining a range of frequency-to-phase offset values per unit time based on the adjustment time interval and the second frequency deviation value at the time T1+ M; determining a second clock holding phase offset value range of the clock system between time T1-M to time T1 based on the unit time frequency phase offset value range.
The method comprises the steps of obtaining a first frequency locking curve of a clock system before the T1 moment, and determining a first frequency compensation curve according to the first frequency locking curve; continuing to lock the clock system for the duration of T2, and obtaining a second frequency locking curve of the clock system between the time T1 and the time T1+ T2; determining a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve; continuing to lock the clock system for M duration to obtain a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M; acquiring a fourth frequency locking curve of the clock system before the T1+ M moment, and determining a second frequency compensation curve according to the fourth frequency locking curve; determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment according to the third frequency locking curve and the second frequency compensation curve; determining a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation; compared with the prior art that when a user needs to obtain frequency holding values corresponding to each time point in a target time period, the phase deviation value corresponding to each time point needs to be obtained based on the T1 duration, namely, the clock system needs to pass through the first T1 duration in each measurement, the phase deviation value corresponding to each time point in a time period can be obtained only through one T1 duration, the measurement time can be shortened, and the measurement efficiency is improved.
Drawings
Fig. 1 is a schematic flowchart of a clock holding phase offset value measuring method according to a first embodiment of the present invention;
FIG. 2 is a frequency chart of a clock system according to a method for measuring a clock holding phase offset value according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a clock hold phase offset measurement method according to a second embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for measuring a clock holding phase offset value according to a third embodiment of the present invention;
fig. 5 is a block diagram of a clock holding phase offset value measuring apparatus according to a first embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for measuring a clock holding phase offset value according to a first embodiment of the method for measuring a clock holding phase offset value according to an embodiment of the present invention.
In this embodiment, the method for measuring the clock holding phase offset value includes the following steps:
step S10: acquiring a first frequency locking curve of a clock system before a T1 moment, and determining a first frequency compensation curve according to the first frequency locking curve;
it should be noted that the method of this embodiment may be applied in a scenario where a holding frequency in a clock system is measured, or in other scenarios where a frequency needs to be measured. The implementation subject of the embodiment may be a clock-keeping phase offset value measuring device with data processing, network communication and program running functions, such as a computer, or other devices capable of implementing the same or similar functions. The present embodiment and the following embodiments are specifically described with the above-described clock holding phase offset value measuring device (hereinafter simply referred to as a device).
It can be understood that the clock system may have two states, that is, when the clock system receives a GPS signal, it is to enter a locking state, and when the GPS signal is lost, it is to enter a holding state, and when the GPS signal is lost, it is to enter the holding state, and each time it enters the holding state, it corresponds to a holding frequency.
For convenience of understanding, as described with reference to fig. 2, as shown in fig. 2, each time before the time T1 corresponds to a locking frequency, so as to form a first frequency locking curve DAC1, the first frequency compensation curve may be a holding frequency when the clock system enters a holding state, and the holding frequency when the clock system enters the holding state at the time T1 further forms a first frequency holding curve DAC1'.
It should be appreciated that the first frequency compensation curve described above may be the hold frequency at which the clock system enters the hold state.
Further, in order to accurately acquire the first frequency compensation curve, the step S10 includes: acquiring a first frequency locking curve of a clock system before a T1 moment; a first frequency compensation curve is obtained from the first frequency lock curve based on a compensation hold algorithm.
It should be noted that, the compensation holding algorithm may be an algorithm for calculating a holding frequency at a corresponding time according to a locking frequency at a time of entering into holding, as shown in fig. 2, entering into holding after the time T1 of locking the clock system, holding for a time period of T2, and obtaining a first frequency compensation curve DAC1' based on the compensation algorithm after obtaining the first frequency locking curve DAC 1.
Step S20: continuing to lock the clock system for the duration of T2, and obtaining a second frequency locking curve of the clock system between the time T1 and the time T1+ T2;
it should be noted that the second frequency locking curve DAC2 may represent a locking frequency corresponding to each time point from the time T1 to the time T1+ T2 of the clock system.
In a specific implementation, after the time T1, the device continues to transmit the GPS signal to the clock system, so that the clock system continues to maintain for the time period T2 until the time T1+ T2, and stores the second frequency locking curve DAC2 between the time T1 and the time T1+ T2.
Step S30: determining a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve;
it should be noted that the first frequency deviation value accumulation may be an integral of an absolute value of a difference between the first frequency locking curve and the first frequency compensation curve between the time T1 and the time T1+ T2, as shown in fig. 2, and further, the step S30 includes: determining a first frequency deviation value accumulation between the T1 moment and the T1+ T2 moment through a first preset formula based on the second frequency locking curve and the first frequency compensation curve;
wherein the first preset formula is as follows:
wherein T1 is the time T1, H T1 For the first frequency deviation value accumulation, DAC2 is the second frequency lock curve and DAC1' is the first frequency compensation curve.
Step S40: continuing to lock the clock system for M duration to obtain a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M;
it can be understood that the duration M may be any duration, and may be set according to a measurement range required by a user, and with reference to fig. 2, the third frequency locking curve DAC3 may be a curve formed by the locking frequency of the clock system at any time between the time T1+ M and the time T1+ T2+ M.
Step S50: acquiring a fourth frequency locking curve of the clock system before the T1+ M moment, and determining a second frequency compensation curve according to the fourth frequency locking curve;
it should be noted that, since the device stores the frequency locking curve before the time T1+ T2+ M, the fourth frequency locking curve before the time T1+ M can be directly obtained.
It can be understood that, in order to accurately obtain the second frequency compensation curve, the step S50 includes: acquiring a fourth frequency locking curve of the clock system before the time T1+ M; and obtaining a second frequency compensation curve DAC3' according to the fourth frequency locking curve based on the compensation and maintenance algorithm.
Step S60: determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment according to the third frequency locking curve and the second frequency compensation curve;
it should be noted that the second frequency deviation value accumulation may be an integral of an absolute value of a difference between the third frequency locking curve and the second frequency compensation curve between the time T1+ M and the time T1+ T2+ M, as shown in fig. 2, and the step S60 further includes: determining the accumulation of a second frequency deviation value from the time T1+ M to the time T1+ T2+ M according to the third frequency locking curve and the second frequency compensation curve, wherein the step comprises the following steps;
determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment through a second preset formula according to the third frequency locking curve and the second frequency compensation curve;
wherein the second preset formula is as follows:
wherein T1+ M is the time of T1+ M, H T1+M And accumulating the second frequency deviation value, wherein the DAC3 is the third frequency locking curve, and the DAC3' is the second frequency compensation curve.
Step S70: and determining a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation.
It should be noted that, for convenience of subsequent use, the time corresponding to the generally measured phase shift value range may satisfy the symmetry requirement, i.e., the time T1-M to the time T1+ M.
In this embodiment, the device may determine a first frequency compensation curve according to a first frequency locking curve obtained by a clock system before a time T1; continuing to lock the time length of T2 to the clock system to obtain a second frequency locking curve of the clock system between the time T1 and the time T1+ T2; determining a first frequency deviation value accumulation from the time T1 to the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve; continuing to lock the clock system for M duration to obtain a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M; acquiring a fourth frequency locking curve of the clock system before the time T1+ M, and determining a second frequency compensation curve according to the fourth frequency locking curve; determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment according to the third frequency locking curve and the second frequency compensation curve; determining a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation; compared with the prior art that when a user needs to obtain frequency holding values corresponding to each time point in a target time period, a frequency deviation value corresponding to each time point needs to be obtained based on the T1 duration, namely, each time of measurement needs to enable a clock system to pass through the first T1 duration, and the embodiment can obtain the frequency deviation values corresponding to each time point in the range from the T1-M moment to the T1+ M moment only by one time of T1 duration, so that the measurement time can be shortened, and the measurement efficiency can be improved.
Referring to fig. 3, fig. 3 is a flowchart illustrating a clock hold phase offset value measuring method according to a second embodiment of the present invention.
As shown in fig. 3, in order to reduce the measurement error and improve the measurement accuracy in consideration of the existence of a certain error in the measurement result, based on the first embodiment, in this embodiment, the step S70 includes:
step S71: determining a first clock holding phase deviation value range of the clock system between the time T1 and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation;
it should be noted that the range of the first clock holding phase offset value may be a maximum range of the phase offset corresponding to the holding frequency when the clock system enters the holding state at any time between the time T1 and the time T1+ M, and if the holding frequency does not exceed the range of the first clock holding phase offset value, the holding frequency that the clock system enters the holding state at the time may be indicated to meet the user requirement.
Step S72: determining a second range of clock hold phase offset values for the clock system between time T1-M to the time T1 based on the first range of clock hold phase offset values;
further, in order to more accurately obtain the second target period clock frequency holding value range, before step S72, the method further includes:
acquiring an adjusting time interval of the digital-to-analog converter;
cumulatively determining a range of frequency-phase offset values per unit time based on the adjustment time interval and the second frequency offset value at the time T1+ M;
it should be noted that the digital-to-analog converter may be a device for adjusting the magnitude of the locking frequency in the clock system, and the adjustment time interval may be a time interval for adjusting the frequency of the digital-to-analog converter, and the adjustment time interval may be set according to actual conditions.
It will be appreciated that the above range of frequency phase offset values per unit time may be a range of frequency phase offset values corresponding to a single adjustment time interval.
In a specific implementation, the apparatus may determine the range of frequency phase offset values per unit time based on the adjustment time interval and the second frequency offset value at time T1+ M.
Accordingly, the step S72 includes: determining a second clock hold phase offset value range of the clock system between time T1-M to the time T1 based on the unit time frequency phase offset value range.
Step S73: and integrating the first clock holding phase deviation value range and the second clock holding phase deviation value range, and taking the integration result as the clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M.
It should be noted that, the repeated portions of the first clock holding phase offset value range and the second clock holding phase offset value range are integrated, and the non-repeated portions are added to obtain the target time period clock frequency holding value range, so as to enable the obtained result to be more accurate.
The apparatus of this embodiment determines a range of a first clock hold phase offset value for the clock system between time T1 and time T1+ M based on the first frequency offset value accumulation and the second frequency offset value accumulation; acquiring an adjusting time interval of the digital-to-analog converter; cumulatively determining a range of frequency-phase offset values per unit time based on the adjustment time interval and the second frequency offset value at time T1+ M; determining a second clock holding phase offset value range of the clock system between the time T1-M and the time T1 based on the unit time frequency phase offset value range; the range of the first clock holding phase deviation value and the range of the second clock holding phase deviation value are integrated, and the integrated result is used as the range of the clock holding phase deviation value of the clock system between the time T1-M and the time T1+ M, so that the measurement error can be reduced, and the measurement precision is improved.
Referring to fig. 4, fig. 4 is a flowchart illustrating a clock holding phase offset value measuring method according to a third embodiment of the present invention.
As shown in fig. 4, in order to further improve the reliability of the device obtaining the target time period clock frequency holding value range, in this embodiment, after step S70, the method further includes:
step S80: continuing to keep the time length of T2 for the clock system, and obtaining a phase deviation value of the clock system at the moment of T1+ T2+ M + T2;
it should be noted that the phase shift value at the time T1+ T2+ M + T2 can be directly obtained by measurement.
Step S90: judging whether the phase deviation value at the time of T1+ T2+ M + T2 is in a clock holding phase deviation value range from the time of T1-M to the time of T1+ M of the clock system;
step S100: if yes, the product is judged to meet the preset standard.
It can be understood that the above device can be used to determine whether a product meets a preset standard, and when a phase deviation value at a time T1+ T2+ M + T2 is within a range of a clock holding phase deviation value of the clock system between the time T1-M and the time T1+ M, it can be determined that the product meets the preset standard.
In an embodiment, the device stops outputting a GPS signal to enable the clock system to start entering a hold state at a time T1+ T2+ M, and keeps a time length of T2, obtains a phase offset value of the clock system at the time T1+ T2+ M + T2 by using an instrument, and determines whether the phase offset value at the time T1+ T2+ M + T2 is within a clock hold phase offset value range from the time T1-M to the time T1+ M, if so, it indicates that a product to be tested meets a preset standard, and if not, it indicates that the product to be tested does not meet the preset standard, thereby further improving reliability of the device in obtaining the clock frequency hold value range of the target time period.
In addition, referring to fig. 5, fig. 5 is a block diagram of a first embodiment of the clock holding phase offset value measuring apparatus according to the present invention, and the embodiment of the present invention further provides a clock holding phase offset value measuring apparatus, including:
a first frequency compensation curve obtaining module 501, configured to obtain a first frequency locking curve of a clock system before a time T1, and determine a first frequency compensation curve according to the first frequency locking curve;
a second frequency locking curve obtaining module 502, configured to continue to lock the clock system for the duration of T2, and obtain a second frequency locking curve of the clock system between the time T1 and the time T1+ T2;
a first frequency deviation value accumulation determining module 503, configured to determine a first frequency deviation value accumulation from the time T1 to the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve;
a third frequency locking curve obtaining module 504, configured to continue to lock the clock system for M durations, and obtain a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M;
a second frequency compensation curve determining module 505, configured to acquire a fourth frequency locking curve of the clock system before the T1+ M time, and determine a second frequency compensation curve according to the fourth frequency locking curve;
a second frequency deviation value accumulation determining module 506, configured to determine a second frequency deviation value accumulation from the time T1+ M to the time T1+ T2+ M according to the third frequency locking curve and the second frequency compensation curve;
a phase deviation value range determining module 507, configured to determine a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation.
The phase offset value range determining module 507 is further configured to determine a first clock holding phase offset value range of the clock system between the time T1 and the time T1+ M according to the first frequency offset value accumulation and the second frequency offset value accumulation; determining a second range of clock hold phase offset values for the clock system between time T1-M to the time T1 based on the first range of clock hold phase offset values; and integrating the first clock holding phase deviation value range and the second clock holding phase deviation value range, and taking the integration result as the clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M.
The phase offset value range determining module 507 is further configured to obtain an adjustment time interval of the digital-to-analog converter; cumulatively determining a range of frequency-phase offset values per unit time based on the adjustment time interval and the second frequency offset value at the time T1+ M; determining a second clock holding phase offset value range of the clock system between time T1-M to time T1 based on the unit time frequency phase offset value range.
In this embodiment, the device may determine a first frequency compensation curve according to a first frequency locking curve obtained by a clock system before a time T1; continuing to lock the time length of T2 to the clock system to obtain a second frequency locking curve of the clock system between the time T1 and the time T1+ T2; determining a first frequency deviation value accumulation from the time T1 to the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve; continuing to lock the clock system for M duration to obtain a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M; acquiring a fourth frequency locking curve of the clock system before the time T1+ M, and determining a second frequency compensation curve according to the fourth frequency locking curve; determining second frequency deviation value accumulation from the time T1+ M to the time T1+ T2+ M according to the third frequency locking curve and the second frequency compensation curve; determining a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation; compared with the prior art that when a user needs to obtain frequency holding values corresponding to each time point in a target time period, a frequency deviation value corresponding to each time point needs to be obtained based on the T1 duration, namely, each time of measurement needs to enable a clock system to pass through the first T1 duration, and the embodiment can obtain the frequency deviation values corresponding to each time point in the range from the T1-M moment to the T1+ M moment only by one time of T1 duration, so that the measurement time can be shortened, and the measurement efficiency can be improved.
Other embodiments or specific implementations of the clock holding phase shift value measuring device of the present invention may refer to the above method embodiments, and are not described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., a rom/ram, a magnetic disk, an optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent structures or equivalent processes performed by the present invention or directly or indirectly applied to other related technical fields are also included in the scope of the present invention.
Claims (10)
1. A method of clock-hold phase offset value measurement, the method comprising the steps of:
acquiring a first frequency locking curve of a clock system before a T1 moment, and determining a first frequency compensation curve according to the first frequency locking curve;
continuing to lock the clock system for the duration of T2, and obtaining a second frequency locking curve of the clock system between the time T1 and the time T1+ T2;
determining a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve;
continuing to lock the clock system for M duration to obtain a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M;
acquiring a fourth frequency locking curve of the clock system before the T1+ M moment, and determining a second frequency compensation curve according to the fourth frequency locking curve;
determining a second frequency deviation value accumulation from the T1+ M moment to the T1+ T2+ M moment according to the third frequency locking curve and the second frequency compensation curve;
and determining a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation.
2. The method of claim 1, wherein determining a range of clock holding phase offset values for the clock system between time T1-M and time T1+ M based on the first frequency offset value accumulation and the second frequency offset value accumulation comprises:
determining a first clock holding phase deviation value range of the clock system between the time T1 and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation;
determining a second range of clock maintenance phase offset values for the clock system between time T1-M to time T1 based on the first range of clock maintenance phase offset values;
and integrating the first clock holding phase deviation value range and the second clock holding phase deviation value range, and taking the integration result as the clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M.
3. The clock-hold phase offset value measurement method of claim 2, wherein, prior to the step of determining a second range of clock-hold phase offset values for the clock system between time T1-M to time T1 based on the first range of clock-hold phase offset values, further comprising:
acquiring an adjustment time interval of the digital-to-analog converter;
cumulatively determining a range of frequency-phase offset values per unit time based on the adjustment time interval and the second frequency offset value at the time T1+ M;
accordingly, the step of determining a second range of clock hold phase offset values for the clock system between times T1-M to time T1 based on the first range of clock hold phase offset values comprises:
determining a second clock holding phase offset value range of the clock system between time T1-M to time T1 based on the unit time frequency phase offset value range.
4. The method of any of claims 1-3, wherein the step of determining a range of clock holding phase offset values for the clock system between time T1-M and time T1+ M based on the first frequency offset value accumulation and the second frequency offset value accumulation is further followed by the step of:
continuing to keep the time length of T2 for the clock system, and obtaining a phase deviation value of the clock system at the moment of T1+ T2+ M + T2;
judging whether the phase deviation value of the time T1+ T2+ M + T2 is in a clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M;
if yes, the product is judged to meet the preset standard.
5. The method of claim 4, wherein the step of obtaining a first frequency lock curve of the clock system prior to time T1 and determining a first frequency compensation curve based on the first frequency lock curve comprises:
acquiring a first frequency locking curve of a clock system before a T1 moment;
and obtaining a first frequency compensation curve according to the first frequency locking curve based on a compensation and maintenance algorithm.
6. The method of claim 5, wherein the step of determining a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency lock curve and the first frequency compensation curve comprises:
determining a first frequency deviation value accumulation between the T1 moment and the T1+ T2 moment through a first preset formula based on the second frequency locking curve and the first frequency compensation curve;
wherein the first preset formula is as follows:
wherein T1 is the time T1, H T1 For the first frequency deviation value accumulation, DAC2 is the second frequency lock curve, and DAC1' is the first frequency compensation curve.
7. The method of claim 6, wherein the step of determining a second frequency deviation value accumulation from the time T1+ M to the time T1+ T2+ M according to the third frequency locking curve and the second frequency compensation curve comprises;
determining a second frequency deviation value accumulation from the time T1+ M to the time T1+ T2+ M through a second preset formula according to the third frequency locking curve and the second frequency compensation curve;
wherein the second preset formula is as follows:
wherein T1+ M is the time of T1+ M, H T1+M And accumulating the second frequency deviation value, wherein the DAC3 is the third frequency locking curve, and the DAC3' is the second frequency compensation curve.
8. A clock holding phase offset value measuring apparatus, characterized in that the clock holding phase offset value measuring apparatus comprises:
the first frequency compensation curve acquisition module is used for acquiring a first frequency locking curve of a clock system before the time T1 and determining a first frequency compensation curve according to the first frequency locking curve;
a second frequency locking curve acquisition module for continuing to lock the clock system for a duration of T2, obtaining a second frequency locking curve of the clock system between the time T1 and the time T1+ T2;
a first frequency deviation value accumulation determining module, configured to determine a first frequency deviation value accumulation between the time T1 and the time T1+ T2 based on the second frequency locking curve and the first frequency compensation curve;
the third frequency locking curve acquisition module is used for continuously locking the clock system for M time length to acquire a third frequency locking curve of the clock system between the time T1+ M and the time T1+ T2+ M;
a second frequency compensation curve determining module, configured to acquire a fourth frequency locking curve of the clock system before the time T1+ M, and determine a second frequency compensation curve according to the fourth frequency locking curve;
a second frequency deviation value accumulation determining module, configured to determine, according to the third frequency locking curve and the second frequency compensation curve, a second frequency deviation value accumulation from the time T1+ M to the time T1+ T2+ M;
and the phase deviation value range determining module is used for determining a clock maintaining phase deviation value range of the clock system between the time T1-M and the time T1+ M according to the first frequency deviation value accumulation and the second frequency deviation value accumulation.
9. The clock-holdover phase offset value measurement apparatus of claim 8, wherein the phase offset value range determination module is further configured to determine a first range of clock-holdover phase offset values for the clock system between the time T1 and the time T1+ M based on the first frequency offset value accumulation and the second frequency offset value accumulation; determining a second range of clock hold phase offset values for the clock system between time T1-M to the time T1 based on the first range of clock hold phase offset values; and integrating the first clock holding phase deviation value range and the second clock holding phase deviation value range, and taking the integration result as the clock holding phase deviation value range of the clock system between the time T1-M and the time T1+ M.
10. The clock-hold phase offset value measurement apparatus of claim 9, wherein the phase offset value range determination module is further configured to obtain an adjustment time interval of a digital-to-analog converter; cumulatively determining a range of frequency-phase offset values per unit time based on the adjustment time interval and the second frequency offset value at the time T1+ M; determining a second clock hold phase offset value range of the clock system between time T1-M to the time T1 based on the unit time frequency phase offset value range.
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