CN114978146A - Level conversion circuit, chip and electronic equipment - Google Patents
Level conversion circuit, chip and electronic equipment Download PDFInfo
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- CN114978146A CN114978146A CN202210573949.5A CN202210573949A CN114978146A CN 114978146 A CN114978146 A CN 114978146A CN 202210573949 A CN202210573949 A CN 202210573949A CN 114978146 A CN114978146 A CN 114978146A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
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Abstract
The invention discloses a level conversion circuit, a chip and an electronic device, wherein the level conversion circuit comprises: the input unit is connected with the signal input end and used for carrying out voltage limiting processing on an input signal of the signal input end to obtain a first voltage; the substrate bias conversion unit is connected with the input unit and used for generating a first current and a second current based on different substrate bias effects under the action of a first voltage; the current mirror image unit is connected with the substrate bias conversion unit and used for comparing the first current with the second current; and the output voltage conversion unit is connected with the current mirror image unit and the signal output end and is used for performing voltage conversion on the comparison result to obtain an output signal and outputting the output signal through the signal output end. Therefore, the level conversion function with low power consumption and large swing amplitude is realized, and the applicability of the level conversion circuit is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a level shifter, a chip, and an electronic device.
Background
With the advent of the information and intelligent era, devices with various functions are integrated, and due to different working characteristics, the signal levels of the devices with different functions are also various, so that a circuit capable of adapting to level conversion between different voltage domains needs to be designed to realize rapid conversion between different signal levels so as to realize signal transmission between the devices with various functions.
The traditional level conversion circuit can meet the level conversion between fixed voltage domains in a chip so as to meet the signal transmission between systems with known corresponding voltage domains in the chip. For example, fig. 1 shows a low-level to high-level conversion circuit, which performs level conversion between fixed voltage domains through a differential feedback structure, but the differential feedback structure requires that input terminals present logically opposite differential signals, which not only limit the input signal range of the level conversion circuit, but also cause large power consumption during high-voltage conversion due to phase errors of the differential signals; meanwhile, the level shift circuit has difficulty in meeting the demand for a unipolar input signal whose level is uncertain.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, a first object of the present invention is to provide a level shift circuit, which can implement a unipolar large swing of an input signal by performing compression and amplitude limiting on the input signal, so as to meet a wider signal level input application, and can implement fine control of level shift and reduce power consumption in a high voltage shift process by using a substrate bias structure, thereby implementing a level shift function with low power consumption and a large swing, and improving applicability of the level shift circuit.
A second objective of the present invention is to provide a chip.
A third object of the invention is to propose an electronic device.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a level shift circuit, including: the input unit is connected with the signal input end and used for carrying out voltage limiting processing on an input signal of the signal input end to obtain a first voltage; the substrate bias conversion unit is connected with the input unit and used for generating a first current and a second current based on different substrate bias effects under the action of a first voltage; the current mirror image unit is connected with the substrate bias conversion unit and used for comparing the first current with the second current; and the output voltage conversion unit is connected with the current mirror image unit and the signal output end and is used for performing voltage conversion on the comparison result to obtain an output signal and outputting the output signal through the signal output end.
According to the level conversion circuit provided by the embodiment of the invention, through carrying out compression amplitude limiting on the input signal, the unipolar large amplitude of oscillation of the input signal can be realized, wider signal level input application is met, and through adopting a substrate biasing structure, the fine control of level conversion can be realized, and the power consumption in the high-voltage conversion process is reduced, so that the level conversion function of low power consumption and large amplitude of oscillation is realized, and the applicability of the level conversion circuit is improved.
According to one embodiment of the present invention, an input unit includes: the amplitude limiting circuit is connected with the signal input end and is used for carrying out voltage amplitude limiting processing on the input signal to obtain a second voltage; and the voltage division circuit is connected with the amplitude limiting circuit and is used for carrying out voltage division processing on the second voltage to obtain a first voltage.
According to an embodiment of the present invention, a clip circuit includes: one end of the first resistor is connected with the signal input end; and the cathode of the voltage stabilizing diode is connected with the other end of the first resistor and forms a first node, and the anode of the voltage stabilizing diode is grounded.
According to an embodiment of the present invention, a voltage dividing circuit includes: one end of the second resistor is connected with the first node; and the control electrode and the first electrode of the first switch tube are respectively connected with the other end of the second resistor and form a second node, the second electrode of the first switch tube is grounded, and the second node is connected with the substrate bias conversion unit.
According to one embodiment of the present invention, a substrate bias converting unit includes: the control electrode of the second switching tube is connected with the input unit, the first electrode of the second switching tube is connected with the current mirror image unit, and the substrate of the second switching tube is grounded; a control electrode of the third switching tube is connected with a control electrode of the second switching tube, a first electrode of the third switching tube is connected with the current mirror unit, and a second electrode of the third switching tube, a substrate of the third switching tube and a second electrode of the second switching tube are connected and form a third node; and one end of the third resistor is connected with the third node, and the other end of the third resistor is grounded.
According to one embodiment of the present invention, a current mirror cell includes: a control electrode and a first electrode of the fourth switching tube are respectively connected with a first electrode of the second switching tube, and a second electrode of the fourth switching tube is connected with a power supply; and the control electrode of the fifth switching tube is connected with the control electrode of the fourth switching tube, the first electrode of the fifth switching tube is connected with the first electrode of the third switching tube and is provided with a fourth node, the second electrode of the fifth switching tube is connected with the power supply, and the fourth node is connected with the output voltage conversion unit.
According to an embodiment of the present invention, the current mirror cell further includes: and the clamping circuit is arranged between the first pole of the fourth switching tube and the first pole of the fifth switching tube and is used for clamping the voltage of the fourth node.
According to one embodiment of the present invention, a clamp circuit includes: and the control electrode and the first electrode of the sixth switching tube are connected with the fourth node, and the second electrode of the sixth switching tube is connected with the first electrode of the fourth switching tube.
According to an embodiment of the present invention, the voltage conversion circuit further includes: and the isolation unit is arranged between the substrate bias conversion unit and the current mirror image unit and is used for carrying out isolation protection on the substrate bias conversion unit.
According to one embodiment of the present invention, an isolation unit includes: the voltage division circuit is used for carrying out voltage division processing on the power supply to obtain a third voltage; and the isolation circuit is connected with the voltage division circuit and is used for carrying out isolation protection on the substrate bias conversion unit under the action of the third voltage.
According to an embodiment of the present invention, a voltage dividing circuit includes: one end of the fourth resistor is connected with the power supply; a control electrode and a first electrode of the seventh switching tube are respectively connected with the other end of the fourth resistor and form a fifth node, and the fifth node is connected with the isolation circuit; and the control electrode and the first electrode of the eighth switching tube are respectively connected with the second electrode of the seventh switching tube, and the second electrode of the eighth switching tube is grounded.
According to one embodiment of the invention, an isolation circuit comprises: a control electrode of the ninth switching tube is connected with the voltage dividing circuit, a first electrode of the ninth switching tube is connected with a first electrode of the fourth switching tube, and a second electrode of the ninth switching tube is connected with a first electrode of the second switching tube; and a control electrode of the tenth switching tube is connected with a control electrode of the ninth switching tube, a first electrode of the tenth switching tube is connected with a first electrode of the fifth switching tube, and a second electrode of the tenth switching tube is connected with a first electrode of the third switching tube.
According to an embodiment of the present invention, an output voltage converting unit includes: the control electrode of the eleventh switch tube is connected with the current mirror image unit, the first electrode of the eleventh switch tube is connected with the signal output end, and the second electrode of the eleventh switch tube is connected with the power supply; and one end of the fifth resistor is connected with the first pole of the eleventh switching tube, and the other end of the fifth resistor is connected with the reference ground.
In order to achieve the above object, a second embodiment of the invention provides a chip including the foregoing level shift circuit.
According to the chip provided by the embodiment of the invention, the level conversion circuit is adopted, the unipolar large amplitude of oscillation of the input signal can be realized by compressing and limiting the input signal, the wider signal level input application is met, the fine control of level conversion can be realized by adopting the substrate biasing structure, and the power consumption in the high-voltage conversion process is reduced, so that the level conversion function of low power consumption and large amplitude of oscillation is realized, the applicability of the chip is improved, and the power consumption of the chip is reduced.
In order to achieve the above object, an embodiment of a third aspect of the present invention provides an electronic device, including the foregoing chip.
According to the embodiment of the invention, by adopting the chip and compressing and amplitude limiting the input signal, the unipolar large amplitude of oscillation of the input signal can be realized, wider signal level input application can be met, and by adopting the substrate biasing structure, the fine control of level conversion can be realized, and the power consumption in the high-voltage conversion process is reduced, so that the level conversion function of low power consumption and large amplitude of oscillation is realized, the applicability of the electronic equipment is improved, and the power consumption of the electronic equipment is reduced.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a circuit diagram of a low-to-high conversion circuit in the related art;
FIG. 2 is a diagram illustrating a level shift circuit according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a level shifting circuit according to one embodiment of the present invention;
FIG. 4 is a schematic diagram of voltage compression conversion of an input cell according to an embodiment of the invention;
FIG. 5 is a schematic diagram of voltage conversion clamped by a clamping unit according to an embodiment of the present invention;
FIG. 6 is a circuit diagram of a level shifting circuit according to another embodiment of the present invention;
FIG. 7 is a schematic diagram of input-output level shifting according to one embodiment of the present invention;
FIG. 8 is a schematic diagram of a chip according to an embodiment of the invention;
fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
A level shift circuit, a chip, and an electronic apparatus according to an embodiment of the present invention will be described with reference to the drawings.
Fig. 2 is a schematic structural diagram of a level shift circuit according to an embodiment of the invention.
Referring to fig. 2, the level shift circuit 100 includes: an input unit 110, a substrate bias converting unit 120, a current mirroring unit 130, and an output voltage converting unit 140.
The input unit 110 is connected to the signal input end VIN, and configured to perform voltage limiting processing on an input signal of the signal input end VIN to obtain a first voltage; the substrate bias converting unit 120 is connected to the input unit 110, and configured to generate a first current and a second current based on different substrate bias effects under the action of a first voltage; the current mirror unit 130 is connected to the substrate bias converting unit 120, and is configured to compare the first current with the second current; the output voltage converting unit 140 is connected to the current mirror unit 130 and the signal output terminal VOUT, and is configured to perform voltage conversion on the comparison result to obtain an output signal, and output the output signal through the signal output terminal VOUT.
Specifically, the input unit 110 is used as a receiving and processing portion of the input signal, and is provided with a limiting structure, and the input signal at the signal input end VIN is subjected to voltage range compression by the limiting structure to obtain a first voltage, so that the first voltage meets the working voltage range of the substrate bias conversion unit 120, and thus the unipolar large swing of the input signal can be realized. The substrate bias converting unit 120 is provided with a substrate bias structure, and a structure for comparing differential currents is realized based on the substrate bias structure, the substrate bias structure has different substrate bias effects, and generates a first current and a second current under the action of a first voltage. The current mirror unit 130 is mainly used for performing a current mirror comparison of the first current and the second current. The output voltage converting unit 140 is mainly configured to convert a comparison result of the first current and the second current into a logic level required by an output terminal, and output the logic level through the signal output terminal VOUT.
In the above embodiment, through performing compression amplitude limiting on the input signal, a unipolar large amplitude of oscillation of the input signal can be achieved, and a wider signal level input application is satisfied.
In some embodiments, as shown with reference to fig. 3, the input unit 110 includes: the amplitude limiting circuit 111 is connected with the signal input end VIN, and is used for performing voltage amplitude limiting processing on the input signal to obtain a second voltage; the voltage dividing circuit 112 is connected to the amplitude limiting circuit 111, and is configured to divide the second voltage to obtain the first voltage.
Further, with continued reference to fig. 3, the clipping circuit 111 includes: a first resistor R1 and a zener diode Z, wherein one end of the first resistor R1 is connected with the signal input end VIN; the cathode of the zener diode Z is connected to the other end of the first resistor R1 and forms a first node J1, and the anode of the zener diode Z is grounded GND.
The voltage dividing circuit 112 includes: a second resistor R2 and a first switch tube M1, wherein one end of the second resistor R2 is connected with a first node J1; a control electrode and a first electrode of the first switch M1 are respectively connected to the other end of the second resistor R2 and form a second node J2, a second electrode of the first switch M1 is connected to the ground GND, and the second node J2 is connected to the substrate bias converting unit 120.
Specifically, the amplitude limiting circuit 111 is mainly used for performing voltage range compression on the input signal at the signal input terminal VIN to implement a unipolar large swing of the input signal.
Referring to fig. 3, the first resistor R1 and the zener diode Z form a series amplitude limiting structure, and the zener diode Z mainly plays a role of voltage limiting protection for the first node J1, wherein when the voltage of the input signal at the signal input end VIN is large, the second voltage at the corresponding first node J1 is larger than a set value VT (i.e., the reverse breakdown voltage of the zener diode Z), the zener diode Z is turned on, a large current flows through, the voltage of the input signal is concentrated at two ends of the first resistor R1 through the current limiting function of the first resistor R1, and the second voltage at the first node J1 is VT; when the voltage of the input signal at the signal input end VIN is smaller, the corresponding second voltage at the first node J1 is smaller than the set value VT, the zener diode Z is not turned on, and the flowing current is small, and at this time, the second voltage at the first node J1 is mainly generated by connecting the first resistor R1, the second resistor R2, and the first switching tube M1 in series. Aiming at the voltage and current driving range of the input signal, the large voltage range of the input signal can be converted into the variation range of 0-VT by reasonably setting the parameters of the first resistor R1 and the voltage stabilizing diode Z, so that the voltage range of the input signal is compressed in a voltage detection and current leakage mode, and the unipolar large swing of the input signal can be realized.
Further, the voltage divider 112 may further compress the second voltage to obtain the first voltage, so that the first voltage meets the operating voltage range of the substrate bias converting unit 120. Referring to fig. 3, the second resistor R2 and the first switch transistor M1 are connected in series to determine the variation range of the first voltage (i.e., the voltage at the second node J2), wherein the second resistor R2 is used as a voltage divider to convert the second voltage into the first voltage, and the power consumption current of the input terminal is reduced while protecting the first switch transistor M1.
As a specific example, referring to fig. 4, assuming that the reverse breakdown voltage of the zener diode Z is 3V, when the voltage of the input signal is 50V, the second voltage at the first node J1 is higher than the reverse breakdown voltage of the zener diode Z, the zener diode Z is turned on, the second voltage at the first node J1 is 3V, and after voltage division, the first voltage at the second node J2 is 1.8V; when the voltage of the input signal is 2V, the second voltage at the first node J1 is lower than the reverse breakdown voltage of the zener diode Z, the zener diode Z is not conductive, and the second voltage at the second node J2 is 1V after voltage division, so that the large voltage range of the input signal is converted into a variation range of 0-1.8V.
It should be noted that the zener diode Z may also be replaced by a clipping device or a circuit similar to the voltage detection bleeder, that is, all circuit structures that enable the first node J1 to maintain the small voltage fluctuation through the fixed-value voltage detection bleeder manner are within the protection scope of the present application. The first switch M1 corresponds to a diode structure, and the first switch M1 may be replaced by a device or a circuit with a similar diode structure, all of which are within the protection scope of the present application.
In the above embodiment, the dynamic range compression of the input signal is realized by using the current-voltage conduction property of the zener diode, the switching tube and the resistor, and through amplitude limiting, current limiting and voltage dividing conversion, the high-voltage unipolar large-swing reception of the input signal is achieved, and the wider signal level input application is met. That is to say, the receiving and processing part of the input signal can realize the unipolar large swing of the input signal by adopting the signal compression protection structure.
In some embodiments, referring to fig. 3, the substrate bias converting unit 120 includes: a second switching tube M2, a third switching tube M3 and a third resistor R3, wherein a control electrode of the second switching tube M2 is connected to the input unit 110, a first electrode of the second switching tube M2 is connected to the current mirror unit 130, and a substrate of the second switching tube M2 is grounded GND; a gate of the third switching transistor M3 is connected to a gate of the second switching transistor M2, a first gate of the third switching transistor M3 is connected to the current mirror unit 130, a second gate of the third switching transistor M3, a substrate of the third switching transistor M3 and a second gate of the second switching transistor M2 are connected and a third node J3 is formed; one end of the third resistor R3 is connected to the third node J3, and the other end of the third resistor R3 is grounded to GND.
Specifically, the second switch tube M2, the third switch tube M3 and the third resistor R3 form a differential input structure, wherein the second switch tube M2 and the third switch tube M3 are of the same type but different sizes, for example, the second switch tube M2 and the third switch tube M3 are both PMOS tubes, and considering the matching layout effect, the width-to-length ratio of the second switch tube M2 and the third switch tube M3 is N:1, where N is greater than 1, that is, the width-to-length ratio of the second switch tube M2 is greater than that of the third switch tube M3.
When the second switching tube M2 and the third switching tube M3 are both PMOS tubes, the substrate of the second switching tube M2 is directly grounded to GND, and the source is grounded to GND through the third resistor R3, that is, a substrate bias voltage is added between the source of the second switching tube M2 and the substrate, the magnitude of the substrate bias voltage is determined by the voltage across the third resistor R3, and as the substrate bias voltage increases, the current of the second switching tube M2 is influenced by the substrate bias effect to increase; the substrate and the source of the third switching tube M3 are directly connected, that is, there is no substrate bias voltage between the substrate and the source of the third switching tube M3, and the third switching tube M3 is not affected by the substrate bias effect. Since the gate voltages of the second switching tube M2 and the third switching tube M3 are the same, the input first voltage can be converted into a current difference between the first current and the second current based on different substrate offset effects and sizes under the same gate voltage (i.e., the first voltage), and both the second switching tube M2 and the third switching tube M3 operate in the non-saturation region.
Specifically, when the gate voltage, i.e., the first voltage, of the second switch tube M2 and the third switch tube M3 is smaller, the current flowing through the third resistor R3 is smaller, the voltage at the two ends of the third resistor R3 is smaller, and the substrate bias effect of the second switch tube M2 is negligible, at this time, the magnitude of the drain-source current, i.e., the first current, of the second switch tube M2 and the magnitude of the drain-source current, i.e., the second current, of the third switch tube M3 are mainly influenced by the width-to-length ratio of the switch tubes, and since the width-to-length ratios of the second switch tube M2 and the third switch tube M3 are N:1, N is greater than 1, the first current of the second switch tube M2 is greater than the second current of the third switch tube M3.
The first current and the second current gradually increase with the increase of the first voltage, the voltage across the third resistor R3 gradually increases, the substrate bias effect of the second switch tube M2 gradually increases, so that the first current gradually decreases, when the influence of the substrate bias effect on the current is equal to the influence of the width-length ratio of the switch tube itself on the current, the first current of the second switch tube M2 is equal to the second current of the third switch tube M3, at this time, the first voltage is a voltage conversion threshold, and the voltage conversion threshold determines the level conversion value of the whole circuit. It should be noted that, since the voltage conversion threshold is determined by the width-to-length ratio of the switching tube and the substrate bias voltage (i.e. the voltage across the third resistor R3), and the substrate bias voltage is related to the width-to-length ratio of the third resistor R3 and the switching tube, by selecting a suitable device type, and by adjusting the width-to-length ratio of the switching tube and the resistance value of the third resistor R3, the level conversion value, the power consumption, and the like can be flexibly adjusted to meet the functional requirements of the whole circuit.
When the first voltage continues to increase, the influence of the substrate bias effect of the second switching tube M2 on the current is greater than the influence of the width-to-length ratio of the switching tube itself on the current, at this time, the first current of the second switching tube M2 is smaller than the second current of the third switching tube M3, and the current difference between the first current and the second current increases with the increase of the first voltage, so that the first voltage is converted into the current difference between the first current and the second current, and a corresponding converted voltage is obtained based on the current difference in the following process.
In the above embodiment, by adopting the structure of current differential input of the substrate bias structure, based on the sizes of different switching tubes and the substrate bias effect, the low-power-consumption fine control of the level switching threshold can be realized. Particularly, the level shift circuit of traditional difference feedback structure mainly conducts current difference value comparison through grid source voltage control, voltage and current control are exponential relation, when voltage variation is great, cause the power consumption variation of level shift to change greatly, and the exponential control relation of suppression voltage electric current that the conversion based on substrate bias effect can be fine, cooperation third resistance can realize substrate bias suppression and grid source voltage control between balanced, guarantee in whole level shift interval, the power consumption changes very little, cooperate the voltage compression function of input element simultaneously, realize the fine control of low-power consumption of whole circuit. Namely, the voltage compression of the input unit can greatly reduce large power consumption change in the level conversion process, the substrate bias effect can further inhibit the exponential control relation of the grid source voltage and the grid source current, the sizes of the switch tube and the third resistor can be flexibly adjusted, and the level conversion value and the power consumption can be finely controlled.
In some embodiments, continuing to refer to fig. 3, the current mirror unit 130 includes: a fourth switching tube M4 and a fifth switching tube M5, a control electrode and a first electrode of the fourth switching tube M4 are respectively connected with a first electrode of the second switching tube M2, and a second electrode of the fourth switching tube M4 is connected with a power supply VDD; a control electrode of the fifth switch tube M5 is connected to a control electrode of the fourth switch tube M4, a first electrode of the fifth switch tube M5 is connected to a first electrode of the third switch tube M3 and is formed with a fourth node J4, a second electrode of the fifth switch tube M5 is connected to the power supply VDD, and the fourth node J4 is connected to the output voltage conversion unit 140.
Specifically, the fourth switching tube M4 and the fifth switching tube M5 form a mirror current mirror, and the type, structure and size of the fourth switching tube M4 and the fifth switching tube M5 are the same, for example, the fourth switching tube M4 and the fifth switching tube M5 are NMOS tubes with the same size and structure, so as to implement a complete mirror function of the differential circuit. The fourth switching tube M4 and the fifth switching tube M5 can both operate in a saturation region by setting the voltage of the power supply VDD, and since the fourth switching tube M4 and the fifth switching tube M5 adopt the same type, structure and size and have the same gate-source voltage, the drain-source current of the fourth switching tube M4 is equal to the drain-source current of the fifth switching tube M5, and the drain-source current of the fourth switching tube M4 is equal to the first current, so the output current at the fourth node J4 is the current difference between the first current and the second current, that is, the comparison result of the differential currents.
Therefore, the comparison of the first current and the second current output by the substrate bias conversion unit is realized through the current mirror circuit formed by the fourth switching tube and the fifth switching tube, and the comparison result is output to the output voltage conversion unit.
In some embodiments, with continued reference to fig. 3, the current mirror unit 130 further includes: and the clamping circuit 131 is arranged between the first pole of the fourth switching tube M4 and the first pole of the fifth switching tube M5, and is used for clamping the voltage of the fourth node J4 so as to protect subsequent circuits.
Specifically, as the input signal increases, the current difference between the first current and the second current increases, the voltage difference between the first pole of the fourth switching tube M4 and the first pole of the fifth switching tube M5 increases, and the output voltage at the fourth node J4 increases, so that the clamp circuit 131 may be added between the first pole of the fourth switching tube M4 and the first pole of the fifth switching tube M5 to control the output voltage within a reasonable voltage range for protecting the subsequent circuits.
Further, referring to fig. 3, the clamp circuit 131 includes: sixth switch M6, the control terminal and the first terminal of sixth switch M6 are coupled to fourth node J4, and the second terminal of sixth switch M6 is coupled to the first terminal of fourth switch M4.
Specifically, the sixth switching tube M6 is the same as the fourth switching tube M4 and the fifth switching tube M5 in type, the sixth switching tube M6 may be a PMOS tube, and the fourth switching tube M4 and the sixth switching tube M6 are all connected in a diode type manner, so that the current and the voltage of the branch where they are located change exponentially, that is, a very small voltage change causes a very large current conduction, thereby providing a large current conversion range for the substrate bias conversion unit 120, when the output voltage at the fourth node J4 is higher than a certain value, it indicates that the voltage at this point exceeds the withstand voltage of the subsequent circuit, the corresponding difference between the first current and the second current is too large, the sixth switching tube M6 is turned on, and the output voltage at the fourth node J4 is clamped at a fixed value, so as to protect the subsequent circuit.
As a specific example, referring to fig. 5, when the first voltage at the second node J2 rises to the voltage shown by the dotted line in the figure, the voltage difference between the first pole of the fourth switching tube M4 and the first pole of the fifth switching tube M5 exceeds a certain value, and the sixth switching tube M6 is turned on. The current of the branch in which the fourth switching tube M4 and the sixth switching tube M6 are connected in a diode manner flows from the power supply VDD to the ground through the fourth switching tube M4 and the sixth switching tube M6, and the current-voltage relationship of the branch changes exponentially, that is, the voltage change is small in a large current change interval, so that the voltage at the fourth node J4 changes basically around VDD-2VTH, and the voltage change is small and is represented as being clamped at VDD-2VTH, where VTH is the conduction voltage of the fourth switching tube M4 (that is, the sixth switching tube M6), so that subsequent circuits are protected, for example, the control electrode of the eleventh switching tube M11 in fig. 6 is protected, so that the voltage of the control electrode of the eleventh switching tube M11 changes between VDD and VDD-2VTH in the whole conversion process.
It should be noted that, the clamp circuit 131 may be formed by connecting two or more MOS transistors in parallel, or by using NMOS transistors in reverse connection, or by using other forms of clamp circuits such as diodes and transistors, and is not limited herein.
Therefore, the clamping function of the voltage of the fourth node is realized, and the safe use of the level conversion circuit is protected.
In some embodiments, referring to fig. 6, the level shift circuit 100 further includes: and an isolation unit 150, wherein the isolation unit 150 is arranged between the substrate bias conversion unit 120 and the current mirror 130 unit, and is used for performing isolation protection on the substrate bias conversion unit 120.
Specifically, since the switching tubes of the substrate bias conversion unit 120 all work in the non-saturation region, the requirement for the voltage of the switching tubes is high, and the isolation unit 150 is added between the substrate bias conversion unit 120 and the current mirror unit 130, so that the voltage of the power supply VDD can be prevented from being poured into the substrate bias conversion unit 120 through the current mirror unit 130, and the switching tubes of the substrate bias conversion unit 120 work in a wrong logic, and meanwhile, the switching tubes of the substrate bias conversion unit 120 can be selected to obtain a larger space, so that the flexibility of design is increased, the accuracy of voltage conversion is improved, and high-voltage conversion can be realized.
Therefore, by adding the isolation unit, the working voltage of the substrate bias conversion unit is not influenced by the current mirror image unit, the substrate bias conversion unit is protected, meanwhile, the flexibility of design is increased, and the precision of voltage conversion is improved.
Further, with continued reference to fig. 6, the isolation unit 150 includes: the voltage divider circuit 151 and the isolation circuit 152, the voltage divider circuit 151 is used for performing voltage division processing on the power supply VDD to obtain a third voltage; the isolation circuit 152 is connected to the voltage dividing circuit 151, and is used for performing isolation protection on the substrate bias converting unit 120 under the action of the third voltage.
Further, the voltage dividing circuit 151 includes: a fourth resistor R4, a seventh switch tube M7 and an eighth switch tube M8, wherein one end of the fourth resistor R4 is connected with a power supply VDD; a control electrode and a first electrode of the seventh switch tube M7 are respectively connected with the other end of the fourth resistor R4 and form a fifth node J5, and the fifth node J5 is connected with the isolation circuit 152; a control pole and a first pole of the eighth switch M8 are respectively connected to the second pole of the seventh switch M7, and the second pole of the eighth switch M8 is grounded to GND.
The isolation circuit 152 includes: a ninth switch tube M9 and a tenth switch tube M10, wherein a control electrode of the ninth switch tube M9 is connected to the voltage dividing circuit 151, a first electrode of the ninth switch tube M9 is connected to a first electrode of the fourth switch tube M4, and a second electrode of the ninth switch tube M9 is connected to a first electrode of the second switch tube M2; a gate of the tenth switching transistor M10 is connected to a gate of the ninth switching transistor M9, a first pole of the tenth switching transistor M10 is connected to a first pole of the fifth switching transistor M5, and a second pole of the tenth switching transistor M10 is connected to a first pole of the third switching transistor M3.
Specifically, referring to fig. 6, the fourth resistor R4 functions to divide and limit voltage, so as to reduce power consumption of the voltage divider circuit; the seventh switch tube M7 and the eighth switch tube M8 are both diode-connected, and by adjusting the fourth resistor R4 and selecting a proper switch tube, it can be ensured that the two switch tubes are stably turned on under the driving of the power supply VDD, and at this time, the voltage at the fifth node J5, i.e., the third voltage, is about 2 times the threshold voltage VTH. The voltage dividing circuit 151 supplies the voltage to the isolation unit 152.
The ninth switch tube M9 and the tenth switch tube M10 in the isolation unit 152 are of the same type and may be PMOS tubes, and through the body diode characteristics thereof, unidirectional voltage isolation may be achieved, so as to prevent the voltage of the power supply VDD from affecting the substrate bias conversion unit 120, and meanwhile, through adjusting the third voltage, the conduction voltage drop of the ninth switch tube M9 and the tenth switch tube M10 may be reduced, so as not to affect the voltage conversion function of the substrate bias conversion unit 120. In practical applications, the relationship between power consumption and voltage can be balanced by reasonably selecting parameters of the fourth resistor R4, the seventh switching tube M7 and the eighth switching tube M8, so that the ninth switching tube M9 and the tenth switching tube M10 can realize isolated output with low power consumption without affecting the conversion function of the substrate bias conversion unit 120. Therefore, the substrate bias conversion unit, the current mirror image unit and the output voltage conversion unit are isolated on the premise of not influencing the conversion function of the substrate bias conversion unit, the influence of external voltage provided by a power supply on the substrate bias conversion unit is avoided, and a level conversion circuit is protected.
In some embodiments, as shown with reference to fig. 3, the output voltage converting unit 140 includes: an eleventh switch tube M11 and a fifth resistor R5, a control electrode of the eleventh switch tube M11 is connected to the current mirror unit 130, a first electrode of the eleventh switch tube M11 is connected to the signal output terminal VOUT, and a second electrode of the eleventh switch tube M11 is connected to the power supply VDD; one end of the fifth resistor R5 is connected to the first pole of the eleventh switch M11, and the other end of the fifth resistor R5 is connected to the ground VSS.
Specifically, the eleventh switch tube M11 may be an NMOS tube, and forms a common source amplifying structure with the fifth resistor R5, and amplifies the gate voltage of the eleventh switch tube M11, that is, the output voltage at the fourth node J4, and converts the amplified voltage into an output signal. The level switching time and the magnitude of the power consumption current can be controlled by adjusting parameters of the fifth resistor R5 and the eleventh switch tube M11, and besides the current limiting function of the fifth resistor R5, the flexible selection of the potential of the reference ground VSS can be realized, so that the flexible configuration of the voltage interval of the output signal is realized, and the large swing of the output signal is realized.
As a specific example, referring to fig. 7, when the input signal is 2V or 50V, the voltage of the output signal is the voltage of the power supply VDD, so that unipolar input signals with different voltages are converted into a certain logic level, and the voltage of the reference ground VSS and the power supply voltage VDD can be flexibly selected, so as to achieve flexible configuration of the voltage interval of the output signal. Meanwhile, as shown in fig. 7, when the input signal is reduced to 2V, there is a significant delay in the level shift time, which can be controlled by adjusting the parameters of the eleventh switching tube M11 and the fifth resistor R5. It should be noted that the auxiliary circuit may be added to reduce power consumption based on the difference between the voltage intervals of the output signals.
In the above embodiment, the common source amplifying structure formed by the switching tube and the resistor not only can convert the comparison result of the differential current into the output signal, but also can realize a large swing of the output signal through the fifth resistor, thereby effectively improving the flexibility of setting the voltage interval of the output signal, and enabling the level conversion circuit to be suitable for signal transmission between different system levels.
In summary, according to the level shift circuit of the embodiment of the present invention, by using the signal compression protection structure, a unipolar large swing of an input signal can be realized, and a wider signal level input application is satisfied; by adopting a current differential input structure of a substrate biasing structure, the low-power-consumption fine control of a level conversion threshold can be realized, and the power consumption in the conversion process, especially the power consumption in the high-voltage conversion process, can be reduced; through current comparison, high-voltage protection and an active amplification structure, the level of an output signal can be flexibly configured according to requirements, and the large swing amplitude of the output signal is met. The whole circuit can realize signal level conversion between different voltage domains, realize signal transmission between devices with different functions, solve the problems of single voltage range and poor universality of the traditional level conversion circuit and have strong applicability.
In some embodiments, a chip is also provided.
Referring to fig. 8, a chip 1000 includes the level shift circuit 100 described above.
According to the chip provided by the embodiment of the invention, the level conversion circuit is adopted, and a signal compression protection structure is adopted, so that the unipolar large swing of an input signal can be realized, and the wider signal level input application is met; by adopting a current differential input structure of a substrate bias structure, the low-power-consumption fine control of a level conversion threshold can be realized, and the power consumption in the conversion process, especially the power consumption in the high-voltage conversion process, can be reduced; through the current comparison, the high-voltage protection and the active amplification structure, the level of the output signal can be flexibly configured according to the requirement, and the large swing amplitude of the output signal is met, so that the level conversion function of low power consumption and large swing amplitude is realized, the applicability of the chip is improved, and the power consumption of the chip is reduced.
In some embodiments, an electronic device is presented.
Referring to fig. 9, an electronic device 10000 includes the aforementioned chip 1000.
According to the embodiment of the invention, the level conversion circuit is adopted, and a signal compression protection structure is adopted, so that the unipolar large swing of an input signal can be realized, and the wider signal level input application is met; by adopting a current differential input structure of a substrate bias structure, the low-power-consumption fine control of a level conversion threshold can be realized, and the power consumption in the conversion process, especially the power consumption in the high-voltage conversion process, can be reduced; through the current comparison, the high-voltage protection and the active amplification structure, the level of the output signal can be flexibly configured according to the requirement, and the large swing amplitude of the output signal is met, so that the level conversion function with low power consumption and large swing amplitude is realized, the applicability of the electronic equipment is improved, and the power consumption of the electronic equipment is reduced.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being permanently connected, detachably connected, or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (15)
1. A level shift circuit, comprising:
the input unit is connected with the signal input end and used for carrying out voltage limiting processing on an input signal of the signal input end to obtain a first voltage;
the substrate bias conversion unit is connected with the input unit and is used for generating a first current and a second current based on different substrate bias effects under the action of the first voltage;
the current mirror image unit is connected with the substrate bias conversion unit and is used for comparing the first current with the second current;
and the output voltage conversion unit is connected with the current mirror image unit and the signal output end, and is used for performing voltage conversion on the comparison result to obtain an output signal and outputting the output signal through the signal output end.
2. The level shift circuit according to claim 1, wherein the input unit comprises:
the amplitude limiting circuit is connected with the signal input end and is used for carrying out voltage amplitude limiting processing on the input signal to obtain a second voltage;
and the voltage division circuit is connected with the amplitude limiting circuit and is used for carrying out voltage division processing on the second voltage to obtain the first voltage.
3. The level shift circuit of claim 2, wherein the clipping circuit comprises:
one end of the first resistor is connected with the signal input end;
and the cathode of the voltage stabilizing diode is connected with the other end of the first resistor and forms a first node, and the anode of the voltage stabilizing diode is grounded.
4. The level shifter circuit of claim 3, wherein the voltage divider circuit comprises:
one end of the second resistor is connected with the first node;
and the control electrode and the first electrode of the first switch tube are respectively connected with the other end of the second resistor and form a second node, the second electrode of the first switch tube is grounded, and the second node is connected with the substrate bias conversion unit.
5. The level shifter circuit according to any of claims 1-4, wherein the substrate bias shifting unit comprises:
a control electrode of the second switching tube is connected with the input unit, a first electrode of the second switching tube is connected with the current mirror image unit, and a substrate of the second switching tube is grounded;
a control electrode of the third switching tube is connected with a control electrode of the second switching tube, a first electrode of the third switching tube is connected with the current mirror unit, a second electrode of the third switching tube, a substrate of the third switching tube and the second electrode of the second switching tube are connected and a third node is formed;
and one end of the third resistor is connected with the third node, and the other end of the third resistor is grounded.
6. The level shift circuit of claim 5, wherein the current mirror unit comprises:
a control electrode and a first electrode of the fourth switching tube are respectively connected with a first electrode of the second switching tube, and a second electrode of the fourth switching tube is connected with a power supply;
and a control electrode of the fifth switch tube is connected with a control electrode of the fourth switch tube, a first electrode of the fifth switch tube is connected with a first electrode of the third switch tube and a fourth node is formed, a second electrode of the fifth switch tube is connected with the power supply, and the fourth node is connected with the output voltage conversion unit.
7. The level shift circuit of claim 6, wherein the current mirror unit further comprises:
and the clamping circuit is arranged between the first pole of the fourth switching tube and the first pole of the fifth switching tube and is used for clamping the voltage of the fourth node.
8. The level shift circuit of claim 7, wherein the clamp circuit comprises:
and the control electrode and the first electrode of the sixth switching tube are connected with the fourth node, and the second electrode of the sixth switching tube is connected with the first electrode of the fourth switching tube.
9. The circuit of claim 6, further comprising:
and the isolation unit is arranged between the substrate bias conversion unit and the current mirror image unit and is used for carrying out isolation protection on the substrate bias conversion unit.
10. The level shift circuit of claim 9, wherein the isolation unit comprises:
the voltage division circuit is used for carrying out voltage division processing on the power supply to obtain a third voltage;
and the isolation circuit is connected with the voltage division circuit and is used for carrying out isolation protection on the substrate bias conversion unit under the action of the third voltage.
11. The level shift circuit of claim 10, wherein the voltage divider circuit comprises:
one end of the fourth resistor is connected with the power supply;
a control electrode and a first electrode of the seventh switching tube are respectively connected with the other end of the fourth resistor and form a fifth node, and the fifth node is connected with the isolation circuit;
and a control electrode and a first electrode of the eighth switch tube are respectively connected with a second electrode of the seventh switch tube, and the second electrode of the eighth switch tube is grounded.
12. The level shift circuit of claim 10, wherein the isolation circuit comprises:
a control electrode of the ninth switching tube is connected with the voltage dividing circuit, a first electrode of the ninth switching tube is connected with a first electrode of the fourth switching tube, and a second electrode of the ninth switching tube is connected with a first electrode of the second switching tube;
a tenth switching tube, a control electrode of the tenth switching tube is connected to the control electrode of the ninth switching tube, a first electrode of the tenth switching tube is connected to the first electrode of the fifth switching tube, and a second electrode of the tenth switching tube is connected to the first electrode of the third switching tube.
13. The level shift circuit according to any of claims 1-4, wherein the output voltage conversion unit comprises:
a control electrode of the eleventh switch tube is connected with the current mirror unit, a first electrode of the eleventh switch tube is connected with the signal output end, and a second electrode of the eleventh switch tube is connected with a power supply;
one end of the fifth resistor is connected with the first pole of the eleventh switching tube, and the other end of the fifth resistor is connected with the reference ground.
14. A chip comprising a level shifting circuit according to any of claims 1-13.
15. An electronic device, characterized in that it comprises a chip according to claim 14.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210573949.5A CN114978146A (en) | 2022-05-24 | 2022-05-24 | Level conversion circuit, chip and electronic equipment |
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| CN202210573949.5A CN114978146A (en) | 2022-05-24 | 2022-05-24 | Level conversion circuit, chip and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116660614A (en) * | 2023-08-01 | 2023-08-29 | 苏州贝克微电子股份有限公司 | Voltage detection circuit for improving switching speed |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116660614A (en) * | 2023-08-01 | 2023-08-29 | 苏州贝克微电子股份有限公司 | Voltage detection circuit for improving switching speed |
| CN116660614B (en) * | 2023-08-01 | 2023-09-22 | 苏州贝克微电子股份有限公司 | Voltage detection circuit for improving switching speed |
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