CN114977200A

CN114977200A - Quick thyristor turn-off method, electronic equipment and storage medium

Info

Publication number: CN114977200A
Application number: CN202210924385.5A
Authority: CN
Inventors: 秦玲; 宋国伟; 李新娟; 陈小佳
Original assignee: Dongfang Power Beijing Technology Co ltd
Current assignee: Dongfang Power Beijing Technology Co ltd
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2022-08-30
Anticipated expiration: 2042-08-03
Also published as: CN114977200B

Abstract

The application provides a rapid thyristor turn-off method, electronic equipment and a storage medium, wherein the method comprises the following steps: stopping sending each gate-level driving signal pulse; calculating to obtain a first comparison value of the first IGBT group, a second comparison value of the second IGBT group and a third comparison value of the third IGBT group based on an SPWM algorithm; and correcting the first comparison value, the second comparison value and the third comparison value according to the target back pressure turn-off value, the voltage value of the first input end on the power grid side, the voltage value of the second input end on the power grid side, the voltage value of the third input end on the power grid side, the first current value detected by the first current transformer, the second current value detected by the second current transformer and the third current value detected by the third current transformer. The thyristor can be applied to the voltage restorer circuit with the isolation transformer, and the thyristor in the voltage restorer circuit with the isolation transformer is turned off in advance of natural turn-off time when the voltage sag problem occurs in a power grid.

Description

Quick thyristor turn-off method, electronic equipment and storage medium

Technical Field

The present disclosure relates to the field of power electronics technologies, and in particular, to a method for quickly turning off a thyristor, an electronic device, and a storage medium.

Background

The dynamic voltage restorer (circuit) is a preferable product for solving the problem of power grid voltage sag, and the thyristor in the dynamic voltage restorer (circuit) can be turned off in advance of the self natural turn-off time by sending a Pulse Width Modulation (pwm) comparison value of an Insulated Gate Bipolar Transistor (IGBT) obtained based on a Sinusoidal Pulse Width Modulation (spwm) algorithm to the IGBT in the dynamic voltage restorer (circuit) so as to enable the IGBT to execute the self switching period according to the received pwm comparison value.

However, the above method cannot be directly applied to a dynamic voltage restorer circuit with an isolation transformer, because the isolation transformer will generate a coupling effect on the voltage at the output end of the power grid side, so that when the IGBT directly executes its own switching cycle according to the pwm comparison value obtained based on the spwm algorithm, it cannot be ensured that the thyristor achieves its own condition of turning off in advance (i.e., it cannot be ensured that the thyristor is turned off in advance of its own natural turn-off time).

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method for rapidly turning off a thyristor, an electronic device, and a storage medium, which can be applied to a voltage restorer circuit with an isolation transformer, so that a thyristor in the voltage restorer circuit with the isolation transformer is turned off in advance of a natural turn-off time when a voltage sag problem occurs in a power grid.

In a first aspect, an embodiment of the present application provides a method for rapidly turning off a thyristor, which is applied to a voltage restorer circuit, where the voltage restorer circuit includes: the power supply comprises a first thyristor, a second thyristor, a third thyristor, a first current transformer, a second current transformer, a third current transformer, an isolation transformer, a first IGBT, a second IGBT, a third IGBT, a fourth IGBT, a fifth IGBT, a sixth IGBT, a first capacitor, a second capacitor and a third capacitor; a first end of the first thyristor is electrically connected to a first input end on a power grid side, a second end of the first thyristor is electrically connected to a first output end on a load side through the first current transformer, a first end of the second thyristor is electrically connected to a second input end on the power grid side, a second end of the second thyristor is electrically connected to a second output end on the load side through the second current transformer, a first end of the third thyristor is electrically connected to a third input end on the power grid side, a second end of the third thyristor is electrically connected to a third output end on the load side through the third current transformer, a fourth input end on the power grid side is electrically connected to a fourth output end on the load side, a collector electrode of the first IGBT is electrically connected to a collector electrode of the third IGBT, and an emitter electrode of the first IGBT is electrically connected to a collector electrode of the second IGBT, the emitter of the second IGBT is electrically connected with the emitter of the fourth IGBT, the emitter of the fourth IGBT is also electrically connected with the emitter of the sixth IGBT, the collector of the third IGBT is also electrically connected with the collector of the fifth IGBT, the emitter of the third IGBT is electrically connected with the collector of the fourth IGBT, the emitter of the fifth IGBT is electrically connected with the collector of the sixth IGBT, the emitter of the first IGBT is also electrically connected with the first end of the first target side of the isolation transformer, the first target side of the isolation transformer is the primary side or the secondary side of the isolation transformer, the emitter of the third IGBT is also electrically connected with the second end of the first target side of the isolation transformer, the emitter of the fifth IGBT is also electrically connected with the third end of the first target side of the isolation transformer, and the first end of the second target side of the isolation transformer is electrically connected with the first output end of the load side, if the first target side of the isolation transformer is the primary side of the isolation transformer, the second target side of the isolation transformer is the secondary side of the isolation transformer, if the first target side of the isolation transformer is the secondary side of the isolation transformer, the second target side of the isolation transformer is the primary side of the isolation transformer, the second end of the second target side of the isolation transformer is electrically connected with the second output end of the load side, the third end of the second target side of the isolation transformer is electrically connected with the third output end of the load side, the fourth end of the second target side of the isolation transformer is electrically connected with the fourth output end of the load side, the first end of the first capacitor is electrically connected with the first end of the second target side of the isolation transformer, and the second end of the first capacitor is electrically connected with the fourth end of the second target side of the isolation transformer, a first end of the second capacitor is electrically connected with a second end of a second target side of the isolation transformer, a second end of the second capacitor is electrically connected with a second end of the first capacitor, a first end of the third capacitor is electrically connected with a third end of the second target side of the isolation transformer, a second end of the third capacitor is electrically connected with a second end of the second capacitor, and when no voltage sag problem occurs on the grid side, gate-level driving signal pulses are sent to the first thyristor, the second thyristor and the third thyristor so as to enable the first thyristor, the second thyristor and the third thyristor to be in a conducting state; when the voltage sag problem occurs on the power grid side, the method comprises the following steps:

s101, stopping sending each gate-level driving signal pulse;

s102, calculating and obtaining a first pwm initial comparison value of a first IGBT group, a second pwm initial comparison value of a second IGBT group and a third pwm initial comparison value of a third IGBT group based on an SPWM algorithm, wherein the first IGBT group comprises: the first IGBT and the second IGBT, the second IGBT group includes: the third IGBT and the fourth IGBT, the third IGBT group includes: the fifth IGBT and the sixth IGBT;

s103, according to a target back-pressure turn-off value, a current voltage value of the first input end of the power grid side, a current voltage value of the second input end of the power grid side, a current voltage value of the third input end of the power grid side, a current first current value detected by the first current transformer, a current second current value detected by the second current transformer and a current third current value detected by the third current transformer, correcting a latest first pwm initial comparison value, a latest second pwm initial comparison value and a latest third pwm initial comparison value to obtain a first pwm corrected comparison value corresponding to the latest first pwm initial comparison value, a second pwm corrected comparison value corresponding to the latest second pwm initial comparison value and a third pwm corrected comparison value corresponding to the latest third pwm initial comparison value, wherein the target back-pressure turn-off value is the back-pressure turn-off value of the first thyristor, Either one of a back-voltage turn-off value of the second thyristor and a back-voltage turn-off value of the third thyristor, wherein the first IGBT and the second IGBT, when executing a current preset switching cycle of themselves in accordance with the first pwm correction comparison value and the first current value is not 0, can make a first target difference value, whose positive or negative is opposite to that of the first current value, the first target difference value being a difference value between a current voltage value of the first output terminal on the load side and a current voltage value of the first input terminal on the grid side, the third IGBT and the fourth IGBT, when executing a current preset switching cycle of themselves in accordance with the second pwm correction comparison value and the second current value is not 0, can make a second target difference value, whose positive or negative is opposite to that of the second current value, the second target difference value being a difference value between a current voltage value of the second output terminal on the load side and a current voltage value of the second input terminal on the grid side, when the fifth IGBT and the sixth IGBT execute their current preset switching cycles according to the third pwm correction comparison value and the third current value is not 0, the third target difference value is opposite in polarity to the third current value, where the third target difference value is the difference between the current voltage value of the third output terminal on the load side and the current voltage value of the third input terminal on the power grid side;

and S104, sending the first pwm corrected comparison value to the first IGBT group, so that the first IGBT and the second IGBT execute their current preset switching cycles according to the first pwm corrected comparison value, sending the second pwm corrected comparison value to the second IGBT group, so that the third IGBT and the fourth IGBT execute their current preset switching cycles according to the second pwm corrected comparison value, and sending the third pwm corrected comparison value to the third IGBT group, so that the fifth IGBT and the sixth IGBT execute their current preset switching cycles according to the third pwm corrected comparison value, thereby turning off the first thyristor, the second thyristor, and the third thyristor earlier than their natural turn-off times.

In one possible implementation, step S103 includes:

and correcting a latest first pwm initial comparison value, a latest second pwm initial comparison value and a latest third pwm initial comparison value according to the target back-pressure turn-off value, the angle of the voltage of a target input end, the current voltage value of the first input end on the power grid side, the current voltage value of the second input end on the power grid side, the current value of the third input end on the power grid side, the first current value, the second current value and the third current value to obtain the first pwm corrected comparison value, the second pwm corrected comparison value and the third pwm corrected comparison value, wherein the target input end is any one of the first input end on the power grid side, the second input end on the power grid side and the third input end on the power grid side.

In a possible embodiment, the isolation transformer is a DY isolation transformer, and the target input terminal is a first input terminal on the power grid side; correcting the latest first pwm initial comparison value, the latest second pwm initial comparison value and the latest third pwm initial comparison value according to the target back-voltage turn-off value, the angle of the voltage at the target input end, the current voltage value at the first input end on the power grid side, the current voltage value at the second input end on the power grid side, the first current value, the second current value and the third current value to obtain the first pwm corrected comparison value, the second pwm corrected comparison value and the third pwm corrected comparison value, including:

s301, judging whether the current voltage value of the first input end of the power grid side is larger than 0 and the first current value is smaller than 0, if so, executing a step S302, and if not, executing a step S305;

s302, judging whether the current angle of the voltage of the first input end on the power grid side is between 0 and 90 degrees, if so, executing a step S303, and if not, executing a step S304;

s303, subtracting the target back-pressure cutoff value from the latest second pwm initial comparison value to obtain a first value, taking the first value as the latest first pwm initial comparison value, adding the latest third pwm initial comparison value to the target back-pressure cutoff value to obtain a second value, and taking the second value as the latest third pwm initial comparison value, and performing step S305;

s304, adding the latest first pwm initial comparison value to the target back-pressure turn-off value to obtain a third value, and using the third value as a latest second pwm initial comparison value, and subtracting the target back-pressure turn-off value from the latest third pwm initial comparison value to obtain a fourth value, and using the fourth value as a latest third pwm initial comparison value, and performing step S305;

s305, judging whether the current voltage value of the third input end on the power grid side is smaller than 0 and the third current value is larger than 0, if so, executing a step S306, and if not, executing a step S309;

s306, judging whether the angle of the voltage of the first input end of the current power grid side is between 60 degrees and 150 degrees, if so, executing a step S307, otherwise, executing a step S308;

s307, adding the latest first pwm initial comparison value to the target back pressure turn-off value to obtain a fifth numerical value, and using the fifth numerical value as a latest third pwm initial comparison value, and subtracting the target back pressure turn-off value from the latest second pwm initial comparison value to obtain a sixth numerical value, and using the sixth numerical value as a latest second pwm initial comparison value, and performing step S309;

s308, subtracting the target back-pressure turn-off value from the latest third pwm initial comparison value to obtain a seventh value, taking the seventh value as the latest first pwm initial comparison value, adding the latest second pwm initial comparison value to the target back-pressure turn-off value to obtain an eighth value, and taking the eighth value as the latest second pwm initial comparison value, and performing step S309;

s309, judging whether the current voltage value of the second input end of the power grid side is larger than 0 and the second current value is smaller than 0, if so, executing a step S310, and if not, executing a step S313;

s310, judging whether the current angle of the voltage of the first input end on the power grid side is between 120 degrees and 210 degrees, if so, executing a step S311, otherwise, executing a step S312;

s311, subtracting the target back-pressure turn-off value from the latest third pwm initial comparison value to obtain a ninth value, taking the ninth value as the latest second pwm initial comparison value, adding the latest first pwm initial comparison value to the target back-pressure turn-off value to obtain a tenth value, taking the tenth value as the latest first pwm initial comparison value, and performing step S313;

s312, adding the latest second pwm initial comparison value to the target back pressure off value to obtain an eleventh value, and using the eleventh value as the latest third pwm initial comparison value, and subtracting the target back pressure off value from the latest first pwm initial comparison value to obtain a twelfth value, and using the twelfth value as the latest first pwm initial comparison value, and performing step S313;

s313, determining whether the current voltage value of the first input terminal on the power grid side is less than 0 and the first current value is greater than 0, if yes, performing step S314, and if no, performing step S317;

s314, judging whether the angle of the voltage of the first input end of the current power grid side is between 180 degrees and 270 degrees, if so, executing a step S315, and if not, executing a step S316;

s315, adding the latest second pwm initial comparison value to the target back pressure off value to obtain a thirteenth value, and using the thirteenth value as the latest first pwm initial comparison value, and subtracting the target back pressure off value from the latest third pwm initial comparison value to obtain a fourteenth value, and using the fourteenth value as the latest third pwm initial comparison value, and performing step S317;

s316, subtracting the target back-pressure turn-off value from the latest first pwm initial comparison value to obtain a fifteenth value, and taking the fifteenth value as the latest second pwm initial comparison value, and adding the latest third pwm initial comparison value to the target back-pressure turn-off value to obtain a sixteenth value, and taking the sixteenth value as the latest third pwm initial comparison value, and performing step S317;

s317, determining whether the current voltage value of the third input terminal on the power grid side is greater than 0 and the third current value is less than 0, if yes, performing step S318, and if no, performing step S321;

s318, determining whether the current angle of the voltage at the first input end of the power grid side is 240 degrees to 330 degrees, if so, performing step S319, and if not, performing step S320;

s319, subtracting the target back-pressure turn-off value from the latest first pwm initial comparison value to obtain a seventeenth value, and taking the seventeenth value as the latest third pwm initial comparison value, and adding the latest second pwm initial comparison value to the target back-pressure turn-off value to obtain an eighteenth value, and taking the eighteenth value as the latest second pwm initial comparison value, and performing step S321;

s320, adding the latest first pwm initial comparison value to the target back pressure turn-off value to obtain a nineteenth value, and using the nineteenth value as the latest first pwm initial comparison value, and subtracting the target back pressure turn-off value from the latest second pwm initial comparison value to obtain a twentieth value, and using the twentieth value as the latest second pwm initial comparison value, and performing step S321;

s321, determining whether a current voltage value of a second input terminal of the power grid side is less than 0 and the second current value is greater than 0, if yes, performing step S322, and if no, performing step S325;

s322, judging that the angle of the voltage of the first input end of the current power grid side is between 300 and 360 degrees or between 0 and 30 degrees, if so, executing a step S323, and if not, executing a step S324;

s323, adding the latest third pwm initial comparison value to the target back pressure turn-off value to obtain a twenty-first value, taking the twenty-first value as the latest second pwm initial comparison value, subtracting the target back pressure turn-off value from the latest first pwm initial comparison value to obtain a twenty-second value, taking the twenty-second value as the latest first pwm initial comparison value, and performing step S325;

s324, subtracting the target back-pressure turn-off value from the latest second pwm initial comparison value to obtain a twenty-third value, taking the twenty-third value as the latest third pwm initial comparison value, adding the latest first pwm initial comparison value to the target back-pressure turn-off value to obtain a twenty-fourth value, taking the twenty-fourth value as the latest first pwm initial comparison value, and performing step S325;

s325, multiplying the latest first pwm initial comparison value by a first preset value to obtain a twenty-fifth value, and taking the twenty-fifth value as the latest first pwm initial comparison value, and multiplying the latest second pwm initial comparison value by a second preset value to obtain a twenty-sixth value, and taking the twenty-sixth value as the latest second pwm initial comparison value, and multiplying the latest third pwm initial comparison value by a third preset value to obtain a twenty-seventh value, and taking the twenty-seventh value as the latest third pwm initial comparison value, and performing step S326, where the first preset value is greater than 1, the second preset value is greater than 1, and the third preset value is greater than 1;

s326, determining whether the first current value is 0, the second current value is not 0, and the third current value is not 0, if yes, performing step S327, otherwise, performing step S328;

s327, subtracting a twenty-eighth value from the latest first pwm initial comparison value to obtain a twenty-ninth value, and using the twenty-ninth value as the latest first pwm initial comparison value, and adding a thirty-second value to the latest second pwm initial comparison value to obtain a thirty-first value, and using the thirty-first value as the latest second pwm initial comparison value, and executing step S328, wherein the twenty-eighth value is a product of the target backpressure shutdown value and a thirty-twelfth value, if the third current value is greater than 0, the thirty-twelfth value is 1, if the third current value is less than 0, the thirty-twelfth value is-1, the thirty-third value is a product of the target backpressure shutdown value and a thirty-third value, if the second current value is greater than 0, the thirty-third value is 1, and if the second current value is less than 0, the thirty-third value is-1;

s328, determining whether the second current value is 0, the first current value is not 0, and the third current value is not 0, if yes, performing step S329, otherwise, performing step S330;

s329, subtracting a thirty-fourth value from the latest second pwm initial comparison value to obtain a thirty-fifth value, taking the thirty-fifth value as the latest second pwm initial comparison value, adding a thirty-sixth value to the latest third pwm initial comparison value to obtain a thirty-seventh value, and taking the thirty-seventh value as the latest third pwm initial comparison value, and performing step S330, where the thirty-fourth value is a product of the target back-pressure off-value and a thirty-eighth value, if the first current value is greater than 0, the thirty-eighth value is 1, if the first current value is less than 0, the thirty-eighth value is-1, the thirty-sixth value is a product of the target back-pressure off-value and a thirty-ninth value, and if the third current value is greater than 0, the thirty-ninth value is 1, if the third current value is less than 0, the thirty-ninth value is-1;

s330, determining whether the third current value is 0, the first current value is not 0, and the second current value is not 0, if yes, performing step S331, otherwise, performing step S332;

s331, subtracting a forty-first value from a latest third pwm initial comparison value to obtain a forty-first value, and using the forty-first value as a latest third pwm initial comparison value, and adding a forty-third value to the latest first pwm initial comparison value to obtain a forty-third value, and using the forty-third value as a latest first pwm initial comparison value, and performing step S332, where the forty-third value is a product of the target backpressure shutdown value and a forty-fourth value, if the second current value is greater than 0, the forty-fourth value is 1, if the second current value is less than 0, the forty-fourth value is-1, if the fourth twelve value is a product of the target backpressure shutdown value and a forty-fifth value, if the first current value is greater than 0, the forty-fifth value is 1, if the third current value is less than 0, said forty-fifth value is-1;

s332, determining whether the first current value is 0 and the second current value is 0, if yes, performing step S333, and if no, performing step S334;

s333, subtracting a forty-sixth numerical value from the latest first pwm initial comparison value to obtain a forty-seventh numerical value, taking the forty-seventh numerical value as the latest first pwm initial comparison value, adding the latest third pwm initial comparison value to the forty-sixth numerical value to obtain a forty-eighth numerical value, and taking the forty-eighth numerical value as the latest third pwm initial comparison value, and executing step S334, where the forty-sixth numerical value is a product of the target backpressure shut-off value and a forty-ninth numerical value, if the third current value is greater than 0, the forty-ninth numerical value is 1, and if the third current value is less than 0, the forty-ninth numerical value is-1;

s334, determining whether the second current value is 0 and the third current value is 0, if yes, performing step S335, and if no, performing step S336;

s335, subtracting a fifty-first value from the latest second pwm initial comparison value to obtain a fifty-first value, and using the fifty-first value as the latest second pwm initial comparison value, and adding the fifty-first value to the latest first pwm initial comparison value to obtain a fifty-second value, and using the fifty-second value as the latest first pwm initial comparison value, and performing step S336, wherein the fifty-second value is a product of the target backpressure shutdown value and a fifty-third value, and if the first current value is greater than 0, the fifty-third value is 1, and if the first current value is less than 0, the fifty-third value is-1;

s336, determining whether the first current value is 0 and the third current value is 0, if so, executing step S337, otherwise, taking the latest first pwm initial comparison value as the first pwm corrected comparison value, taking the latest second pwm initial comparison value as the second pwm corrected comparison value, and taking the latest third pwm initial comparison value as the third pwm corrected comparison value;

s337, subtracting a fifty-fourth value from a latest third pwm initial comparison value to obtain a fifty-fifth value, and taking the fifty-fifth value as a latest third pwm initial comparison value, and adding the fifty-fourth value to the latest second pwm initial comparison value to obtain a fifty-sixth value, and taking the fifty-sixth value as a latest second pwm initial comparison value, and taking a latest first pwm initial comparison value as the first pwm corrected comparison value, and taking the latest second pwm initial comparison value as the second pwm corrected comparison value, and taking the latest third pwm initial comparison value as the fifty-third pwm corrected comparison value, wherein the fourth value is a product of the target backpressure-cutoff value and a fifty-seventh value, and if the second amperage value is greater than 0, the seventh fifty-fifth value is 1, and if the second amperage value is less than 0, the fifty-seventh numerical value is-1.

In a possible embodiment, the preset switching period of the first IGBT, the preset switching period of the second IGBT, the preset switching period of the third IGBT, the preset switching period of the fourth IGBT, the preset switching period of the fifth IGBT and the preset switching period of the sixth IGBT are all the same; after step S104, the method further comprises:

and repeatedly executing the step S102 to the step S104 every other preset switching period of the first IGBT until the first current value, the second current value and the third current value are all 0.

In one possible implementation, the voltage restorer circuit further includes: a fourth capacitor, a fifth capacitor and a resistor;

the first end of the fourth capacitor is electrically connected with the first end of the resistor;

a second end of the fourth capacitor is electrically connected with a second end of the resistor;

the first end of the fourth capacitor is also electrically connected with the collector electrode of the first IGBT;

the second end of the fourth capacitor is also electrically connected with the emitter of the second IGBT;

the first end of the fifth capacitor is electrically connected with the first end of the resistor;

and the second end of the fifth capacitor is electrically connected with the second end of the resistor.

In one possible embodiment, the voltage restorer circuit further includes: a contactor and a buffer circuit;

the first end of the contactor and the buffer circuit is electrically connected with the first end of the second target side of the isolation transformer;

the second ends of the contactor and the buffer circuit are electrically connected with the second end of the second target side of the isolation transformer;

the third end of the contactor and the buffer circuit is electrically connected with the third end of the second target side of the isolation transformer;

the fourth end of the contactor and buffer circuit is electrically connected with the fourth end of the second target side of the isolation transformer;

the fifth end of the contactor and the buffer circuit is electrically connected with the first output end of the load side;

the sixth end of the contactor and the buffer circuit is electrically connected with the second output end of the load side;

the seventh end of the contactor and buffer circuit is electrically connected with the third output end of the load side;

and the eighth end of the contactor and buffer circuit is electrically connected with the fourth output end of the load side.

In one possible embodiment, the fifth capacitor is a super capacitor.

In a second aspect, an embodiment of the present application further provides an electronic device, including: the thyristor fast turn-off method comprises a processor, a storage medium and a bus, wherein the storage medium stores machine-readable instructions executable by the processor, when an electronic device runs, the processor and the storage medium communicate through the bus, and the processor executes the machine-readable instructions to execute the steps of the thyristor fast turn-off method of the first aspect.

In a third aspect, the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program performs the steps of the method for rapidly turning off a thyristor according to any one of the first aspect.

The method for rapidly turning off the thyristor, the electronic device and the storage medium provided by the embodiment of the application can be applied to a voltage restorer circuit with an isolation transformer, and the thyristor in the voltage restorer circuit with the isolation transformer is turned off in advance of natural turn-off time when a voltage sag problem occurs in a power grid.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 illustrates a schematic structural diagram of a voltage restorer circuit provided in an embodiment of the present application;

fig. 2 is a schematic diagram illustrating a structure of another voltage restorer circuit provided in an embodiment of the present application;

fig. 3 is a schematic diagram illustrating a structure of another voltage restorer circuit provided in an embodiment of the present application;

fig. 4 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.

Description of the reference numerals: 1-a first thyristor; 2-a second thyristor; 3-a third thyristor; 4-a first current transformer; 5-a second current transformer; 6-a third current transformer; 7-an isolation transformer; 8-a first IGBT; 9-a second IGBT; 10-a third IGBT; 11-a fourth IGBT; 12-fifth IGBT; 13-sixth IGBT; 14-a first capacitance; 15-a second capacitance; 16-a third capacitance; 17-grid side; 18-load side; 19-a fourth capacitance; 20-a fifth capacitance; 21-resistance; 22-contactor and snubber circuit.

Detailed Description

In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are only for illustration and description purposes and are not used to limit the protection scope of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.

In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that in the embodiments of the present application, the term "comprising" is used to indicate the presence of the features stated hereinafter, but does not exclude the addition of further features.

For the convenience of understanding the present embodiment, a method for rapidly turning off a thyristor, an electronic device and a storage medium provided in the embodiments of the present application are described in detail.

The method for rapidly turning off the thyristor provided by the embodiment of the application is applied to a voltage restorer circuit, and is shown in fig. 1, which is a schematic structural diagram of the voltage restorer circuit provided by the embodiment of the application, and the voltage restorer circuit includes: the circuit comprises a first thyristor 1, a second thyristor 2, a third thyristor 3, a first current transformer 4, a second current transformer 5, a third current transformer 6, an isolation transformer 7, a first IGBT8, a second IGBT9, a third IGBT10, a fourth IGBT11, a fifth IGBT12, a sixth IGBT13, a first capacitor 14, a second capacitor 15 and a third capacitor 16; a first end of the first thyristor 1 is electrically connected to a first input end of a grid side 17, a second end of the first thyristor 1 is electrically connected to a first output end of a load side 18 through the first current transformer 4, a first end of the second thyristor 2 is electrically connected to a second input end of the grid side 17, a second end of the second thyristor 2 is electrically connected to a second output end of the load side 18 through the second current transformer 5, a first end of the third thyristor 3 is electrically connected to a third input end of the grid side 17, a second end of the third thyristor 3 is electrically connected to a third output end of the load side 18 through the third current transformer 6, a fourth input end of the grid side 17 is electrically connected to a fourth output end of the load side 18, and a collector electrode of the first IGBT8 is electrically connected to a collector electrode of the third IGBT10, the emitter of the first IGBT8 is electrically connected to the collector of the second IGBT9, the emitter of the second IGBT9 is electrically connected to the emitter of the fourth IGBT11, the emitter of the fourth IGBT11 is also electrically connected to the emitter of the sixth IGBT13, the collector of the third IGBT10 is also electrically connected to the collector of the fifth IGBT12, the emitter of the third IGBT10 is electrically connected to the collector of the fourth IGBT11, the emitter of the fifth IGBT12 is electrically connected to the collector of the sixth IGBT13, the emitter of the first IGBT8 is also electrically connected to the first end of the first target side of the isolation transformer 7, the first target side of the isolation transformer 7 is the primary side or the secondary side of the isolation transformer 7, the emitter of the third IGBT10 is also electrically connected to the second end of the first target side of the isolation transformer 7, the emitter of the fifth IGBT12 is also electrically connected to the third end of the first target side of the isolation transformer 7, a first end of the second target side of the isolation transformer 7 is electrically connected to a first output end of the load side 18, if the first target side of the isolation transformer 7 is the primary side of the isolation transformer 7, the second target side of the isolation transformer 7 is the secondary side of the isolation transformer 7, if the first target side of the isolation transformer 7 is the secondary side of the isolation transformer 7, the second target side of the isolation transformer 7 is the primary side of the isolation transformer 7, a second end of the second target side of the isolation transformer 7 is electrically connected to a second output end of the load side 18, a third end of the second target side of the isolation transformer 7 is electrically connected to a third output end of the load side 18, a fourth end of the second target side of the isolation transformer 7 is electrically connected to a fourth output end of the load side 18, a first end of the first capacitor 14 is electrically connected to a first end of the second target side of the isolation transformer 7, a second end of the first capacitor 14 is electrically connected to a fourth end of the second target side of the isolation transformer 7, a first end of the second capacitor 15 is electrically connected to a second end of the second target side of the isolation transformer 7, a second end of the second capacitor 15 is electrically connected to a second end of the first capacitor 14, a first end of the third capacitor 16 is electrically connected to a third end of the second target side of the isolation transformer 7, a second end of the third capacitor 16 is electrically connected to a second end of the second capacitor 15, and when a voltage sag problem does not occur on the grid side 17, gate driving signal pulses are sent to the first thyristor 1, the second thyristor 2, and the third thyristor 3, so that the first thyristor 1, the second thyristor 2, and the third thyristor 3 are in a conducting state; when the voltage sag problem occurs on the grid side 17, the method comprises:

when no voltage sag problem occurs on the power grid side 17, a gate driving signal pulse may be sent to the first thyristor 1, the second thyristor 2, and the third thyristor 3 by the CPU to turn on the first thyristor 1, the second thyristor 2, and the third thyristor 3.

The isolation transformer 7 may be a DY isolation transformer or a DD isolation transformer or a YD isolation transformer or a YY isolation transformer, etc.

S101, stopping sending each gate-level driving signal pulse;

after the thyristor is stopped from sending the gate-level pulse driving signal, the thyristor can be automatically turned off when the natural turn-off time of the thyristor reaches.

Typically, the natural turn-off time of a thyristor is 6-10 ms.

S102, calculating and obtaining a first pwm initial comparison value of a first IGBT group, a second pwm initial comparison value of a second IGBT group and a third pwm initial comparison value of a third IGBT group based on an SPWM algorithm, wherein the first IGBT group comprises: the first IGBT8 and the second IGBT9, the second IGBT group comprising: the third IGBT10 and the fourth IGBT11, the third IGBT group comprising: the fifth IGBT12 and the sixth IGBT 13;

the combination of steps S101 to S102 is an existing method applied to a voltage restorer circuit without an isolation transformer, and is not modified and will not be described herein.

If the first pwm initial comparison value obtained in step S102 is directly sent to the first IGBT group, the second pwm initial comparison value is sent to the second IGBT group, and the third pwm initial comparison value is sent to the third IGBT group, since the isolation transformer can perform voltage coupling on the voltage of the first output terminal of the load side 18, the voltage of the second output terminal of the load side 18, and the voltage of the third output terminal of the load side 18, it is not possible to ensure that the first thyristor 1, the second thyristor 2, and the third thyristor 3 are turned off in advance of their own natural turn-off time.

S103, according to a target back-pressure turn-off value, a current voltage value of the first input end of the power grid side 17, a current voltage value of the second input end of the power grid side 17, a current voltage value of the third input end of the power grid side 17, a current detected first current value of the first current transformer 4, a current detected second current value of the second current transformer 5, and a current detected third current value of the third current transformer 6, correcting the latest first pwm initial comparison value, the latest second pwm initial comparison value, and the latest third pwm initial comparison value to obtain a first pwm corrected comparison value corresponding to the latest first pwm initial comparison value, a second pwm corrected comparison value corresponding to the latest second pwm initial comparison value, and a third pwm corrected comparison value corresponding to the latest third pwm initial comparison value, where the target back-pressure turn-off value is a turn-off value of the first thyristor 1, The first IGBT8 and the second IGBT9 may be configured to make a first target difference value opposite in polarity to a first current value when the first current value is not 0 and the current preset switching cycle is executed according to the first pwm corrected comparison value, the first target difference value is a difference value between a current voltage value of the first output terminal of the load side 18 and a current voltage value of the first input terminal of the grid side 17, the third IGBT10 and the fourth IGBT11 may be configured to make a second target difference value opposite in polarity to a second current value when the second current value is not 0 and the current preset switching cycle is executed according to the second pwm corrected comparison value, the second target difference value is a difference value between a current voltage value of the second output terminal of the load side 18 and a current voltage value of the second input terminal of the grid side 17 When the present preset switching cycle is executed according to the third pwm correction comparison value and the third current value is not 0, the fifth IGBT12 and the sixth IGBT13 may make the positive and negative of a third target difference value opposite to the positive and negative of the third current value, where the third target difference value is the difference value between the present voltage value of the third output terminal of the load side 18 and the present voltage value of the third input terminal of the grid side 17;

the back-voltage turn-off value of the thyristors depends on the maximum voltage magnitude that can be provided by the grid side 17, i.e. the back-voltage turn-off value of the first thyristor 1, the back-voltage turn-off value of the second thyristor 2 and the back-voltage turn-off value of the third thyristor 3 should be the same.

The first current value is not 0, that is, it means that the first thyristor 1 has not been turned off; the second current value is not 0, which means that the second thyristor 2 has not been turned off; if the third current value is not 0, it means that the third thyristor 3 is not turned off.

The fact that the positive and negative of the first target difference are opposite to the positive and negative of the first current value (that is, the first target difference is positive, the first current value is negative, or the first target difference is negative, the first current value is positive) means that a condition that enables the first thyristor 1 to be turned off in advance of the natural turn-off time of the first thyristor is achieved, which is an inherent characteristic of the thyristor, and when the positive and negative of the first target difference are opposite to the positive and negative of the first current value, the larger the absolute value of the first target difference is, the more the first thyristor 1 is turned off in advance of the natural turn-off time of the first thyristor;

the second thyristor 2 and the third thyristor 3 are the same, and will not be described again.

The latest first pwm initial comparison value, the latest second pwm initial comparison value and the latest third pwm initial comparison value are modified to (at least partially) eliminate the coupling influence of the isolation transformer 7 on the voltage value of the first output terminal of the load side 18, the voltage value of the second output terminal of the load side 18 and the voltage value of the third output terminal of the load side 18, so as not to influence the first thyristor 1, the second thyristor 2 and the third thyristor 3 to achieve a condition capable of being turned off earlier than their natural turn-off times.

S104, sending the first pwm corrected comparison value to the first IGBT group to enable the first IGBT8 and the second IGBT9 to execute their current preset switching cycles according to the first pwm corrected comparison value, sending the second pwm corrected comparison value to the second IGBT group to enable the third IGBT10 and the fourth IGBT11 to execute their current preset switching cycles according to the second pwm corrected comparison value, and sending the third pwm corrected comparison value to the third IGBT group to enable the fifth IGBT12 and the sixth IGBT13 to execute their current preset switching cycles according to the third pwm corrected comparison value, so as to enable the first thyristor 1, the second thyristor 2, and the third thyristor 3 to turn off earlier than their natural turn-off times.

As described in step S101, generally, the natural turn-off time of the thyristor is 6-10ms, and through the test, the turn-off time of the thyristor is reduced to about 1ms by the method of the present application, that is, the turn-off is realized by advancing the time by about 90% at most compared with the natural turn-off time.

In one possible implementation, step S103 includes:

and correcting a latest first pwm initial comparison value, a latest second pwm initial comparison value and a latest third pwm initial comparison value according to the target back-pressure turn-off value, the angle of the voltage of the target input end, the current voltage value of the first input end of the grid side 17, the current voltage value of the second input end of the grid side 17, the current voltage value of the third input end of the grid side 17, the first current value, the second current value and the third current value, so as to obtain the first pwm corrected comparison value, the second pwm corrected comparison value and the third pwm corrected comparison value, wherein the target input end is any one of the first input end of the grid side 17, the second input end of the grid side 17 and the third input end of the grid side 17.

In a possible embodiment, the isolation transformer 7 is a DY isolation transformer, and the target input is a first input of the grid side 17; correcting the latest first pwm initial comparison value, the latest second pwm initial comparison value and the latest third pwm initial comparison value according to the target back-voltage turn-off value, the angle of the voltage at the target input end, the current voltage value at the first input end of the grid side 17, the current voltage value at the second input end of the grid side 17, the first current value, the second current value and the third current value to obtain the first pwm corrected comparison value, the second pwm corrected comparison value and the third pwm corrected comparison value, including:

s301, determining whether a current voltage value of a first input terminal of the power grid side 17 is greater than 0 and the first current value is less than 0, if yes, performing step S302, and if no, performing step S305;

s302, determining whether the current angle of the voltage at the first input end of the power grid side 17 is between 0 and 90 degrees, if yes, performing step S303, and if no, performing step S304;

s303, subtracting the target back-pressure turn-off value from the latest second pwm initial comparison value to obtain a first value, and using the first value as the latest first pwm initial comparison value, and adding the latest third pwm initial comparison value to the target back-pressure turn-off value to obtain a second value, and using the second value as the latest third pwm initial comparison value, and performing step S305;

s304, adding the latest first pwm initial comparison value to the target back pressure turn-off value to obtain a third value, and using the third value as a latest second pwm initial comparison value, and subtracting the target back pressure turn-off value from the latest third pwm initial comparison value to obtain a fourth value, and using the fourth value as a latest third pwm initial comparison value, and performing step S305;

s305, determining whether a current voltage value of a third input terminal of the power grid side 17 is less than 0 and the third current value is greater than 0, if yes, performing step S306, and if no, performing step S309;

s306, determining whether the current angle of the voltage at the first input end of the power grid side 17 is between 60 degrees and 150 degrees, if so, executing step S307, and if not, executing step S308;

s308, subtracting the target back-pressure turn-off value from the latest third pwm initial comparison value to obtain a seventh value, taking the seventh value as the latest first pwm initial comparison value, adding the latest second pwm initial comparison value to the target back-pressure turn-off value to obtain an eighth value, taking the eighth value as the latest second pwm initial comparison value, and performing step S309;

s309, determining whether the current voltage value of the second input terminal of the power grid side 17 is greater than 0 and the second current value is less than 0, if yes, performing step S310, and if no, performing step S313;

s310, determining whether the current angle of the voltage at the first input end of the power grid side 17 is between 120 degrees and 210 degrees, if so, performing step S311, otherwise, performing step S312;

s313, determining whether a current voltage value of the first input terminal of the power grid side 17 is smaller than 0 and the first current value is greater than 0, if yes, performing step S314, and if no, performing step S317;

s314, determining whether the current angle of the voltage at the first input end of the power grid side 17 is between 180 degrees and 270 degrees, if so, performing step S315, and if not, performing step S316;

s317, determining whether the current voltage value of the third input terminal of the power grid side 17 is greater than 0 and the third current value is less than 0, if yes, performing step S318, and if no, performing step S321;

s318, determining whether the current angle of the voltage at the first input end of the power grid side 17 is 240 degrees to 330 degrees, if so, performing step S319, and if not, performing step S320;

s319, subtracting the target back-pressure off-value from the latest first pwm initial comparison value to obtain a seventeenth value, taking the seventeenth value as a latest third pwm initial comparison value, adding the latest second pwm initial comparison value to the target back-pressure off-value to obtain an eighteenth value, and taking the eighteenth value as a latest second pwm initial comparison value, and performing step S321;

s321, determining whether the current voltage value of the second input terminal of the power grid side 17 is less than 0 and the second current value is greater than 0, if yes, performing step S322, and if no, performing step S325;

s322, determining that the current angle of the voltage at the first input end of the power grid side 17 is between 300 degrees and 360 degrees or between 0 and 30 degrees, if yes, performing step S323, and if no, performing step S324;

preferably, the first preset value, the second preset value and the third preset value may all be 1.1.

s328, determining whether the second current value is 0, the first current value is not 0, and the third current value is not 0, if yes, performing step S329, and if no, performing step S330;

s329 subtracting a thirty-fourth value from the latest second pwm initial comparison value to obtain a thirty-fifth value, taking the thirty-fifth value as the latest third pwm initial comparison value, adding a thirty-sixth value to the latest third pwm initial comparison value to obtain a thirty-seventh value, and taking the thirty-seventh value as the latest second pwm initial comparison value, and executing step S330, wherein the thirty-fourth value is a product of the target back-pressure off value and a thirty-eighth value, if the first current value is greater than 0, the thirty-eighth value is 1, if the first current value is less than 0, the thirty-eighth value is-1, the thirty-sixth value is a product of the target back-pressure off value and a thirty-ninth value, and if the third current value is greater than 0, the thirty-ninth value is 1, if the third current value is less than 0, the thirty-ninth value is-1;

s337, subtracting a fifty-fourth value from the latest third pwm initial comparison value to obtain a fifty-fifth value, and using the fifty-fifth value as the latest third pwm initial comparison value, and adding the fifty-fourth value to the latest second pwm initial comparison value to obtain a fifty-sixth value, and using the fifty-sixth value as the latest second pwm initial comparison value, and using the latest first pwm initial comparison value as the first pwm corrected comparison value, and using the latest second pwm initial comparison value as the second pwm corrected comparison value, and using the latest third pwm initial comparison value as the third pwm corrected comparison value, wherein the fourth value is a product of the target backpressure shutdown value and a fifty-seventh value, and if the second current value is greater than 0, the fifty-fifth value is 1, and if the second current value is less than 0, the fifty-seventh numerical value is-1.

Specifically, in combination with steps S301 to S337, the present application provides a specific correction manner for the first pwm initial comparison value, the second pwm initial comparison value, and the third pwm initial comparison value when the isolation transformer 7 is a DY isolation transformer.

In one possible embodiment, the preset switching period of the first IGBT8, the preset switching period of the second IGBT9, the preset switching period of the third IGBT10, the preset switching period of the fourth IGBT11, the preset switching period of the fifth IGBT12, and the preset switching period of the sixth IGBT13 are all the same; after step S104, the method further comprises:

In the present application, each time the steps S102 to S104 are executed, the first thyristor 1, the second thyristor 2, and the third thyristor 3 are turned off in advance of their natural turn-off time.

After the first current value, the second current value and the third current value are all 0, that is, after the first thyristor 1, the second thyristor 2 and the third thyristor 3 are all turned off, the steps S102 to S104 are not required to be executed again.

Referring to fig. 2, a schematic structural diagram of another voltage restorer circuit provided in the embodiment of the present application is shown, and in a possible implementation manner, the voltage restorer circuit further includes: a fourth capacitor 19, a fifth capacitor 20, a resistor 21;

a first end of the fourth capacitor 19 is electrically connected with a first end of the resistor 21;

a second end of the fourth capacitor 19 is electrically connected with a second end of the resistor 21;

the first end of the fourth capacitor 19 is also electrically connected with the collector of the first IGBT 8;

the second end of the fourth capacitor 19 is also electrically connected with the emitter of the second IGBT 9;

a first end of the fifth capacitor 20 is electrically connected with a first end of the resistor 21;

a second terminal of the fifth capacitor 20 is electrically connected to a second terminal of the resistor 21.

Referring to fig. 3, a schematic structural diagram of another voltage restorer circuit provided in the embodiment of the present application is shown, in a possible implementation manner, the voltage restorer circuit further includes: a contactor and snubber circuit 22;

a first end of the contactor and snubber circuit 22 is electrically connected to a first end of the second target side of the isolation transformer 7;

a second end of the contactor and snubber circuit 22 is electrically connected to a second end of the second target side of the isolation transformer 7;

the third end of the contactor and snubber circuit 22 is electrically connected to the third end of the second target side of the isolation transformer 7;

the fourth end of the contactor and snubber circuit 22 is electrically connected to the fourth end of the second target side of the isolation transformer 7;

a fifth terminal of the contactor and snubber circuit 22 is electrically connected to a first output terminal of the load side 18;

a sixth terminal of the contactor and snubber circuit 22 is electrically connected to a second output terminal of the load side 18;

a seventh terminal of the contactor and snubber circuit 22 is electrically connected to a third output terminal of the load side 18;

an eighth terminal of the contactor and snubber circuit 22 is electrically connected to a fourth output terminal of the load side 18.

In one possible embodiment, the fifth capacitor 20 is a super capacitor.

The method for quickly turning off the thyristor provided by the embodiment of the application can be applied to a voltage restorer circuit with an isolation transformer, and the thyristor in the voltage restorer circuit with the isolation transformer is turned off in advance of natural turn-off time when a voltage sag problem occurs in a power grid.

Referring to fig. 4, an electronic device 400 provided in an embodiment of the present application includes: a processor 401, a memory 402 and a bus, wherein the memory 402 stores machine-readable instructions executable by the processor 401, when the electronic device is operated, the processor 401 and the memory 402 communicate with each other through the bus, and the processor 401 executes the machine-readable instructions to execute the steps of the method for rapidly shutting off the thyristor as described above.

Specifically, the memory 402 and the processor 401 may be general-purpose memory and processor, and are not limited in particular, and when the processor 401 runs a computer program stored in the memory 402, the method for rapidly turning off the thyristor may be performed.

Corresponding to the method for rapidly shutting down the thyristor, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program is executed by a processor to perform the steps of the method for rapidly shutting down the thyristor.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to corresponding processes in the method embodiments, and are not described in detail in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, and method may be implemented in other ways. The above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and there may be other divisions in actual implementation, and for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or modules through some communication interfaces, and may be in an electrical, mechanical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in software functional units and sold or used as a stand-alone product, may be stored in a non-transitory computer-readable storage medium executable by a processor. Based on such understanding, the technical solutions of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for rapidly turning off a thyristor, which is applied to a voltage restorer circuit, the voltage restorer circuit comprising: the power supply comprises a first thyristor, a second thyristor, a third thyristor, a first current transformer, a second current transformer, a third current transformer, an isolation transformer, a first IGBT, a second IGBT, a third IGBT, a fourth IGBT, a fifth IGBT, a sixth IGBT, a first capacitor, a second capacitor and a third capacitor; a first end of the first thyristor is electrically connected to a first input end on a power grid side, a second end of the first thyristor is electrically connected to a first output end on a load side through the first current transformer, a first end of the second thyristor is electrically connected to a second input end on the power grid side, a second end of the second thyristor is electrically connected to a second output end on the load side through the second current transformer, a first end of the third thyristor is electrically connected to a third input end on the power grid side, a second end of the third thyristor is electrically connected to a third output end on the load side through the third current transformer, a fourth input end on the power grid side is electrically connected to a fourth output end on the load side, a collector electrode of the first IGBT is electrically connected to a collector electrode of the third IGBT, and an emitter electrode of the first IGBT is electrically connected to a collector electrode of the second IGBT, the emitter of the second IGBT is electrically connected with the emitter of the fourth IGBT, the emitter of the fourth IGBT is also electrically connected with the emitter of the sixth IGBT, the collector of the third IGBT is also electrically connected with the collector of the fifth IGBT, the emitter of the third IGBT is electrically connected with the collector of the fourth IGBT, the emitter of the fifth IGBT is electrically connected with the collector of the sixth IGBT, the emitter of the first IGBT is also electrically connected with the first end of the first target side of the isolation transformer, the first target side of the isolation transformer is the primary side or the secondary side of the isolation transformer, the emitter of the third IGBT is also electrically connected with the second end of the first target side of the isolation transformer, the emitter of the fifth IGBT is also electrically connected with the third end of the first target side of the isolation transformer, and the first end of the second target side of the isolation transformer is electrically connected with the first output end of the load side, if the first target side of the isolation transformer is the primary side of the isolation transformer, the second target side of the isolation transformer is the secondary side of the isolation transformer, if the first target side of the isolation transformer is the secondary side of the isolation transformer, the second target side of the isolation transformer is the primary side of the isolation transformer, the second end of the second target side of the isolation transformer is electrically connected with the second output end of the load side, the third end of the second target side of the isolation transformer is electrically connected with the third output end of the load side, the fourth end of the second target side of the isolation transformer is electrically connected with the fourth output end of the load side, the first end of the first capacitor is electrically connected with the first end of the second target side of the isolation transformer, and the second end of the first capacitor is electrically connected with the fourth end of the second target side of the isolation transformer, a first end of the second capacitor is electrically connected with a second end of a second target side of the isolation transformer, a second end of the second capacitor is electrically connected with a second end of the first capacitor, a first end of the third capacitor is electrically connected with a third end of the second target side of the isolation transformer, a second end of the third capacitor is electrically connected with a second end of the second capacitor, and when no voltage sag problem occurs on the grid side, gate-level driving signal pulses are sent to the first thyristor, the second thyristor and the third thyristor so as to enable the first thyristor, the second thyristor and the third thyristor to be in a conducting state; when the voltage sag problem occurs on the power grid side, the method comprises the following steps:

s101, stopping sending each gate-level driving signal pulse;

s103, according to a target back-pressure turn-off value, a current voltage value of the first input end of the power grid side, a current voltage value of the second input end of the power grid side, a current voltage value of the third input end of the power grid side, a current first current value detected by the first current transformer, a current second current value detected by the second current transformer and a current third current value detected by the third current transformer, correcting a latest first pwm initial comparison value, a latest second pwm initial comparison value and a latest third pwm initial comparison value to obtain a first pwm corrected comparison value corresponding to the latest first pwm initial comparison value, a second pwm corrected comparison value corresponding to the latest second pwm initial comparison value and a third pwm corrected comparison value corresponding to the latest third pwm initial comparison value, wherein the target back-pressure turn-off value is a back-pressure turn-off value of the first thyristor, Either one of a back-voltage turn-off value of the second thyristor and a back-voltage turn-off value of the third thyristor, wherein the first IGBT and the second IGBT, when executing a current preset switching cycle of themselves in accordance with the first pwm correction comparison value and the first current value is not 0, can make a first target difference value, whose positive or negative is opposite to that of the first current value, the first target difference value being a difference value between a current voltage value of the first output terminal on the load side and a current voltage value of the first input terminal on the grid side, the third IGBT and the fourth IGBT, when executing a current preset switching cycle of themselves in accordance with the second pwm correction comparison value and the second current value is not 0, can make a second target difference value, whose positive or negative is opposite to that of the second current value, the second target difference value being a difference value between a current voltage value of the second output terminal on the load side and a current voltage value of the second input terminal on the grid side, when the fifth IGBT and the sixth IGBT execute their current preset switching cycles according to the third pwm correction comparison value and the third current value is not 0, the third target difference value is opposite in polarity to the third current value, where the third target difference value is the difference between the current voltage value of the third output terminal on the load side and the current voltage value of the third input terminal on the power grid side;

2. The method for rapidly turning off the thyristor according to claim 1, wherein the step S103 comprises:

and correcting a latest first pwm initial comparison value, a latest second pwm initial comparison value and a latest third pwm initial comparison value according to the target back-pressure turn-off value, the current angle of the voltage of the current target input end, the current voltage value of the first input end on the power grid side, the current voltage value of the second input end on the power grid side, the current value of the third input end on the power grid side, the first current value, the second current value and the third current value to obtain the first pwm corrected comparison value, the second pwm corrected comparison value and the third pwm corrected comparison value, wherein the target input end is any one of the first input end on the power grid side, the second input end on the power grid side and the third input end on the power grid side.

3. The method for rapidly shutting down a thyristor according to claim 2, wherein the isolation transformer is a DY isolation transformer, and the target input terminal is a first input terminal of the power grid side; correcting the latest first pwm initial comparison value, the latest second pwm initial comparison value and the latest third pwm initial comparison value according to the target back-voltage turn-off value, the angle of the voltage at the target input end, the current voltage value at the first input end on the power grid side, the current voltage value at the second input end on the power grid side, the first current value, the second current value and the third current value to obtain the first pwm corrected comparison value, the second pwm corrected comparison value and the third pwm corrected comparison value, including:

s306, judging whether the angle of the voltage of the first input end of the current power grid side is between 60 degrees and 150 degrees, if so, executing a step S307, and if not, executing a step S308;

s307, adding the latest first pwm initial comparison value to the target back-pressure cutoff value to obtain a fifth numerical value, taking the fifth numerical value as a latest third pwm initial comparison value, subtracting the target back-pressure cutoff value from the latest second pwm initial comparison value to obtain a sixth numerical value, and taking the sixth numerical value as a latest second pwm initial comparison value, and performing step S309;

s309, judging whether the current voltage value of the second input end of the power grid side is larger than 0 and the second current value is smaller than 0, if so, executing a step S310, otherwise, executing a step S313;

s313, determining whether a current voltage value of the first input terminal on the power grid side is less than 0 and the first current value is greater than 0, if yes, performing step S314, and if no, performing step S317;

s329 subtracting a thirty-fourth value from the latest second pwm initial comparison value to obtain a thirty-fifth value, taking the thirty-fifth value as the latest second pwm initial comparison value, adding a thirty-sixth value to the latest third pwm initial comparison value to obtain a thirty-seventh value, and taking the thirty-seventh value as the latest third pwm initial comparison value, and executing step S330, wherein the thirty-fourth value is a product of the target back-pressure off value and a thirty-eighth value, if the first current value is greater than 0, the thirty-eighth value is 1, if the first current value is less than 0, the thirty-eighth value is-1, the thirty-sixth value is a product of the target back-pressure off value and a thirty-ninth value, and if the third current value is greater than 0, the thirty-ninth value is 1, if the third current value is less than 0, the thirty-ninth value is-1;

s333 subtracting a forty-sixth value from the latest first pwm initial comparison value to obtain a forty-seventh value, taking the forty-seventh value as the latest first pwm initial comparison value, adding the forty-sixth value to the latest third pwm initial comparison value to obtain a forty-eighth value, and taking the forty-eighth value as the latest third pwm initial comparison value, and performing step S334, where the forty-sixth value is a product of the target backpressure shutdown value and a forty-ninth value, if the third current value is greater than 0, the forty-ninth value is 1, and if the third current value is less than 0, the forty-ninth value is-1;

4. The method for rapidly turning off a thyristor according to claim 1, wherein the preset switching period of the first IGBT, the preset switching period of the second IGBT, the preset switching period of the third IGBT, the preset switching period of the fourth IGBT, the preset switching period of the fifth IGBT and the preset switching period of the sixth IGBT are all the same; after step S104, the method further comprises:

5. The method for rapidly shutting down a thyristor according to claim 1, wherein the voltage restorer circuit further comprises: a fourth capacitor, a fifth capacitor and a resistor;

6. The method for rapidly shutting down a thyristor according to claim 1, wherein the voltage restorer circuit further comprises: a contactor and a buffer circuit;

7. The method for rapidly shutting down a thyristor as claimed in claim 5, wherein the fifth capacitor is a super capacitor.

8. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating via the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the steps of the thyristor fast turn-off method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps of the thyristor fast turn-off method as claimed in any one of claims 1 to 7.