CN114974372A

CN114974372A - Nonvolatile memory operation method and system

Info

Publication number: CN114974372A
Application number: CN202210600518.3A
Authority: CN
Inventors: 黄莹; 刘红涛; 赵向南; 蒋颂敏; 游开开; 王均保
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-05-30
Filing date: 2022-05-30
Publication date: 2022-08-30

Abstract

The application provides an operation method of a nonvolatile memory, which comprises the following steps: performing first-stage pre-charging on the plurality of memory strings, wherein the first-stage pre-charging is grid-induced drain leakage pre-charging; programming the memory cells in the memory string which is subjected to the first-stage pre-charging to different memory states through first-stage programming; pre-charging the memory strings after the first stage programming in a second stage, wherein the second stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain leakage pre-charging; and performing second-stage programming on memory cells in the memory string subjected to the second-stage precharging.

Description

Nonvolatile memory operation method and system

Technical Field

The embodiment of the application relates to the technical field of semiconductors, in particular to a method and a system for operating a nonvolatile memory.

Background

The flash memory device has the characteristics of multiple programming, high storage density, lower power consumption, large capacity, high reading and writing speed, suitability for storage of a large amount of data and the like, shows strong market competitiveness in the field of nonvolatile storage, and is also increasingly widely applied. For example, flash memory devices have been widely used in smart phones, cloud storage, and solid state drives of computers.

Flash memories have widely used NAND flash memory chips to process data. With the increase of the storage density, the number of storage bits of each storage unit is gradually increased, and the number of storage bits of each storage unit is increased accordingly. Taking a four-level cell QLC (quad-level cell) flash memory as an example, the QLC flash memory can store four bits per memory cell, i.e., has the capability of storing sixteen memory states. Different storage states can have different threshold voltage distributions, and different threshold voltage intervals where the storage unit is located after being charged through write operation can be mapped according to different threshold voltage intervals when data are read.

The threshold voltage of each storage state has a certain interval distribution, the non-overlapping part of the threshold voltage distributions of adjacent storage states is called a reading window, the smaller the threshold voltage distribution interval of each storage state is, the larger the reading window is, and the lower the probability of generating misjudgment in the process of reading data is. For the current QLC flash memory, the reading window is small, and in the programming process, the reading window of the memory is further reduced due to the programming interference and the rapid charge loss of the memory unit, so that the accuracy of data reading is reduced. At present, the channel is precharged by adopting a bit line precharging or source line precharging mode to reduce program interference, but the channel is precharged by adopting a bit line precharging or source line precharging mode, and the transfer of a precharging potential in the channel is influenced by a data mode.

Disclosure of Invention

The present application provides a method and system for operating a non-volatile memory that at least partially addresses the above-identified problems in the prior art.

According to an aspect of the present application, there is provided a method of programming of a non-volatile memory including a plurality of memory strings, the method may include: performing a first stage pre-charge on the plurality of memory strings, wherein the first stage pre-charge is a gate-induced drain leakage pre-charge; programming the memory cells in the memory string which is subjected to the first-stage pre-charging to different memory states through first-stage programming; performing a second stage pre-charge on the memory strings subjected to the first stage programming, wherein the second stage pre-charge is bit line pre-charge, source line pre-charge or gate-induced drain leakage pre-charge; and performing a second stage programming on memory cells in the memory string that have undergone the second stage precharging.

In one embodiment of the present application, after the first level programming, the method may further include: determining a bit error rate after the first level programming; in response to the bit error rate exceeding a predetermined value, the second stage pre-charge employs the gate-induced drain leakage pre-charge; and in response to the bit error rate not exceeding the predetermined value, the second stage precharging employing either the bit line precharging or the source line precharging.

In one embodiment of the present application, the memory string includes a top selection transistor, a bottom selection transistor, and a plurality of memory cells, and the pre-charging the memory string at the first stage and the pre-charging the memory string at the second stage may include: applying a first voltage to a bit line connected to the memory string; applying a second voltage to a source line connected to the memory string; applying a third voltage to a word line connected to a memory cell of the memory string; applying a fourth voltage to a top select line connected to a top select transistor of the memory string; and applying a fifth voltage to a bottom select line connected to a bottom select transistor of the memory string.

In one embodiment of the present application, during the pre-charging of the memory string with gate-induced drain leakage, at least one of the first voltage and the second voltage is a high level voltage, and the third voltage, the fourth voltage, and the fifth voltage are low level voltages.

In one embodiment of the present application, during the bit line precharge of the memory string, the first voltage and the fourth voltage are high level voltages, and the second voltage, the third voltage, and the fifth voltage are low level voltages.

In one embodiment of the present application, during the source line precharge of the memory string, the second voltage and the fifth voltage are high level voltages, and the first voltage, the third voltage, and the fourth voltage are low level voltages.

In one embodiment of the present application, the method may further include: performing third-stage pre-charging on the memory strings subjected to the second-stage programming, wherein the third-stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain leakage pre-charging; and performing third-stage programming on the memory cells in the memory string subjected to the third-stage precharging.

Another aspect of the present application provides a nonvolatile memory, including: a plurality of memory strings including a top select transistor, a bottom select transistor, and a plurality of memory cells; a control circuit configured to: performing a first stage pre-charge on the plurality of memory strings, wherein the first stage pre-charge is a gate-induced drain leakage pre-charge; programming the memory cells in the memory string which is subjected to the first-stage pre-charging to different memory states through first-stage programming; performing a second stage pre-charge on the memory string programmed by the first stage, wherein the second stage pre-charge is a bit line pre-charge, a source line pre-charge or a gate-induced drain leakage pre-charge; and performing second-stage programming on the memory cells subjected to the second-stage precharging.

In one embodiment of the present application, the control circuit may be further configured to: and verifying the memory unit which is programmed in the first stage, judging the error rate of the memory unit, if the error rate exceeds a preset value, pre-charging the second stage by adopting the gate-induced drain leakage, and otherwise, pre-charging the bit line or the source line.

In one embodiment of the present application, the control circuit further configured to precharge the memory string at the first stage and the second stage may include: applying a first voltage to a bit line connected to the memory string; applying a second voltage to a source line connected to the memory string; applying a third voltage to a word line connected to a memory cell of the memory string; applying a fourth voltage to a top select line connected to a top select transistor of the memory string; and applying a fifth voltage to a bottom select line connected to a bottom select transistor of the memory string.

In one embodiment of the present application, the control circuit may be further configured to: in the process of performing gate-induced drain leakage pre-charging on the memory string, at least one of the first voltage and the second voltage is a high level voltage, and the third voltage, the fourth voltage and the fifth voltage are low level voltages.

In one embodiment of the present application, the control circuit may be further configured to: in the bit line precharge process of the memory string, the first voltage and the fourth voltage are high level voltages, and the second voltage, the third voltage, and the fifth voltage are low level voltages.

In one embodiment of the present application, the control circuit may be further configured to: in the process of precharging the source line of the memory string, the second voltage and the fifth voltage are high-level voltages, and the first voltage, the third voltage and the fourth voltage are low-level voltages.

In one embodiment of the present application, the control circuit may be further configured to: performing third-stage pre-charging on the memory strings subjected to the second-stage programming, wherein the third-stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain leakage pre-charging; and performing third-stage programming on the memory cells in the memory string subjected to the third-stage precharging.

The present application also provides a non-volatile memory system, which may include: a non-volatile memory as described above; and a controller coupled with the non-volatile memory and configured to: performing a first stage pre-charge on the plurality of memory strings, wherein the first stage pre-charge is a gate-induced drain leakage pre-charge; programming the memory cells in the memory string which is subjected to the first-stage pre-charging to different memory states through first-stage programming; performing a second stage pre-charge on the memory string programmed by the first stage, wherein the second stage pre-charge is a bit line pre-charge, a source line pre-charge or a gate-induced drain leakage pre-charge; and performing a second stage programming on memory cells in the memory string that have undergone the second stage precharging.

In one embodiment of the present application, the controller may be further configured to: performing third-stage pre-charging on the memory strings subjected to the second-stage programming, wherein the third-stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain leakage pre-charging; and performing third-stage programming on the memory cells in the memory string subjected to the third-stage precharging.

In one embodiment of the present application, the memory system may be a solid state disk or a memory card.

According to the nonvolatile memory of the embodiment of the application, the storage string is subjected to grid-induced drain leakage pre-charging and then subjected to first-stage programming, so that charges at a shallow energy level in a channel corresponding to the storage string can be leaked after the first-stage programming, more charges in a corresponding channel layer are at a deep energy level, the threshold voltage retentivity of a storage unit to be programmed in the storage string is better after the first-stage programming, the anti-interference performance of the storage unit in the storage string is improved, the size of a read window of the storage unit in the subsequent programming process is improved, the misjudgment rate of the memory is reduced, and the performance of the memory is improved. And then, performing second-stage pre-charging and second-stage programming on the memory string subjected to the first-stage programming, further reducing the electron concentration in the channel layer, enabling the charges to be in a deep energy level, improving the potential of the channel, and enhancing the data retention.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. Wherein:

FIG. 1 is a schematic diagram of a memory string 10 of an exemplary embodiment;

FIG. 2 is a schematic diagram of a memory cell of an exemplary embodiment;

FIG. 3 is a schematic diagram illustrating the process of disturbing a memory cell during programming according to an exemplary embodiment;

FIG. 4 is a programming process diagram of an exemplary embodiment of a QLC memory of an exemplary embodiment;

FIG. 5 is a schematic diagram of a programming process of another exemplary embodiment of a QLC memory of an exemplary embodiment;

FIG. 6 is a flow chart illustrating a method of operating a memory according to an exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a memory block according to an exemplary embodiment of the present application;

FIG. 8 is an equivalent schematic diagram of a portion of the memory block shown in FIG. 7;

FIG. 9 is a schematic diagram of gate-induced drain leakage pre-charge according to an exemplary embodiment of the present application;

FIG. 10 is a schematic diagram of bit line precharging in accordance with an exemplary embodiment of the present application;

FIG. 11 is a schematic diagram of source line precharging in accordance with an exemplary embodiment of the present application;

FIG. 12 is a diagram illustrating programming effects according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a three-dimensional memory 2000 according to an embodiment of the present application;

FIG. 14 is a block diagram of a non-volatile storage system according to an example embodiment of the present application;

FIG. 15A is a schematic diagram of a non-volatile memory system according to an example embodiment of the present application; and

FIG. 15B is a schematic diagram of a non-volatile memory system according to another example embodiment of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification. The expression "and/or" includes any and all combinations of one or more of the associated listed items.

In the drawings, the size, dimension, and shape of elements have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-degree terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. In addition, in the present application, the order in which the processes of the respective steps are described does not necessarily indicate an order in which the processes occur in actual operation, unless explicitly defined otherwise or can be inferred from the context.

It will be further understood that terms such as "comprising," "including," "having," "including," and/or "containing," when used in this specification, are open-ended and not closed-ended, and specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than merely individual elements of the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

FIG. 1 is a schematic diagram of a memory string 10 of an exemplary embodiment. As shown in fig. 1, the memory string 10 may include a channel structure 12, wherein the channel structure includes a plurality of memory cells 13, and each memory cell is electrically connected to its corresponding word line WL through a gate 11. In programming the memory string 10, voltage programming pulses are applied to the word lines WL in a certain order, e.g., bottom to top or top to bottom, along the direction in which the channel structure 12 extends.

As shown in fig. 2, the memory cell 13 includes, in order from outside to inside, a charge blocking layer 131, a charge trapping layer 132, a tunneling layer 133, and a channel layer 134, wherein the channel layer 134 may be doped polysilicon, for example, doped with N-type impurity ions (e.g., phosphorus ions). During programming, a voltage programming pulse is applied to the gate 11 and electrons tunnel through the tunneling layer 133 to the charge trapping layer 132. The number of electrons reaching the charge trapping layer 132 varies with the applied voltage programming pulse. Based on the charge and discharge of electrons, the threshold voltage of the memory cell 13 can be strictly controlled, so that the data to be stored is in a specified threshold voltage interval, and therefore, different data can be stored.

FIG. 3 is a schematic diagram illustrating the process of disturbing a memory cell during programming according to an exemplary embodiment. As shown in a to C in fig. 3, the horizontal axis represents the threshold voltage of the memory cell, the vertical axis represents the number of memory cells, and the curve represents the distribution of the number of memory cells at different threshold voltages. The first level programming, also called rough programming, is performed on the memory cells on the word line WLn, so that the memory cells are in a certain memory state, and the memory cells are in the Px state for example. Applying a voltage programming pulse on a certain word line, applying a conducting voltage on the word lines of the rest memory cells in the same memory string, wherein the voltage programming pulse is far larger than the conducting voltage, a large voltage difference exists between the word line of the programmed memory cell and an adjacent word line, and inevitably programming interference can be generated on the memory cells corresponding to the adjacent word line, namely when the adjacent word line WLn +1 is subjected to first-stage programming, the memory cells of which the adjacent word line WLn is in a Px state can be subjected to certain programming interference. After being subjected to WLn +1 first level program disturb, the threshold voltage distribution of the memory cells with the word line WLn in the Px state is shown as B in FIG. 3, which generally results in widening of the threshold voltage distribution and overall increase of the threshold voltage of the memory cells with WLn in the Px state.

A certain interval generally exists between threshold voltage distributions of memory cells in adjacent memory states, and a part of the interval is called a Read Window (RWB), the read window is critical to reliability of the three-dimensional memory, and the smaller the threshold voltage distribution interval is, the larger the read window is, and the lower the probability of erroneous judgment is in the process of reading data. Accordingly, the threshold voltage distribution of memory cells in the same memory state can be reduced by second level programming, also referred to as fine programming. C in fig. 3 is the threshold voltage distribution of the memory cell in the Px state after the second level programming. As shown in C in fig. 3, the threshold voltage distribution of the memory cell in the Px state after the second level programming is smaller than the threshold voltage distribution (B in fig. 3) of the memory cell in the Px state after the first level programming interference of the word line WLn +1, which is beneficial to the accuracy of the subsequent read operation of the memory.

The memory may be divided into SLC memory, MLC memory, TLC memory, QLC memory, PLC memory, etc. according to the different storage bit numbers of each memory cell, and the application takes QLC memory as an example for description.

FIG. 4 is a schematic diagram of a programming process of an exemplary embodiment of a QLC memory. The memory cell to be programmed is in the erased state E0 (not shown). During programming, a first level of programming is first performed on the memory cells on word line WLn. Taking the threshold voltage distribution of the memory cells on the word line WLn as an example, as shown by the solid line in a in fig. 4, the QLC memory can store 4 bits per memory cell, and therefore 16 voltage interval distributions are required to represent 0000 to 1111. The memory cells on word line WLn, which are charged to a specified threshold voltage interval, may be in the corresponding storage states, i.e., P0-P15, and this programming method may be referred to as 16-16 programming. And then, performing first-level programming on the adjacent word line WLn +1, applying a voltage programming pulse to the word line WLn +1, wherein the distance between the memory cell of the word line WLn +1 and the memory cell on the word line WLn is small, so that the distribution of the threshold voltages of the memory cells on the word line WLn is increased, as shown by B in FIG. 4 or shown by a dotted line in A in FIG. 4, the threshold voltage distributions of adjacent memory states are overlapped, and during the subsequent read operation, misjudgment easily occurs, and the reliability of the memory is affected. C in FIG. 4 is the threshold voltage distribution of the memory cells on word line WLn after the second level programming. When the memory cells on the word line WLn are programmed in the second level, the threshold voltage distribution of the memory cells in the storage state (i.e., P0-P15) after the second level programming is smaller than the threshold voltage distribution (B in FIG. 4) of the memory cells after the first level programming interference of the word line WLn +1, and the threshold voltage distribution interval of the memory cells in the storage state (i.e., P0-P15) is smaller, as shown by the solid line C in FIG. 4. After the memory cells on word line WLn have completed the second level programming, the voltage distribution of the memory cells on word line WLn after receiving program disturb for the remaining word lines (e.g. word line WLn +1) is shown by the dotted line in FIG. 4C. As can be seen from fig. 4, when the adjacent other word lines are programmed, the programmed memory cells are easily subjected to program disturb, resulting in a smaller read window.

FIG. 5 is a schematic diagram of a programming process of another exemplary embodiment of a QLC memory. The memory cell to be programmed is in the erased state E0 (not shown). During programming, a first level of programming is first performed on the memory cells on word line WLn. Taking the threshold voltage distribution of the memory cells on the word line WLn as an example, as shown by the solid line in a in fig. 5, the QLC memory can store 4 bits per memory cell, and therefore 16 voltage interval distributions are required to represent 0000 to 1111. The memory cells on word line WLn are charged to a designated threshold voltage range, and the memory cells are programmed to 8 memory states, namely P0-P7. Then, a first level programming is performed on the adjacent word line WLn +1, a voltage programming pulse is applied to the word line WLn +1, and the distribution of threshold voltages of memory cells on the word line WLn increases due to the small distance between the memory cells of the word line WLn +1 and the memory cells on the word line WLn, as shown by B in fig. 5 or by a dotted line in fig. 5. Threshold voltage distribution reading windows of adjacent storage states are small, and misjudgment is easy to occur in the subsequent reading operation process, so that the reliability of the storage is influenced. C in FIG. 4 is the threshold voltage distribution of the memory cells on word line WLn after the second level programming. The second level programming is performed on the memory cells on word line WLn, further programming the memory cells of 8 storage states to 16 storage states (i.e., P0-P15). After the memory cells on the word line WLn complete the second level programming, the voltage distribution of the memory cells on the word line WLn after receiving the program disturb of the remaining word lines (e.g., the word line WLn +1) is shown by the dotted line C in fig. 5, and this programming method can be referred to as 8-16 programming. As can be seen from fig. 5, when the adjacent other word lines are programmed, the programmed memory cells are easily subjected to program disturb, resulting in a smaller read window.

FIG. 6 is a flowchart illustrating a method of operating a non-volatile memory according to an exemplary embodiment of the present application. As shown in fig. 6, a method 1000 of operating a non-volatile memory may include:

step S100: performing first-stage pre-charging on the plurality of memory strings, wherein the first-stage pre-charging is grid-induced drain leakage pre-charging;

step S200: programming the memory cells in the memory string which is subjected to the first-stage pre-charging to different memory states through first-stage programming;

step S300: performing second-stage pre-charging on the memory string subjected to the first-stage programming, wherein the second-stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain leakage pre-charging; and

step S400: and performing second-stage programming on the memory cells in the memory strings subjected to the second-stage precharging.

The steps of the programming method 1000 will be described in detail with reference to fig. 7 to 15.

In an exemplary embodiment of the present application, the non-volatile memory may include at least one memory array, which may include a plurality of memory blocks. FIG. 7 is a schematic diagram of a memory block according to an exemplary embodiment of the present application. As shown in FIG. 7, the memory block includes a plurality of memory strings MS 11-MSnm, and the memory strings MS 11-Mnm may be arranged in a two-dimensional array. Each memory string may be connected to the bit line BL and the common source line SL, and each memory string may include a top select transistor TSG, a plurality of memory cells MC, and a bottom select transistor BSG sequentially connected in series, where the number of the top select transistor TSG, the memory cells MC, and the bottom select transistor BSG of each memory string MS is not specifically limited in this application. The memory cell MC can be connected to its corresponding word line WL, and the threshold voltage of the memory cell MC is changed by applying different voltages to the word line WL by using a tunneling effect, so that the memory cell MC is in different storage states.

Fig. 8 is an equivalent schematic diagram of a portion of a memory block according to that shown in fig. 7. FIG. 8 shows a plurality of memory strings MS 11-MS 1m connected to the same bit line BL 1. The top select transistors in memory strings MS 11-MS 1m may be connected to top select line TSL11, and the bottom select transistors in memory strings MS 12-MS 1m may be connected to bottom select line BSL 1. The operation of the memory strings MS 11-MS 1m during the precharge phase will be described in detail with reference to the accompanying drawings.

In the exemplary embodiment of the present application, step S100 is first performed to perform a first stage precharge on the plurality of memory strings, where the first stage precharge may be a gate-induced drain leakage (GIDL) precharge. The memory string subjected to the first-stage precharge may be a selected memory string from a plurality of memory strings, or may be all memory strings, which is not limited in this application. The gate-induced drain leakage is to form a voltage difference between at least one of the bit line BL and the source line SL and the select transistor to cause electrons in the channel to flow to at least one of the bit line BL and the source line SL, thereby reducing the concentration of electrons in the channel layer and increasing the potential of the channel. FIG. 9 is a schematic diagram of gate-induced drain leakage pre-charge, where a selected memory string may also be referred to as a memory string to be programmed, according to an example embodiment of the present application. As shown in fig. 9, in the first stage of the precharge phase, for example, the selected memory string is precharged, and a first voltage, also referred to as a bit line precharge voltage Vbl-pre, is applied to both the selected bit line sel-BL connected to the selected memory string and the unselected bit line unsel-BL connected to the unselected memory string, and the bit line precharge voltage Vbl-pre may be at a high level, for example, 5V. A fourth voltage is applied to the selected top select line sel-TSL to which the top select transistor TSG included in the selected memory string is connected and the unselected top select line unsel-TSL to which the top select transistor TSG included in the unselected memory string is connected, wherein the fourth voltage is a low level voltage, for example, 0V, so that a voltage difference is formed between the top select transistor TSG and the bit line BL to generate a Band-to-Band Tunneling effect (BTB), and therefore, holes may be generated in a channel layer (see fig. 2 for details) of a channel structure corresponding to the top select transistor TSG, and then electrons in the channel may flow to and combine with the holes, thereby reducing the concentration of electrons in the channel layer and increasing the potential of the channel. Meanwhile, a third voltage is applied to the selected word line sel-WL to which the memory cell to be programmed is connected and the unselected word line unsel-WL to which the non-programmed memory cell is connected, wherein the third voltage may be a low level voltage. A fifth voltage, which may be a low level voltage, is applied to the bottom select line BSL to which the bottom select transistor BSG included in the selected memory string is connected, and a second voltage, which may also be referred to as a source line precharge voltage Vsl-pre, which may be a high level, for example, 5V, is applied to the source line SL to which the selected memory string is connected. Since a voltage difference is formed between the bottom selection transistor BSG and the source line SL to generate a Band-to-Band Tunneling (BTB), holes may be generated in a channel layer (see fig. 2) of a channel structure corresponding to the bottom selection transistor BSG, and then electrons in the channel may flow to and combine with the holes, thereby reducing an electron concentration in the channel layer and increasing a potential of the channel. It can be seen by those skilled in the art that the voltage range of the high level voltage and the voltage range of the low level voltage can be adjusted according to the memory parameters, and the present application is not limited thereto.

In the exemplary embodiment of the present application, during the gate-induced drain leakage pre-charge process, one of the first voltage and the second voltage may also be set to a high level, for example, 5V (not shown in the figure). Illustratively, the first voltage is at a high level, and the second voltage is at a low level, for example, 0V, which may form a voltage difference between the top select or select transistor TSG and the bit line BL, further generating a Band-to-Band Tunneling (BTB) effect, so that holes may be generated in a channel layer (see fig. 2) of the channel structure corresponding to the top select transistor TSG, and then electrons in the channel may flow to the holes and combine with the holes, thereby reducing the concentration of electrons in the channel layer and increasing the potential of the channel. Illustratively, the first voltage is low, the second voltage is high, a voltage difference may be formed between the bottom selection transistor BSG and the source line SL, and a Band-to-Band Tunneling (BTB) effect may be further generated, so that holes may be generated in a channel layer (see fig. 2 in detail) of a channel structure corresponding to the bottom selection transistor BSG, and then electrons in the channel may flow to and combine with the holes, thereby reducing an electron concentration in the channel layer and increasing a potential of the channel. One skilled in the art can appreciate that the voltage range of the high level voltage and the voltage range of the low level voltage can be adjusted according to the memory parameters, and the present application is not limited thereto.

Step S200 may then be performed to program the memory cells in the first-stage precharged memory string to different memory states by first-stage programming. In an exemplary embodiment of the present application, in conjunction with FIG. 9, a low level voltage is applied to the selected bit lines sel-BL and the unselected bit lines unsel-BL apply a bit line program inhibit voltage Vbl-inhibit during the program phase, wherein the bit line program inhibit voltage Vbl-inhibit is slightly less than the bit line precharge voltage Vbl-pre. Selecting the top select line sel-TSL applies a top select transistor programming voltage Vtsg-pgm, which may be high, to the top select transistor TSG to which the selected top select line sel-TSL is connected, in a turned-on state, while applying a voltage of low level to the unselected top select line unsel-TSL to put the top select transistor TSG to which the unselected top select line unsel-TSL is connected in a turned-off state. Applying a conducting voltage to an unselected word line unsel-WL connected with the un-programmed memory cell to enable the un-programmed memory cell to be in a conducting state, applying a programming voltage to a selected word line sel-WL connected with the memory cell to be programmed, and performing first-level programming on the memory cell to be programmed, wherein the first-level programming can be performed in the mode of any one of the graph 4 or the graph 5, and the memory cell is programmed to 8 memory states or 16 memory states through the first-level programming. Meanwhile, in the programming stage, a low level voltage is applied to the bottom selection line BSL and the source line SL connected to the selected memory string.

According to the exemplary embodiment of the application, by performing gate-induced drain leakage pre-charging on the memory string, charges at a shallow level in a channel corresponding to the memory string can be leaked after undergoing first-stage programming, more charges in a corresponding channel layer are located at a deep level, and threshold voltage retentivity of a memory cell to be programmed in the memory string is better after the first-stage programming, so that the anti-interference performance of the memory cell can be increased in subsequent programming, the size of a read window of the memory cell in the subsequent programming process is improved, the misjudgment rate of the memory is reduced, and the performance of the memory is improved.

Step S300 may then be performed to perform a second stage precharge on the memory string programmed by the first stage, where the second stage precharge includes a bit line precharge, a source line precharge, or a gate-induced drain leakage precharge. In the exemplary embodiment of the present application, after the first-stage programming is performed, a bit line precharge may be performed on the selected memory string, where a potential difference is formed between the bit line BL connected to the memory string and the channel thereof, so that electrons in the channel flow to the bit line BL, the electron concentration in the channel layer is reduced, and the channel potential is increased. FIG. 10 is a schematic diagram of bit line precharging in which a memory string to be programmed may also be referred to as a selected memory string, according to an example embodiment of the present application. As shown in FIG. 10, during the second stage precharge phase, a first voltage, also referred to as a bit line precharge voltage Vbl-pre, which may be high, e.g., 5V, is applied to both the selected bit line sel-BL connected to the selected memory string and the unselected bit line unsel-BL connected to the unselected memory string. A fourth voltage, also referred to as a top select line precharge voltage Vtsl-pre, is applied to the selected top select line sel-TSL to which the top select transistor TSG included in the selected memory string is connected and the unselected top select lines unsel-TSL to which the top select transistor TSG included in the unselected memory string is connected, wherein the top select line precharge voltage Vtsl-pre may be high, and the top select transistor TSG may be brought into a conductive state by applying the top select line precharge voltage Vtsl-pre to the top select transistor TSG. Meanwhile, a third voltage is applied to the selected word line sel-WL to which the memory cell to be programmed is connected and the unselected word line unsel-WL to which the non-programmed memory cell is connected, a fifth voltage is applied to the bottom select line BSL to which the bottom select transistor BSG included in the selected memory string is connected, and a second voltage is applied to the source line SL to which the selected memory string is connected, wherein the third voltage, the fifth voltage, and the second voltage may be low level voltages, for example, 0V. Since a high-level voltage is applied to the bit line BL connected to the memory string and the top selection transistor TSG connected thereto is in an on state, electrons in the channel can be made to flow to the bit line BL, and the electron concentration in the channel layer can be further reduced to some extent, increasing the channel potential. It can be seen by those skilled in the art that the voltage range of the high level voltage and the voltage range of the low level voltage can be adjusted according to the memory parameters, and the present application is not limited thereto.

In the exemplary embodiment of the present application, after the first-stage programming is performed, source line precharging may be performed on the memory string, where source line precharging is performed by forming a potential difference between a source line SL connected to the memory string and a channel thereof, so that electrons in the channel flow to the source line SL, the concentration of electrons in the channel layer is reduced, and the channel potential is increased. FIG. 11 is a schematic diagram of source line precharging in which a memory string to be programmed may also be referred to as a selected memory string, according to an example embodiment of the present application. As shown in FIG. 11, in the second stage precharge phase, a third voltage is applied to the selected bit line sel-BL of the memory string connection and the unselected bit line unsel-BL of the unselected memory string connection, the selected top select line sel-TSL and the unselected top select line unsel-TSL fourth voltage, the selected word line sel-WL of the memory cell to be programmed connection and the unselected word line unsel-WL of the non-programmed memory cell connection, and the first voltage, the fourth voltage and the third voltage may be low level voltages, for example, 0V. Meanwhile, a second voltage, also referred to as a bottom selection line precharge voltage Vbsl-pre, which may be a high level, is applied to a bottom selection line BSL to which a bottom selection transistor BSG included in the selected memory string is connected, and the bottom selection transistor BSG may be brought into a conductive state by applying a fifth voltage, also referred to as a bottom selection line precharge voltage Vbsl-pre, to the bottom selection transistor BSG. The source line precharge voltage Vsl-pre, which may be high, for example, 5V, is applied to the source line SL connected to the selected memory string. Since a high-level voltage is applied to the source line SL connected to the memory string and the bottom selection transistor BSG connected thereto is in a conductive state, electrons in the channel can be made to flow to the source line SL, the electron concentration in the channel layer can be further reduced to some extent, and the channel potential can be increased. One skilled in the art can appreciate that the voltage range of the high level voltage and the voltage range of the low level voltage can be adjusted according to the memory parameters, and the present application is not limited thereto.

In the exemplary embodiment of the present application, after the first-stage programming is performed on the plurality of memory cells in the plurality of memory strings and the plurality of memory cells are programmed to different memory states, the disturbed condition of the memory cells after the first-stage programming can be judged, and then the charging mode of the second-stage precharging can be determined. Illustratively, the memory cell after the first-stage programming is verified, the error rate of the memory cell is judged, if the error rate of the programmed memory cell after the first-stage programming exceeds a preset value, namely the programmed memory cell is greatly interfered, the memory string is subjected to gate-induced drain leakage pre-charging again, and otherwise, bit line pre-charging or source line pre-charging is adopted. The bit error rate of the programmed memory cell after the first-level programming can be obtained by reading the storage state of the programmed memory cell after the first-level programming and comparing the storage state with correct data to be stored. The predetermined value of the bit error rate may be set according to actual needs, which is not limited in this application. The detailed descriptions of the processes of performing the GIDL precharge and the second-level programming on the memory string again are already described above, and will not be described herein too much.

According to the exemplary embodiment of the application, after the first-stage programming is carried out on the memory strings, if the programmed memory cells are programmed in the first stage, the error rate of the memory cells subjected to the first-stage programming is judged, and if the error rate exceeds a preset value, GIDL pre-charging is carried out on the selected memory strings again, so that the electron concentration in the channel layer is further reduced, the charges are in a deep energy level, and the channel potential is improved. After bit line pre-charging or source line pre-charging is carried out on the memory cell to be programmed in the selected memory string, the threshold voltage retentivity is better, so that the size of a read window of the memory cell in the subsequent programming process is improved, the misjudgment rate of the memory is reduced, and the performance of the memory is improved.

According to the exemplary embodiments of the present application, after the first-stage programming is performed on the selected memory string, bit line pre-charging, source line pre-charging or gate-induced drain leakage is performed. Further reducing the electron concentration in the channel layer, enabling the charges to be in a deep energy level, and improving the channel potential. After bit line pre-charging, source line pre-charging or grid-induced drain leakage is carried out on the memory cell to be programmed in the selected memory string, the threshold voltage retentivity is better, so that the size of a read window of the memory cell in the subsequent programming process is improved, the misjudgment rate of the memory is reduced, and the performance of the memory is improved. Furthermore, the mode of precharging the second stage is selected, so that the performance of the memory and the precharging time are considered. After the first stage programming, if the interference on the programmed memory cell is small, the second stage pre-charging can adopt bit line pre-charging or source line pre-charging, so that the pre-charging time can be reduced; after the first stage programming, if the interference on the programmed memory cell is larger, the second stage pre-charging can adopt grid-induced drain leakage, thereby further reducing the interference of the memory cell and improving the performance of the memory.

Step S400 may then be performed to perform a second level programming on the memory cells in the second level precharged memory string. In the exemplary embodiment of the present application, in conjunction with FIGS. 10 and 11, a low level voltage is applied to the selected bit lines sel-BL and the unselected bit lines unsel-BL apply a bit line program inhibit voltage Vbl-inhibit during the second level programming phase, wherein the bit line program inhibit voltage Vbl-inhibit is slightly less than the bit line precharge voltage Vbl-pre. Selecting the top select line sel-TSL applies a top select transistor programming voltage Vtsg-pgm, which may be high, to the top select transistor TSG to which the selected top select line sel-TSL is connected, in a turned-on state, while applying a voltage of low level to the unselected top select line unsel-TSL to put the top select transistor TSG to which the unselected top select line unsel-TSL is connected in a turned-off state. Applying a conducting voltage to an unselected word line unsel-WL connected with the un-programmed memory cell to enable the un-programmed memory cell to be in a conducting state, applying a programming voltage to a selected word line sel-WL connected with the memory cell to be programmed, and performing second-stage programming on the memory cell to be programmed, wherein the second-stage programming can be performed in the manner of any one of the graph 4 or the graph 5, and the memory cell is programmed to a final storage state through the second-stage programming.

In the exemplary embodiment of the present application, the program result obtained by using the precharge method of the present application and the related art precharge method will be described with reference to a QLC memory as an example, as shown in fig. 12, where a solid line 1 is a threshold voltage distribution immediately after the memory cell finishes programming, a broken line 2 is a threshold voltage distribution when a certain time (less than 1s) has elapsed after the memory cell finishes programming, and a broken line 3 is a threshold voltage distribution when a selected memory string is precharged in the precharge stage by using the exemplary embodiment of the present application and a certain time (less than 1s) has elapsed after the memory cell finishes programming. As can be seen from the solid line 1 and the dashed line 2 in fig. 12, in the related art, after the programming is finished, there is a certain fast charge loss, which causes a certain shift of the threshold voltage distribution of the memory cell, resulting in a reduction of the read window; as can be seen from the dotted line 2 and the dotted line 3 in fig. 12, the GIDL precharge mode is adopted before the first-stage programming, and the SL precharge mode, the GIDL precharge or the BL precharge mode is adopted before the second-stage programming, so that the fast charge loss can be effectively suppressed, the drift amount of the threshold voltage distribution of the memory cell is small, the size of the read window is further improved, the misjudgment rate of the memory is reduced, and the performance of the memory is improved.

In the exemplary embodiments of the present application, after the second level programming is performed, a bit line precharge, a source line precharge or a gate-induced drain leakage precharge may be performed on the selected memory string, and then the third level programming is performed. Illustratively, the QLC memory is taken as an example for explanation. Performing first-stage pre-charging on the memory string, wherein the first-stage pre-charging is gate-induced drain leakage pre-charging, and in the first-stage programming process, programming the memory cell to 8 memory states, namely P0-P7 states (figure 5); then, carrying out second-stage pre-charging on the memory string, wherein the second-stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain leakage pre-charging, and in the second-stage programming process, the memory cell is programmed to 16 memory states from 8 memory states (P0-P7), namely P0-P15 (figure 5); and then carrying out third-stage pre-charging on the memory strings, wherein the third-stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain pre-charging, and in the third-stage programming process, the threshold voltage distribution interval of 16 memory states is reduced. The process of precharging and the process of programming have been specifically described above, and are not described herein in detail.

According to the exemplary embodiment of the application, the electron concentration in the channel layer is further reduced by performing three times of pre-charging and three times of programming on the memory string, so that the charges are in a deep energy level, and the channel potential is improved. After bit line pre-charging, source line pre-charging or grid-induced drain leakage is carried out on a memory cell to be programmed in the memory string, the threshold voltage retentivity is better, so that the size of a read window of the memory cell in the subsequent programming process is improved, the misjudgment rate of the memory is reduced, and the performance of the memory is improved.

In another aspect of the present application, a nonvolatile memory 2000 is provided, and fig. 13 is a schematic diagram of the nonvolatile memory 2000 according to an embodiment of the present application. As shown in fig. 13, the nonvolatile memory 2000 may include a memory array 21 and a control circuit 22. The control circuit 22 may include an I/O circuit 221, a control logic circuit 222, a voltage generator 223, an address decoder 224, and a page buffer 225.

The memory array 21 may be connected to the address decoder 224 by, for example, word lines WL, bit lines BL, top select lines TSL, and bottom select lines BSL. The memory array 21 may include a plurality of memory blocks, each of which may include a plurality of memory strings, each of which may include a top select transistor, a bottom select transistor, and a plurality of memory cells in which data may be stored.

The control logic circuit 222 may control the address decoder 224, the page buffer 225, and the voltage generator 223 in response to a command CMD (e.g., a precharge command, a program command, and a read command) and an address ADD from the I/O circuit 221. In addition, the control logic 222 may control the memory to perform a precharge operation and a program operation. In the exemplary embodiment of the present application, the control logic circuit 222 may control the memory to perform a first stage precharge on a selected memory string from the plurality of memory strings, wherein the first stage precharge may be a gate-induced drain leakage precharge; programming the memory cells in the memory string which is subjected to the first-stage pre-charging to different memory states through first-stage programming; performing a second-stage pre-charge on the memory strings after the first-stage programming, wherein the second-stage pre-charge can be a gate-induced drain leakage pre-charge, a bit line pre-charge or a source line pre-charge; and performing second-stage programming on memory cells in the memory string subjected to the second-stage precharging. The control logic 222 may control the memory to determine the bit error rate of the memory cell after programming the first stage, and if the bit error rate exceeds a predetermined value, the second stage pre-charge selects the gate-induced drain leakage pre-charge, otherwise the second stage pre-charge employs the bit line pre-charge or the source line pre-charge.

In the exemplary embodiment of the present application, the control logic circuit 222 may control the memory to perform a third stage precharge on the memory string subjected to the second stage programming, wherein the third stage precharge is a bit line precharge, a source line precharge or a gate-induced drain leakage precharge, and then may perform the third stage programming on the memory cell in the memory string subjected to the third stage precharge.

The voltage generator 223 may generate a precharge voltage, a turn-on voltage, and a program voltage to be supplied to the memory cells including the word line WL, the bit line BL, the source line SL, the top select line TSL, and the bottom select line BSL under the control of the control logic circuit 222. The voltage generator 223 may also generate a verify voltage to cause the control circuit to verify the threshold voltage of the memory cell with the verify voltage to confirm that the memory cell is in the corresponding memory state. Those skilled in the art will appreciate that the precharge voltage, the turn-on voltage, the program voltage, and the verify voltage may be determined according to the actual application. In an exemplary trial mode of the present application, the voltage generator 223 may generate a plurality of precharge voltages and apply the precharge voltages to the word line WL, the bit line BL, the source line SL, the top select line TSL, and the bottom select line BSL in a precharge stage including a first precharge stage and a second precharge stage, for example, applying a first voltage to a bit line connected to a selected memory string and applying a second voltage to a source line connected to the selected memory string; applying a third voltage to a word line connected to a memory cell of the selected memory string; applying a fourth voltage to a top selection line TSL connected to the top selection transistor of the selected memory string; and applying a fifth voltage to a bottom select line BSL connected to the bottom select transistor of the selected memory string.

In an exemplary embodiment of the present application, the control logic circuit 222 configured to perform gate-induced drain leakage pre-charging on the memory string may include: at least one of the first voltage and the second voltage is set to a high level voltage, and the third voltage, the fourth voltage, and the fifth voltage are set to a low level voltage.

In an exemplary embodiment of the present application, the control logic 222 is configured to bit line precharge the memory strings, including: the first voltage and the fourth voltage are set as high level voltages, and the second voltage, the third voltage, and the fifth voltage are set as low level voltages.

In an exemplary embodiment of the present application, the control logic 222 is configured to source line precharge the memory strings, including: the second voltage and the fifth voltage are set as high level voltages, and the first voltage, the third voltage and the fourth voltage are set as low level voltages.

The address decoder 224 may control word lines WL, bit lines BL, source lines SL, top select lines TSL, and bottom select lines BSL connected to the memory cell array in response to the control logic circuit 222. In other words, address decoder 224 may receive and decode address ADD from control logic 222 and select memory cells in the memory array for programming based on the decoded address ADD. The address decoder 224 may provide a voltage required for the word line WL from the voltage generator 223 to the word line WL corresponding to the selected memory cell.

The page buffer 225 may function as a write driver or a sense amplifier depending on the operation mode. For example, in a programming operation, the page buffer 225 may provide DATA to be programmed to the memory array 21, and the DATA may be multi-bit DATA to be programmed. In a read operation, the page buffer 225 may read DATA stored in the selected memory cell and output the read DATA to the I/O circuit 221.

FIG. 14 is a block diagram of a non-volatile storage system according to an example embodiment of the present application. The non-volatile storage system may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, Virtual Reality (VR) device, Augmented Reality (AR) device, or any other suitable electronic device having storage therein. As shown in fig. 14, the non-volatile storage system may include a host 30, and a memory system 40 having one or more memories 42 and a controller 41. The host 30 may be a processor of an electronic device, such as a Central Processing Unit (CPU), or a system on a chip (SoC), such as an Application Processor (AP).

In the exemplary embodiment of the present application, the controller 41 is coupled to the memory 42 and the host 30, and is configured to control the memory 42 to perform operations, such as performing data erase, data write, or data read operations. The controller 41 may manage data stored in the memory 42 and communicate with the host 30. In some exemplary embodiments, the controller 41 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, Compact Flash (CF) card, Universal Serial Bus (USB) flash drive, or other medium used in electronic devices such as personal computers, digital cameras, mobile phones, and the like. In some example embodiments, the controller 41 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC) that serves as data storage for mobile devices (such as smart phones, tablets, laptops, etc.) and enterprise storage arrays. The controller 41 may be configured to control operations of the memory 42, such as read, erase, and program operations. The controller 41 may also be configured to manage various functions with respect to data stored or to be stored in the memory 42, including bad block management, garbage collection, logical to physical address translation, wear leveling, and the like. In some exemplary embodiments, the controller 41 is further configured to process an Error Correction Code (ECC) for data read from or written to the memory 42. Any other suitable function may also be performed by the controller 41, such as formatting memory. Controller 41 may communicate with an external device (e.g., host 30) according to a particular communication protocol. For example, the controller 41 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a firewire protocol, and the like.

The controller 41 and the one or more memories 42 may be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Storage (UFS) package or an eMMC package. That is, the memory system 40 may be implemented as and packaged into different types of end electronics.

Non-volatile memory system of an exemplary embodiment of the present application as shown in fig. 15A, a controller 41 and a single memory 42 may be integrated into a non-volatile memory system 400 a. The controller 41 may control the memory 42 through, for example, a channel (not shown), and the memory 42 may perform an operation based on the control of the controller 41. The memory 42 may receive commands and addresses from the controller 41 through the channel and access a region selected from the memory array in response to the address. More specifically, the controller 41 may send a command and an address to execute the program operation method 1000 described in any of the above embodiments through the channel, so that the memory 42 executes the program operation method.

In some example embodiments, the controller 41 and the one or more memories 42 may be integrated into various types of storage systems, in other words, the

memory systems

400a, 400b may be implemented and packaged into different types of final electronic products. In one example as shown in fig. 15A, the controller 41 and the memory 42 may be integrated into a memory system 400a in the form of a memory card. The memory card may include a PC card (PCMCIA, personal computer memory card international association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), and the like. The memory system 400a in the form of a memory card may also include a memory card connector 43 for coupling it with a host (not shown).

In the nonvolatile memory system according to an exemplary embodiment of the present application, as shown in fig. 15B, a controller 41 and a plurality of memories 42 may be integrated into a memory system 400B. The controller 41 and the plurality of memories 42 may be integrated into a memory system 400b formed of a Solid State Disk (SSD). The Solid State Disk (SSD) may also include an SSD connector 43 coupling it with a host. In some embodiments, the storage capacity and/or operating speed of a Solid State Disk (SSD) may be higher than that of a memory card.

The objects, technical solutions and advantageous effects of the present invention are further described in detail with reference to the above-described embodiments. It should be understood that the above description is only a specific embodiment of the present invention, and is not intended to limit the present invention. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method of operating a non-volatile memory, the non-volatile memory including a plurality of memory strings, the method comprising:

performing a first stage pre-charge on the plurality of memory strings, wherein the first stage pre-charge is a gate-induced drain leakage pre-charge;

programming the memory cells in the memory string which is subjected to the first-stage pre-charging to different memory states through first-stage programming;

performing a second stage pre-charge on the memory string programmed by the first stage, wherein the second stage pre-charge is a bit line pre-charge, a source line pre-charge or a gate-induced drain leakage pre-charge; and

and performing second-stage programming on the memory cells in the memory strings which are subjected to the second-stage precharging.

2. The method of claim 1, wherein after passing the first level of programming, the method further comprises:

determining an error rate of memory cells programmed through the first level;

in response to the bit error rate exceeding a predetermined value, the second stage pre-charge employs the gate-induced drain leakage pre-charge; and

in response to the bit error rate not exceeding the predetermined value, the second stage precharge employs either the bit line precharge or the source line precharge.

3. The method of claim 1, wherein the memory string includes a top select transistor, a bottom select transistor, and a plurality of memory cells, the first stage precharging and the second stage precharging including:

applying a first voltage to a bit line connected to the memory string;

applying a second voltage to a source line connected to the memory string;

applying a third voltage to a word line connected to a memory cell of the memory string;

applying a fourth voltage to a top select line connected to a top select transistor of the memory string; and

applying a fifth voltage to a bottom select line connected to a bottom select transistor of the memory string.

4. The method of claim 3, wherein at least one of the first voltage and the second voltage is a high level voltage and the third voltage, the fourth voltage, and the fifth voltage are low level voltages during a gate-induced drain leakage pre-charge of the memory string.

5. The method of claim 3, wherein the first voltage and the fourth voltage are high level voltages and the second voltage, the third voltage and the fifth voltage are low level voltages during the bit line precharging of the memory string.

6. The method of claim 3, wherein the second voltage and the fifth voltage are high level voltages and the first voltage, the third voltage, and the fourth voltage are low level voltages during the source line precharge of the memory string.

7. The method of claim 1, wherein the method further comprises:

performing third-stage pre-charging on the memory strings subjected to the second-stage programming, wherein the third-stage pre-charging is bit line pre-charging, source line pre-charging or gate-induced drain leakage pre-charging; and

and performing third-stage programming on the memory cells in the memory strings which are subjected to the third-stage precharging.

8. A non-volatile memory, wherein the non-volatile memory comprises:

a plurality of memory strings including a top select transistor, a bottom select transistor, and a plurality of memory cells;

a control circuit configured to:

and performing second-stage programming on the memory cells subjected to the second-stage precharging.

9. The non-volatile memory of claim 8, wherein the control circuitry is further configured to:

determining a bit error rate after the first level programming;

10. The non-volatile memory of claim 8, wherein the control circuit is further configured to precharge the memory string at the first stage and the second stage comprises:

applying a first voltage to a bit line connected to the memory string;

applying a second voltage to a source line connected to the memory string;

11. The non-volatile memory of claim 10, wherein the control circuitry is further configured to: in the process of performing gate-induced drain leakage pre-charging on the memory string, at least one of the first voltage and the second voltage is a high level voltage, and the third voltage, the fourth voltage and the fifth voltage are low level voltages.

12. The non-volatile memory of claim 10, wherein the control circuitry is further configured to: in the bit line precharge process of the memory string, the first voltage and the fourth voltage are high level voltages, and the second voltage, the third voltage, and the fifth voltage are low level voltages.

13. The non-volatile memory of claim 10, wherein the control circuitry is further configured to: in the process of precharging the source line of the memory string, the second voltage and the fifth voltage are high-level voltages, and the first voltage, the third voltage and the fourth voltage are low-level voltages.

14. The non-volatile memory of claim 10, wherein the control circuitry is further configured to:

15. A non-volatile memory system, comprising:

the non-volatile memory of any one of claims 8 to 14; and

a controller coupled with the non-volatile memory and configured to:

performing a first stage precharge on a selected memory string from the plurality of memory strings, wherein the first stage precharge is a gate-induced drain leakage precharge;

and performing second-stage programming on the memory cells in the memory string which is subjected to the second-stage precharging.

16. The non-volatile memory system of claim 15, the controller further configured to:

17. The non-volatile memory system of claim 15, being a solid state hard disk or a memory card.