CN114974171A - Refresh rate control method and device based on display device, display terminal and medium - Google Patents

Refresh rate control method and device based on display device, display terminal and medium Download PDF

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Publication number
CN114974171A
CN114974171A CN202210233422.8A CN202210233422A CN114974171A CN 114974171 A CN114974171 A CN 114974171A CN 202210233422 A CN202210233422 A CN 202210233422A CN 114974171 A CN114974171 A CN 114974171A
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frame
input
refresh rate
storage areas
display
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CN114974171B (en
Inventor
梁宁
郭斌
黄秋升
付玉红
鲁文怡
梁桂孟
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Konka Group Co Ltd
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Konka Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a refresh rate control method, a refresh rate control device, a display terminal and a medium based on a display device, wherein the method comprises the following steps: acquiring input signals of a plurality of signal sources, wherein the input signals of the plurality of signal sources comprise a plurality of input signals with different input refresh rates; circularly storing input signal frames in a plurality of pre-divided frame storage areas in an interval jump mode; generating an insertion frame by adopting a bilinear interpolation algorithm, and inserting and storing the generated insertion frame into an interval frame storage area between every two corresponding adjacent input frames; and when reading the frame, controlling the input frame writing speed and the output frame reading speed according to the input refresh rate of the input information source and the output refresh rate of the application scene. The invention provides a configurable refresh rate control method for realizing 8K ultra-high definition 50-240 Hz, which enables a moving picture to be smoother and clearer, can reduce the problems of motion smear and motion jitter, and can avoid the frame tearing phenomenon.

Description

Refresh rate control method and device based on display device, display terminal and medium
Technical Field
The present invention relates to the field of display terminal technologies, and in particular, to a refresh rate control method and apparatus based on a display device, a display terminal, and a medium.
Background
With the development of electronic technology and the continuous improvement of living standard of people, the use of various display terminals such as smart televisions is more and more popular, and the smart televisions have become indispensable communication tools in people's lives.
The development of the video and audio industry aims to pursue more perfect and clear images and sound, particularly in the display field, the resolution is promoted to be continuously improved by the digitalization process, and the popularization of ultra high definition 4K televisions and the promotion of ultra high definition 8K televisions show the rapid development trend of the current television and video and audio industries, particularly, the video and audio effect with high refresh rate of 8K-120Hz is excellent, and the video and audio system becomes one of the hot points concerned by consumers.
At present, the development of the display industry before and after an 8K-120Hz ecological chain is unbalanced, the highest quality of a front-end program information source is only 8K-60Hz, and a rear-end 8K-120Hz display module is mature and produced in mass. In addition, in the field of electronic competitions, the refresh rate of game software pictures is designed according to the highest refresh rate 144Hz which can be sensed by human eyes, so that the refresh rate of the display special for the electronic competitions is up to 144Hz or even 240 Hz. The prior art has display devices with schemes of 8K-60Hz and 8K-120Hz, but the refresh rate is fixed, the use is not flexible enough, and the problems of motion smear and motion jitter are easy to occur.
Thus, there is still a need for improvement and development of the prior art.
Disclosure of Invention
The invention mainly aims to provide a refresh rate control method, a device, a display terminal and a computer readable storage medium based on a display device, and provides a configurable refresh rate control method for realizing 8K ultra-high definition 50-240 Hz.
In order to achieve the above object, a first aspect of the present invention provides a refresh rate control method based on a display device, wherein the method comprises:
acquiring input signals of a plurality of signal sources, wherein the input signals of the plurality of signal sources comprise a plurality of input signals with different input refresh rates;
circularly storing the acquired input signals of the multi-channel information source in a plurality of pre-divided frame storage areas in an interval jumping mode according to the time sequence of input signal frames;
generating an insertion frame between every two stored adjacent input frames by adopting a bilinear interpolation algorithm, and inserting and storing the generated insertion frame into an interval frame storage area between every two corresponding adjacent input frames;
when reading the frame, controlling the input frame writing speed and the reading speed of the output frame according to the input refreshing rate of the input information source and the output refreshing rate of the application scene; sequentially reading and outputting the input frame and the insertion frame stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed;
and driving the display panel to display by the read display data.
The method for controlling the refresh rate based on the display device, wherein the step of obtaining the input signals of the multiple signal sources, wherein the input signals of the multiple signal sources comprise a plurality of input signals with different input refresh rates, comprises the following steps:
the storage area of the storage unit is divided into a plurality of frame storage areas in advance, wherein the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses.
The method for controlling the refresh rate based on the display device, wherein the step of obtaining the input signals of the multiple signal sources, wherein the input signals of the multiple signal sources comprise a plurality of input signals with different input refresh rates, comprises the steps of:
receiving and acquiring input signals of multiple signal sources through FPGA boards arranged on a main circuit board and a display screen, wherein the input signals of the multiple signal sources comprise multiple input signals with different input refresh rates.
The refresh rate control method based on the display device, wherein the step of cyclically storing the acquired input signals of the multiple signal sources in a plurality of pre-divided frame storage areas in an interval jump manner according to the time sequence of the input signal frames comprises the following steps:
the acquired input signals of the multi-channel information source are sequentially stored at intervals in a jumping mode in a plurality of pre-divided frame storage areas according to the time sequence of input signal frames; and storing the frame in the plurality of pre-divided frame storage areas at cyclic intervals;
each frame storage area in the plurality of pre-divided frame storage areas is provided with a 1-bit effective bit wn; when the storage of a certain frame storage area n is finished, setting wn to 1; when the reading of a certain frame of storage area n is completed, the reset wn is equal to 0.
The refresh rate control method based on the display device is characterized in that when the frame is read, the input frame writing speed is controlled and the output frame reading speed is controlled according to the input refresh rate of an input information source and the output refresh rate of an application scene; and sequentially reading and outputting the input frames and the insertion frames stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed, including:
when reading the frame, setting an output refresh rate Y according to an application scene;
determining an input refresh rate X according to the selected input information source;
judging the magnitude of an output refresh rate Y and an input refresh rate X;
when the output refresh rate Y is more than 2 times the input refresh rate X, controlling the next processing frame wn to be 0, and repeatedly reading the current frame;
when the output refresh rate Y is 2 times of the input refresh rate X, the frames are read according to the continuous area in a circulating mode;
when the output refresh rate Y is less than 2 times the input refresh rate X, controlling to ignore if the current frame is an insertion frame when the next processing frame wn is 1; if the current frame is an input frame, the current input frame is repeatedly written.
A refresh rate control apparatus based on a display apparatus, comprising:
the device comprises a signal acquisition module, a signal processing module and a signal processing module, wherein the signal acquisition module is used for acquiring input signals of multiple signal sources, and the input signals of the multiple signal sources comprise multiple input signals with different input refresh rates;
the input frame skipping storage control module is used for circularly storing the acquired input signals of the multi-channel information sources in a plurality of pre-divided frame storage areas in an interval skipping mode according to the time sequence of the input signal frames;
the insertion frame generation and storage control module is used for generating an insertion frame between every two stored adjacent input frames by adopting a bilinear interpolation algorithm and inserting and storing the generated insertion frame into an interval frame storage area between every two corresponding adjacent input frames;
the refresh rate control module is used for controlling the input frame writing speed and the output frame reading speed according to the input refresh rate of the input information source and the output refresh rate of the application scene when reading the frame; sequentially reading and outputting the input frame and the insertion frame stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed;
and the display module is used for driving the read display data to display on the display panel.
The refresh rate control device based on the display device, wherein, it also includes:
the device comprises a presetting module, a data processing module and a data processing module, wherein the presetting module is used for dividing a storage area of a storage unit into a plurality of frame storage areas in advance, the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses.
A display terminal, wherein the display terminal comprises:
the system comprises a main board, an FPGA board, a memory and a display panel; the main board, the FPGA board and the display panel are connected in sequence; the memory is connected with the FPGA board, and a processor is arranged on the mainboard; the storage area of the memory is divided into a plurality of frame storage areas, wherein the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses;
the memory has stored thereon a display device based refresh rate control program operable on the processor, the display device based refresh rate control program when executed by the processor implementing any of the steps of the display device based refresh rate control method.
A computer readable storage medium having a display device based refresh rate control program stored thereon, which when executed by a processor implements any one of the steps of the display device based refresh rate control method.
The invention provides a refresh rate control method, a device, a display terminal and a computer readable storage medium based on a display device, and provides a configurable refresh rate control method for realizing 8K ultra high definition 50-240 Hz.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a schematic block of a display terminal according to an embodiment of the present invention.
Fig. 2 is a flowchart illustrating a refresh rate control method based on a display device according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating a frame sequence saving and reading according to a refresh rate control method for a display device according to an embodiment of the present invention.
Fig. 4 is a flowchart illustrating a refresh rate control method based on a display device according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of a refresh rate control apparatus based on a display device according to an embodiment of the present invention.
Fig. 6 is a schematic block diagram of an internal structure of a display terminal according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular device structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known devices, apparatuses, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.
As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when …" or "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted depending on the context to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings of the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
The development of the video and audio industry aims to pursue more perfect and clear images and sound, particularly in the display field, the resolution is promoted to be continuously improved by the digitalization process, and the popularization of ultra high definition 4K televisions and the promotion of ultra high definition 8K televisions show the rapid development trend of the current television and video and audio industries, particularly, the video and audio effect with high refresh rate of 8K-120Hz is excellent, and the video and audio system becomes one of the hot points concerned by consumers.
In the prior art, the display industry is unbalanced in the forward and backward development of an ecological chain of 8K-120Hz, the highest quality of a front-end program information source is only 8K-60Hz, and a rear-end 8K-120Hz display module is mature and produced in mass production. In addition, in the field of electronic contests, the refresh rate of game software pictures is designed according to the highest refresh rate 144Hz which can be sensed by human eyes, so the refresh rate of the display special for the electronic contest is up to 144Hz or even 240 Hz. However, the prior art has display devices with schemes of 8K-60Hz and 8K-120Hz, the refresh rate is fixed, and the use is not flexible enough.
In order to solve the problems of the prior art, the embodiment of the invention provides a refresh rate control method and device based on a display device, a display terminal and a medium, and provides a configurable refresh rate display device which can realize 8K ultra-high definition 50-240 Hz, has the highest refresh rate of 240Hz output and drives a display panel, ensures the truest and exquisite display effect, and can reduce the problems of motion smear and motion jitter, so that a motion picture is smoother and clearer.
Exemplary devices
A display terminal of an embodiment of the present invention includes: the system comprises a main board, an FPGA board, a memory and a display panel; the main board, the FPGA board and the display panel are connected in sequence; the memory is connected with the FPGA board, and a processor is arranged on the mainboard; the storage area of the memory is divided into a plurality of frame storage areas.
In the preferred embodiment of the present invention, the display terminal is described by taking a television as an example, then the motherboard is a television motherboard 20, the memory is a DDR memory unit 22, as shown in fig. 1, the display terminal in the preferred embodiment of the present invention includes: a television main board 20, an FPGA board 21, a DDR memory unit 22, a display panel 23, a switching power supply 24, a speaker 25, a remote controller 26, and various external source interfaces such as an HDMI interface, a network cable interface, and the like. The television main board 20, the FPGA board 21 and the display panel 23 are connected in sequence; the DDR storage unit 22 is connected with the FPGA board 21, and the television main board 20 is further connected with a loudspeaker 25; the switching power supply 24 is respectively connected with the television main board 20 and the display panel 23, and is configured to provide a working power supply for the television main board 20 and the display panel 23. The FPGA board is also connected with an HDMI2.1 interface, a DP1.4 interface and a network port respectively.
The FPGA board 21 can receive VByOne image signals from a television mainboard, can also receive signals of HDMI2.1 and DP1.4 interfaces, and receives 8KAVS3 code streams through a network port. VbyOne is a digital interface standard developed specifically for image transmission. The input and output level of the signal adopts LVDS (Low Voltage differential Signal). AVS3 video coding standard is the third generation video coding standard established by AVS working group in China.
The FPGA board 21 outputs display data to drive the display panel according to the embodiment of the present invention, and the refresh rate of the display panel is fixed, for example, 8K50Hz or 60Hz, or 8K100Hz or 120 Hz. As can be seen, the input sources of the FPGA board are diversified, so that the input refresh rates of the FPGA board are also diversified, such as 24Hz, 30Hz, 48Hz, 50Hz, 60Hz and the like. The output refresh rate is fixed in a particular application, but different application scenarios, the output refresh rate is configurable, e.g., a 120Hz panel is driven, the output refresh rate is required to be 120Hz, a 144Hz panel is driven, the output refresh rate is required to be 144Hz, and so on.
Under general conditions, the input information sources of the FPGA board are diversified, so that the input refresh rate of the FPGA board is also diversified; while the output refresh rate is fixed in a particular application, but is configurable for different application scenarios. However, in general, the output is asynchronous with respect to the input, i.e. there is no phase locking relationship between the output frame and the input frame, and there is a possibility of "frame tearing" phenomenon, i.e. one frame is divided into 2 parts and displayed successively in two frames. In order to avoid the phenomenon of "frame tearing", the following methods are further proposed in the embodiment of the present invention:
as shown in fig. 2, the present invention further provides a specific application embodiment of a refresh rate control method based on a display device, where the refresh rate control method based on a display device of the specific application embodiment includes the following steps:
step S100: the storage area of the storage unit is divided into a plurality of frame storage areas in advance, wherein the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses.
In the embodiment of the present invention, an FPGA board needs to be additionally disposed between the television main board 20 and the display panel 23 of the display terminal, such as the smart television, and the FPGA board is connected to the television main board 20 and the display panel 23 respectively. When the present invention is embodied, the storage area of the storage unit is divided into a plurality of frame storage areas, for example, N frame storage areas 0 to N-1(N is 4 to 8), each area has the same capacity size, at least one frame of screen can be stored, and the addresses in the area are continuous, and the frame storage area is represented by the top address. For example, when the storage area of the storage unit is divided into 8 frame storage areas, there are a frame storage area 0, a frame storage area 1, a frame storage area 2, a frame storage area 3, a frame storage area 4, a frame storage area 5, a frame storage area 6, and a frame storage area 7, respectively.
Step S200: acquiring input signals of a plurality of information sources, wherein the input signals of the plurality of information sources comprise a plurality of input signals with different input refresh rates;
in the embodiment of the present invention, in a specific implementation, the input signals of multiple signal sources may be received and obtained through the FPGA board disposed between the main circuit board and the display screen, for example, as shown in fig. 1, the FPGA board 21 disposed between the television main board 20 and the display panel 23, where the input signals of the multiple signal sources include multiple input signals with different input refresh rates, for example, VByOne image signals from the television main board may be received, signals of HDMI2.1 and DP1.4 interfaces may also be received, and 8K AVS3 code streams may be received through the network interface. Thus, the input sources of the FPGA board 21 in the embodiment of the present invention are diversified, which results in the diversification of the input refresh rates thereof, such as 24Hz, 30Hz, 48Hz, 50Hz, 60Hz, and the like.
Step S300: according to the time sequence of input signal frames, the input signal frames are circularly stored in a plurality of pre-divided frame storage areas in an interval jumping mode;
according to the embodiment of the invention, the acquired input signals of the multi-channel information source are circularly stored in a plurality of pre-divided frame storage areas in an interval jump type mode according to the time sequence of the input signal frames.
Specifically, for example, the acquired input signals of the multiple signal sources are sequentially stored at intervals in a jumping manner in a plurality of pre-divided frame storage areas according to the time sequence of the input signal frames; and storing the frame in the plurality of pre-divided frame storage areas at cyclic intervals; specifically, as shown in fig. 3, taking N as an example, when the storage area is divided into 8 frame storage areas, the frame storage areas are respectively a frame storage area W0, a frame storage area W1, a frame storage area W2, a frame storage area W3, a frame storage area W4, a frame storage area W5, a frame storage area W6, and a frame storage area W7, in the embodiment of the present invention, the input frames of the input signals of the multiple sources are stored in the frame storage areas 0, 2, 4, 6, 0, 2, 4, and 6 at a jumping interval, and are stored in a circulating manner.
In the embodiment of the invention, each frame storage area in the plurality of pre-divided frame storage areas is provided with a 1-bit effective bit wn; when the storage of a certain frame storage area n is finished, setting wn to 1; when the reading of a certain frame of storage area n is completed, the reset wn is equal to 0.
Step S400: generating an insertion frame between every two stored adjacent input frames by adopting a bilinear interpolation algorithm, and inserting and storing the generated insertion frame into an interval frame storage area between every two corresponding adjacent input frames;
that is, in the embodiment of the present invention, as shown in fig. 3, an interpolated frame is generated between each two adjacent input frames stored in the input frame sequence, for example, W0 and W2, W2 and W4, and W4 and W6, by using a bilinear interpolation algorithm, and the generated interpolated frame is interpolated and stored in an inter-frame storage area between each two adjacent input frames, that is, the correspondingly generated interpolated frame is stored in the frame storage area W1, the frame storage area W3, the frame storage area W5, and the frame storage area W7, respectively. That is, 1 interpolated frame is generated by using a bilinear interpolation algorithm every 2 adjacent input frames, and the interpolated frames are stored cyclically according to the area 13571357.
Step S500: when reading the frame, controlling the input frame writing speed and the reading speed of the output frame according to the input refreshing rate of the input information source and the output refreshing rate of the application scene; sequentially reading and outputting the input frame and the insertion frame stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed;
specifically, the step S500 includes:
when reading the frame, setting an output refresh rate Y according to an application scene;
determining an input refresh rate X according to the selected input information source;
judging the magnitude of an output refresh rate Y and an input refresh rate X;
when the output refresh rate Y is more than 2 times the input refresh rate X, controlling the next processing frame wn to be 0, and repeatedly reading the current frame; that is, when Y >2X, it means that the reading speed is greater than the writing speed, and when the next processing frame wn equals 0, the current frame is repeatedly read, which is equivalent to reducing the reading speed, and the output and input are controlled to be synchronous, that is, the output frame and the input frame realize a phase locking relationship, so that the problems of motion smear and motion jitter can be reduced, and the frame tearing phenomenon can be avoided.
When the output refresh rate Y is 2 times of the input refresh rate X, the frames are read according to the continuous area in a circulating mode; when Y is 2X, it indicates that the writing speed is equal to the reading speed, and the reading and writing do not need to be repeated or wait;
when the output refresh rate Y is less than 2 times the input refresh rate X, controlling to ignore if the current frame is an insertion frame when the next processing frame wn is 1; if the current frame is an input frame, the current input frame is repeatedly written. That is, when Y <2X, it indicates that the writing speed is greater than the reading speed, and when the next processing frame wn is 1, if the current frame is an insertion frame, it is directly ignored; if the current frame is an input frame, the current input frame is repeatedly written, which is equivalent to reducing the writing speed. The output and the input are controlled to be synchronous, namely, the phase locking relation between the output frame and the input frame is realized, the problems of motion smear and motion jitter can be reduced, and the frame tearing phenomenon can be avoided.
Step S600: and driving the display panel to display by the read display data.
Therefore, the embodiment of the invention improves the fluency of the video and controls the output and the input to be synchronous according to the judgment method of the frame insertion technology, namely the output frame and the input frame realize the phase locking relation, thereby reducing the problems of motion smear and motion jitter and avoiding the frame tearing phenomenon.
The process of the invention is described in further detail below by means of a specific application example:
as shown in fig. 4, a refresh rate control method based on a display device according to this embodiment includes the following steps:
step S31: a memory of a display terminal is divided into N frame memory areas 0 to N-1(N is 4 to 8) by a DDR memory unit, for example. The capacity of each frame storage area is the same, at least one frame picture can be stored, and the addresses in the area are continuous. Thus, the frame storage area can be represented using the first address. Taking N as an example, the input frame is cyclically stored by regions 0, 2, 4, 6, 0, 2, 4, 6; and generating 1 insertion frame by adopting a bilinear interpolation algorithm every 2 adjacent input frames, and circularly storing the insertion frames according to the areas 1, 3, 5, 7, 1, 3, 5 and 7. As shown in fig. 4, fig. 4 is a schematic diagram of saving and reading a frame sequence.
In the embodiment of the invention, the bilinear interpolation is linear interpolation expansion of an interpolation function with two variables, and the core idea is to perform linear interpolation in two directions once respectively.
In the embodiment of the present invention, regarding the input frame and the insertion frame, specifically, the following are performed: by adjacent input frames, 1 interpolated frame is generated, all data stored per frame. The camera produces input frames and the interpolated frames are the counted intermediate virtual frames.
In step S32, an identification bit, for example, a 1-bit identification bit (valid bit) wn (N is 0 to N-1, for example, 0 to 7) is introduced for each memory area. In the embodiment of the invention, the 1bit identification bit is used for identifying whether reading is finished or not. 1bit valid bit and the store complete is set to 1. The read completion is set to 0.
Step S33, nth storage area; the writing completion set wn is 1, and the reading completion reset wn is 0;
that is, in the embodiment of the present invention, when the storage in a certain frame storage region n is completed, the set wn is equal to 1, which indicates that the storage in the n region is completed, and the n region can be read. As shown in fig. 3, since the frame sequences w0 to w7 are time-sequentially incremented sequences by the "jump" storage, the frame read only needs to be performed cyclically by the regions 01234567, and when the read of a certain region n is completed, the reset wn is equal to 0, which indicates that the read of the region n is completed, and the write is possible.
In the embodiment of the invention, each frame storage area can be read only after the storage is finished, and only 1 frame (input frame or insertion frame) is stored in one frame storage area.
In the embodiment of the present invention, when reading a frame, only reading the frame in cycles according to the region 01234567, for example: the input frames are stored cyclically in regions 02460246, and are read in time increasing order from regions 01234567.
Step S34: and setting an output refresh rate Y according to the application scene.
In the embodiment of the invention, when reading is needed, the output refresh rate Y is set according to the application scene.
Step S35: selecting an input information source, determining an input refresh rate X, and comparing the magnitude relation of the input refresh rate X and the output refresh rate Y.
Step S36: when the output refresh rate Y >2 and the input refresh rate X indicate that the read speed is greater than the write speed, if the next processing frame wn is 0, the current frame is repeatedly read, which corresponds to a decrease in the read speed.
When Wn is equal to 1, it indicates that writing is completed, and the next processing frame is not read.
The equivalent reduction of the reading speed is specifically: for example, when Y is 144Hz and X is 60Hz, the effective reading speed is 2 × 60Hz, and the remaining 24Hz portion is the repeat reading; for another example, when Y is 165Hz and X is 60Hz, the effective reading speed is also 2 × 60Hz, and the remaining 45Hz portion is the repeat reading; that is, since the effective reading speed is 2 writing speed, there is a phenomenon that reading is repeated when the output refresh rate Y >2 and the input refresh rate X.
Step S37: when the output refresh rate Y is equal to the input refresh rate 2X, it indicates that the write speed is equal to the read speed, and the read and write do not need to be repeated or wait.
Step S38: when the output refresh rate Y is less than 2 and the input refresh rate X is greater than the reading speed, if the current frame is an insertion frame, the current frame is directly ignored, namely, the current frame is not written when the next processing frame wn is 1; if the current frame is an input frame, the current input frame is repeatedly written, which corresponds to reducing the writing speed. For example, when Y is 100Hz and X is 60Hz, then the 2-write speed is 2 × 60Hz, the read speed is 100Hz, the apparent write speed 120 is greater than the read speed 100, and in order to ensure that the effective write and the effective read are balanced, the remaining 20Hz portion is the repeated write.
Step S39: and driving the display panel to display by the read display data.
Therefore, the embodiment of the invention improves the fluency of the video and controls the output and the input to be synchronous according to the judgment method of the frame insertion technology, namely the output frame and the input frame realize the phase locking relation, thereby reducing the problems of motion smear and motion jitter and avoiding the frame tearing phenomenon.
Based on the above embodiment, as shown in fig. 5, the present invention further provides a refresh rate control device based on a display device, including:
a signal obtaining module 510, configured to obtain input signals of multiple signal sources, where the input signals of the multiple signal sources include input signals with multiple different input refresh rates;
an input frame skip storage control module 520, configured to cyclically store the acquired input signals of the multiple signal sources in a plurality of pre-divided frame storage areas in an interval skip manner according to a time sequence of input signal frames;
an insert frame generation and storage control module 530, configured to generate an insert frame by using a bilinear interpolation algorithm between every two stored adjacent input frames, and insert and store the generated insert frame in an inter-frame storage area between every two corresponding adjacent input frames;
the refresh rate control module 540 is used for controlling the input frame writing speed and the output frame reading speed according to the input refresh rate of the input information source and the output refresh rate of the application scene during frame reading; sequentially reading and outputting the input frame and the insertion frame stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed;
the display module 550 is configured to drive the display panel to display the read display data, as described above.
Further, the refresh rate control device based on a display device further comprises:
a presetting module 501, configured to divide a storage area of a storage unit into a plurality of frame storage areas in advance, where a capacity of each frame storage area in the plurality of frame storage areas is equal, addresses in the plurality of frame storage areas are consecutive addresses, and a frame storage area is represented by a first address, which is specifically described above.
Based on the above embodiments, the present invention further provides a display terminal, and a schematic block diagram thereof may be as shown in fig. 4. The display terminal comprises a main board, an FPGA board, a memory and a display panel; the main board, the FPGA board and the display panel are connected in sequence; the memory comprises a DDR memory (double-rate synchronous dynamic random access memory) and a nonvolatile storage medium, the DDR memory is connected with the FPGA board, and a processor is arranged on the mainboard; the storage area of a DDR memory in the memory is divided into a plurality of frame storage areas, wherein the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses;
the processor, the FPGA board and the network interface of the display terminal are connected through a system bus. Wherein the processor of the display terminal is configured to provide computing and control capabilities. The memory of the display terminal comprises a nonvolatile storage medium and a DDR memory. The non-volatile storage medium stores an operating system and a refresh rate control program based on a display device. The internal memory provides an environment for the operating system in the non-volatile storage medium and the operation of the refresh rate control program based on the display device. The network interface of the display terminal is used for connecting and communicating with an external terminal through a network. The display device based refresh rate control program, when executed by a processor, implements the steps of any of the display device based refresh rate control methods described above. The display screen of the display terminal can be a liquid crystal display screen or an electronic ink display screen.
It will be understood by those skilled in the art that the schematic block diagram shown in fig. 5 is only a block diagram of a part of the structure related to the solution of the present invention, and does not constitute a limitation of the display terminal to which the solution of the present invention is applied, and a specific display terminal may include more or less components than those shown in the figure, or combine some components, or have a different arrangement of components.
In one embodiment, a display terminal is provided, where the display terminal includes a memory, a processor, and a display device-based refresh rate control program stored in the memory and executable on the processor, and the display device-based refresh rate control program performs the following instructions when executed by the processor:
acquiring input signals of a plurality of information sources, wherein the input signals of the plurality of information sources comprise a plurality of input signals with different input refresh rates;
circularly storing the acquired input signals of the multi-channel information source in a plurality of pre-divided frame storage areas in an interval jumping mode according to the time sequence of input signal frames;
generating an insertion frame between every two stored adjacent input frames by adopting a bilinear interpolation algorithm, and inserting and storing the generated insertion frame into an interval frame storage area between every two corresponding adjacent input frames;
when reading the frame, controlling the input frame writing speed and the output frame reading speed according to the input refreshing rate of the input information source and the output refreshing rate of the application scene; sequentially reading and outputting the input frame and the insertion frame stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed;
and driving the display panel to display by the read display data.
Wherein, the step of obtaining the input signals of the multiple signal sources, wherein the input signals of the multiple signal sources include a plurality of input signals with different input refresh rates, comprises:
the storage area of the storage unit is divided into a plurality of frame storage areas in advance, wherein the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses.
Wherein the step of obtaining the input signals of the multiple sources, wherein the input signals of the multiple sources include input signals of a plurality of different input refresh rates comprises:
receiving and acquiring input signals of multiple signal sources through FPGA boards arranged on a main circuit board and a display screen, wherein the input signals of the multiple signal sources comprise multiple input signals with different input refresh rates.
The step of circularly storing the acquired input signals of the multiple signal sources in a plurality of pre-divided frame storage areas in an interval jump manner according to the time sequence of input signal frames comprises:
sequentially storing the acquired input signals of the multi-channel information sources at intervals by adopting a jumping mode in a plurality of pre-divided frame storage areas according to the time sequence of input signal frames; and storing the frame in the plurality of pre-divided frame storage areas at cyclic intervals;
each frame storage area in the plurality of pre-divided frame storage areas is provided with a 1-bit effective bit wn; when the storage of a certain frame storage area n is finished, setting wn to 1; when the reading of a certain frame of storage area n is completed, the reset wn is equal to 0.
When the frame is read, controlling the input frame writing speed and controlling the reading speed of the output frame according to the input refresh rate of the input information source and the output refresh rate of the application scene; and sequentially reading and outputting the input frames and the insertion frames stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed, including:
when reading the frame, setting an output refresh rate Y according to an application scene;
determining an input refresh rate X according to the selected input information source;
judging the magnitude of an output refresh rate Y and an input refresh rate X;
when the output refresh rate Y is more than 2 times the input refresh rate X, controlling the next processing frame wn to be 0, and repeatedly reading the current frame;
when the output refresh rate Y is 2 times of the input refresh rate X, the frames are read according to the continuous area in a circulating mode;
when the output refresh rate Y is less than 2 times the input refresh rate X, controlling to ignore if the current frame is an insertion frame when the next processing frame wn is 1; if the current frame is an input frame, the current input frame is repeatedly written.
In summary, the invention provides a refresh rate control method, a device, a display terminal and a computer readable storage medium based on a display device, and the invention provides a configurable refresh rate control method for realizing 8K ultra high definition 50-240 Hz, and the refresh rate of the invention can reach 240Hz output and drive a display panel, thereby ensuring the most real and exquisite display effect, and simultaneously reducing the problems of motion smear and motion jitter.
Based on the foregoing embodiments, an embodiment of the present invention further provides a computer-readable storage medium, where a refresh rate control program based on a display device is stored in the computer-readable storage medium, and when the refresh rate control program based on the display device is executed by a processor, the steps of any one of the refresh rate control methods based on the display device provided in the embodiments of the present invention are implemented.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned functions may be distributed as different functional units and modules according to needs, that is, the internal structure of the apparatus may be divided into different functional units or modules to implement all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only used for distinguishing one functional unit from another, and are not used for limiting the protection scope of the present invention. The specific working processes of the units and modules in the above-mentioned apparatus may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art would appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the above modules or units is only one logical function division, and the actual implementation may be implemented by another division manner, for example, a plurality of units or components may be combined or integrated into another apparatus, or some features may be omitted, or not executed.
The integrated modules/units described above, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the embodiments of the present invention may also be implemented by a computer program, which may be stored in a computer-readable storage medium and can implement the steps of the embodiments of the method when the computer program is executed by a processor. The computer program includes computer program code, and the computer program code may be in a source code form, an object code form, an executable file or some intermediate form. The computer readable medium may include: any entity or device capable of carrying the above-mentioned computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signal, telecommunication signal, software distribution medium, etc. It should be noted that the contents contained in the computer-readable storage medium can be increased or decreased as required by legislation and patent practice in the jurisdiction.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art; the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced, for example, products that can be applied to monitors, security trackers, and the like may be expanded; such modifications and substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein.

Claims (9)

1. A method for controlling a refresh rate of a display device, the method comprising:
acquiring input signals of a plurality of information sources, wherein the input signals of the plurality of information sources comprise a plurality of input signals with different input refresh rates;
circularly storing the acquired input signals of the multi-channel information source in a plurality of pre-divided frame storage areas in an interval jumping mode according to the time sequence of input signal frames;
generating an insertion frame between every two stored adjacent input frames by adopting a bilinear interpolation algorithm, and inserting and storing the generated insertion frame into an interval frame storage area between every two corresponding adjacent input frames;
when reading the frame, controlling the input frame writing speed and the reading speed of the output frame according to the input refreshing rate of the input information source and the output refreshing rate of the application scene; sequentially reading and outputting the input frame and the insertion frame stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed;
and driving the display panel to display by the read display data.
2. The method of claim 1, wherein the step of obtaining input signals from multiple sources, wherein the input signals from the multiple sources comprise input signals at multiple different input refresh rates is preceded by the step of:
the storage area of the storage unit is divided into a plurality of frame storage areas in advance, wherein the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses.
3. The method of claim 1, wherein the step of obtaining input signals of multiple sources, wherein the input signals of the multiple sources comprise input signals of multiple different input refresh rates comprises:
receiving and acquiring input signals of multiple signal sources through FPGA boards arranged on a main circuit board and a display screen, wherein the input signals of the multiple signal sources comprise multiple input signals with different input refresh rates.
4. The display device-based refresh rate control method of claim 1, wherein the step of cyclically storing the acquired input signals of the multiple sources in a time sequence of input signal frames in interval jumping manner in a plurality of frame storage areas divided in advance comprises:
sequentially storing the acquired input signals of the multi-channel information sources at intervals by adopting a jumping mode in a plurality of pre-divided frame storage areas according to the time sequence of input signal frames; and the frame is stored in a plurality of frame storage areas which are divided in advance at cyclic intervals;
each frame storage area in the plurality of pre-divided frame storage areas is provided with a 1-bit effective bit wn; when the storage of a certain frame storage area n is finished, setting wn to 1; when the reading of a certain frame of storage area n is completed, the reset wn is equal to 0.
5. The refresh rate control method according to claim 1, wherein the frame reading controls an input frame writing speed and controls an output frame reading speed according to an input refresh rate of an input source and an output refresh rate of an application scene; and sequentially reading and outputting the input frames and the insertion frames stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed, including:
when reading the frame, setting an output refresh rate Y according to an application scene;
determining an input refresh rate X according to the selected input information source;
judging the magnitude of an output refresh rate Y and an input refresh rate X;
when the output refresh rate Y is more than 2 times the input refresh rate X, controlling the next processing frame wn to be 0, and repeatedly reading the current frame;
when the output refresh rate Y is 2 times of the input refresh rate X, the frames are read according to the continuous area in a circulating mode;
when the output refresh rate Y is less than 2 times the input refresh rate X, when the next processing frame wn is 1, if the current frame is an insertion frame, ignoring; if the current frame is an input frame, the current input frame is repeatedly written.
6. A refresh rate control apparatus based on a display apparatus, comprising:
the device comprises a signal acquisition module, a signal processing module and a signal processing module, wherein the signal acquisition module is used for acquiring input signals of multiple signal sources, and the input signals of the multiple signal sources comprise multiple input signals with different input refresh rates;
the input frame jumping storage control module is used for circularly storing the acquired input signals of the multipath information sources in a plurality of pre-divided frame storage areas in an interval jumping mode according to the time sequence of the input signal frames;
the device comprises an insertion frame generation and storage control module, a frame generation and storage module and a frame extraction and extraction module, wherein the insertion frame generation and storage control module is used for generating an insertion frame between every two stored adjacent input frames by adopting a bilinear interpolation algorithm and inserting and storing the generated insertion frame into an interval frame storage area between every two corresponding adjacent input frames;
the refresh rate control module is used for controlling the input frame writing speed and the output frame reading speed according to the input refresh rate of the input information source and the output refresh rate of the application scene when reading the frame; sequentially reading and outputting the input frame and the insertion frame stored in the plurality of frame storage areas as display data based on the controlled input frame writing speed and the controlled output frame reading speed;
and the display module is used for driving the read display data to display on the display panel.
7. The display device-based refresh rate control apparatus of claim 6, further comprising:
the device comprises a presetting module, a data processing module and a data processing module, wherein the presetting module is used for dividing a storage area of a storage unit into a plurality of frame storage areas in advance, the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses.
8. A display terminal, characterized in that the display terminal comprises:
the system comprises a main board, an FPGA board, a memory and a display panel; the main board, the FPGA board and the display panel are connected in sequence; the memory is connected with the FPGA board, and a processor is arranged on the mainboard; the storage area of the memory is divided into a plurality of frame storage areas, wherein the capacity of each frame storage area in the plurality of frame storage areas is equal, the addresses in the plurality of frame storage areas are continuous addresses, and the frame storage areas are represented by adopting first addresses;
the memory having stored thereon a display device based refresh rate control program executable on the processor, the display device based refresh rate control program when executed by the processor implementing the steps of the display device based refresh rate control method according to any one of claims 1-5.
9. A computer-readable storage medium, having a display device-based refresh rate control program stored thereon, wherein the display device-based refresh rate control program, when executed by a processor, implements the steps of the display device-based refresh rate control method according to any one of claims 1-5.
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