CN114972553A - Pixel address coding circuit with time information suitable for SPAD array - Google Patents
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Abstract
The invention provides a pixel address coding circuit with time information, which is suitable for an SPAD array. The circuit comprises an SPAD detection array consisting of N SPAD detection units, 2 delay chains, 2 TDC circuits and a readout circuit, wherein the SPAD detection units are used for detecting photons and outputting voltage pulses; 2 delay chains transmit delay in opposite directions, each delay chain comprises N basic delay units with delay time tau, each SPAD detection unit is connected with the corresponding basic delay unit in the 2 delay chains at the same time, and voltage pulses output by the SPAD detection units are transmitted in the 2 delay chains in opposite directions at the same time; the tail ends of the 2 delay chains are respectively connected with 1 TDC circuit; the readout circuit reads data of 2 TDC circuits. The invention adopts a digitization circuit scheme, has simple structure, does not need a special decoding circuit to extract address data, and can directly obtain pixel address information through calculation.
Description
Technical Field
The invention relates to the field of integrated circuits of single photon avalanche diode detector arrays, in particular to a pixel address coding circuit with time information, which is suitable for an SPAD array.
Background
The single Photon Avalanche diode SPAD (Single Photon Avalanche diode) as a photoelectric detection device has the characteristics of fast response, high gain and the like. The SPAD device works in a Geiger mode, and when the SPAD detects photon input, a pulse signal is output under the combined action of the quenching circuit. The pulse signal has extremely short rise time, can effectively carry time information through a shaping circuit, and is commonly used for flight time ranging type laser radars.
In the integration process of the SPAD array, the matching problem between the SPAD device and the TDC circuit needs to be considered, and a mode that one TDC circuit is configured for a single pixel or one column of TDC circuits is configured for a pixel area array is generally adopted. However, the mode of configuring one TDC circuit for a single pixel has the disadvantages of large array layout area, low pixel duty ratio, high power consumption, and the like; the way of configuring one pixel area array with one row of TDC circuits has the disadvantage that the area array cannot operate simultaneously. Therefore, a pixel address coding circuit with time information, which is suitable for an SPAD array, is needed, a mode that a plurality of TDC circuits are configured on the SPAD array is adopted, and position information of a device which responds is reversely deduced through address coding information, so that the array works simultaneously, the layout area is reduced, the pixel duty ratio is improved, and the power consumption is also reduced. If the existing coding circuit is realized by adopting combinational logic, the generally needed circuit is more complex and needs to be matched with a special decoding circuit; if the circuit is realized by adopting analog modes such as resistance voltage division and the like, the response speed of the circuit is slow, and certain static power consumption exists.
Disclosure of Invention
The invention provides a pixel address coding circuit with time information, which is suitable for an SPAD array and aims to solve the problems of device and circuit matching in the array integration process of an SPAD detector and the defects of the existing address coding circuit.
The technical scheme adopted by the invention is as follows:
a pixel address coding circuit with time information suitable for an SPAD array comprises the SPAD detection array consisting of N SPAD detection units, 2 delay chains, 2 TDC circuits and a readout circuit, wherein the SPAD detection units are used for detecting photons and outputting voltage pulses; the 2 delay chains transmit delay in opposite directions, each delay chain comprises N basic delay units with delay time of tau, each SPAD detection unit is simultaneously connected with the corresponding basic delay unit in the 2 delay chains, and voltage pulses output by the SPAD detection units are simultaneously transmitted in opposite directions in the 2 delay chains; the tail ends of the 2 delay chains are respectively connected with 1 TDC circuit; the reading circuit reads data of 2 TDC circuits, and pixel address information and pulse time information are obtained through calculation.
Furthermore, each delay chain adopts two input OR gates as a basic delay unit, the first input ends of the two input OR gates are connected to the output end of the SPAD detection unit, the second input ends of the two input OR gates are connected to the output ends of the two input OR gates at the first stage, the output ends of the two input OR gates are connected to the second input ends of the two input OR gates at the next stage, and the two input OR gates in a row are connected in the above manner to form one delay chain; the second input end of the first-stage two-input OR gate of the delay chain is grounded and always inputs '0'; the output ends of the two input OR gates of the last stage are connected with the TDC circuit.
Further, the SPAD detection unit comprises an SPAD device, a quenching circuit and a shaping circuit, voltage pulses are output to the outside under the action of the quenching circuit and the shaping circuit after the SPAD device responds, the voltage pulses carry time information and are reversely transmitted to the 2 TDC circuits in the 2 delay chains to trigger the TDC circuits to generate the time information.
Further, the time when the photon reaches the ith SPAD detection unit is taken as T ti The time delay chain which is transmitted upwards is transmitted to an upper TDC circuit for detectionThe arrival time is T 1 ＝T ti + i tau, passing through a delay chain passing down to the lower TDC circuit, at a time T 2 ＝T ti + (N-i +1) τ, calculating the position of the responding SPAD detecting unit as
While obtaining a photon arrival time of
Furthermore, the readout circuit is composed of 2D flip-flops, 1 AND gate AND 1 FIFO circuit, pulse signals generated by the SPAD detection unit are reversely transferred along 2 delay chains transferred upwards AND downwards, reach the corresponding 2 TDC circuits to trigger TDC timing, AND simultaneously, the two paths of signals respectively trigger the 2D flip-flops to generate high level to mark that one trigger is generated in the pixel cluster at the moment; and then the FIFO circuit reads the data in the 2 TDC circuits under the drive of the system clock, and the 2D flip-flop circuits are Reset by a Reset signal after the data reading is finished, so that the next data detection is realized.
Furthermore, the N SPAD detection units are arranged in a row or a line in the one-dimensional direction to form a single-row or single-line linear array SPAD detection array, and 2 delay chains, 2 TDC circuits and a readout circuit are configured to form a linear array SPAD detector; the 2 delay chains are formed by arranging 2N basic delay units on one side of the linear array SPAD detection array in two columns or two rows, and the 2 TDC circuits are respectively arranged on the upper side and the lower side of an area formed by the linear array SPAD detection array and the 2 delay chains; the output of each SPAD detection unit is simultaneously accessed into the basic delay units at the corresponding positions of the 2 delay chains, and the time information recorded by the 2 TDC circuits reversely deduces the one-dimensional address information and the time information of the responding SPAD detection unit.
Furthermore, M linear array SPAD detection arrays are closely arranged in a two-dimensional direction to form an N multiplied by M area array, and each linear array SPAD detection array is provided with 2 delay chains, 2 TDC circuits and a reading circuit to form an area array SPAD detector with M columns working in parallel; each line array can work independently to generate one-dimensional address information, and the two-dimensional address information can be obtained by combining the address information of the line where the line array is located.
Furthermore, the N SPAD detection units are sequentially arranged in a snake-shaped or Hilbert curve mode to form a two-dimensional area array with a single-chain structure to form an area array SPAD detection array, and 2 delay chains, 2 TDC circuits and a reading circuit are configured to form an area array SPAD detector; the 2 delay chains are formed by closely arranging 2N basic delay units in the same form in the area array SPAD detection array, and the 2 TDC circuits are respectively arranged on the upper side and the lower side of an area formed by the area array SPAD detection array and the 2 delay chains; the output of each SPAD detection unit is simultaneously accessed into the basic delay unit at the corresponding position of 2 delay chains, the time information recorded by 2 TDC circuits reversely deduces the one-dimensional address information and the time information of the responding SPAD detection unit, and then the two-dimensional address information of the responding SPAD detection unit is obtained by reversely deducing according to the known arrangement information.
According to the invention, an SPAD device is used as a photoelectric detection device, an optical signal is accurately detected by utilizing the easy excitation characteristic of the SPAD device, a pulse voltage signal is generated, the generated pulse voltage signal is used as an input signal of a delay chain, and the position information of the SPAD device which responds is calculated by reading time information recorded by TDC circuits at the tail ends of the two delay chains, so that the address coding effect is achieved. The invention adopts a digital circuit mode to read the pixel address information, does not need a special decoding circuit to extract address data, and can directly obtain the pixel address information through calculation, so the circuit is easy to standardize and move, and has strong anti-interference capability. Meanwhile, the time information of the original photoelectric response signal can be output in the address coding process, the signal can be processed in the subsequent processing, and the method is suitable for SPAD arrays which need the time information and the address coding information, such as a time of flight (ToF) array.
Compared with the prior area array reading technology, the invention uses the address coding technology, has short whole frame reading time and is beneficial to high frame frequency reading; meanwhile, the digital circuit has a relatively simple structure, and is favorable for on-chip integration and fidelity. In addition, the technology of the invention can also be used for designing a position sensor, and compared with the prior position sensor technology, the SPAD device is used as a detection unit, so that the sensitivity is higher, and the detection unit is easier to be triggered by photons.
Drawings
FIG. 1 is a schematic diagram of a pixel address coding circuit with time information suitable for SPAD array according to the present invention.
Fig. 2 is a schematic diagram of the working principle of the pixel address coding circuit with time information suitable for the SPAD array according to the present invention.
Fig. 3 is a schematic structural diagram of an SPAD detection unit in the pixel address encoding circuit according to the present invention.
Fig. 4 is a schematic structural diagram of a readout circuit in the pixel address coding circuit according to the present invention.
Fig. 5 is a schematic diagram of a linear array SPAD detector formed by arranging pixel address coding circuits in a linear array form.
FIG. 6 is a schematic diagram of an area array SPAD detector formed by arranging pixel address coding circuits in an area array form.
Fig. 7 shows an area array formed by (a) a serpentine arrangement and (b) a hubert curve arrangement, taking 16 SPAD detection units as an example, according to the present invention.
Fig. 8 is a schematic diagram of a two-dimensional array sensor formed by a plurality of linear array SPAD detectors according to the present invention.
Detailed Description
The technical solutions of the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments, which are only illustrative and not intended to limit the present invention.
FIG. 1 is a schematic diagram of a pixel address coding circuit with time information suitable for SPAD array according to the present invention. The circuit comprises an SPAD detection array consisting of N SPAD detection units, 2 delay chains, 2 TDC circuits and a readout circuit. The SPAD detection unit comprises an SPAD device, a quenching circuit and a shaping circuit, and voltage pulses are output at an output end after photons are detected. The delay chain adopts two input OR gates as a basic delay unit, the first input ends of the two input OR gates are connected to the output end of the SPAD detection unit, the second input ends of the two input OR gates are connected with the output end of the two input OR gates at the first stage, the output ends of the two input OR gates are connected with the second input end of the two input OR gates at the next stage, and the two input OR gates in a row are connected in the mode to form a delay chain. The second input end of the first-stage two-input OR gate of the delay chain is grounded and always inputs '0'; the output ends of the two input OR gates of the last stage are connected with the TDC circuit. The voltage pulse output by the SPAD detection unit is simultaneously connected to 2 delay chains which are transmitted upwards and downwards to perform reverse transmission; the two pulses transmitted in reverse direction respectively reach 2 corresponding TDC circuits through 2 delay chains to trigger TDC timing; the readout circuit reads data of 2 TDC circuits, and pixel address information and pulse time information are obtained through calculation.
Fig. 2 is a schematic diagram of the working principle of the pixel address coding circuit with time information suitable for the SPAD array according to the present invention. The pixel address coding circuit consists of 2 delay chains and 2 TDC circuits, and each delay chain circuit consists of N identical OR gates and a power ground. Each OR gate acts as a basic delay element with a delay time τ. One end of the two input OR gates of each delay chain is connected to the pulse output end of the SPAD, and the other end of the two input OR gates of each delay chain is connected to the output end of the last-stage OR gate. The output time of the SPAD detection units at different positions after response through the delay chain is different, and the time when the photon reaches the ith SPAD detection unit is taken as T ti The time is transmitted to an upper TDC circuit through an upward-transmitted delay chain, and the detected time is T 1 ＝T ti + i tau, passing through a delay chain passing down to the lower TDC circuit, at a time T 2 ＝T ti + (N-i +1) τ, calculating the position of the responding SPAD detecting unit as
While obtaining a photon arrival time of
Fig. 3 is a schematic structural diagram of an SPAD detection unit in the pixel address encoding circuit according to the present invention. The SPAD detection unit comprises a SPAD device, a quenching circuit and a shaping circuit. The SPAD device is a single photon avalanche diode, which operates in the geiger mode. After the single photon avalanche diode generates avalanche, the single photon avalanche diode is quenched by a quenching circuit and shaped by a shaping circuit to generate a pulse voltage signal, and the pulse voltage signal is connected to one input end of the OR gate. When photons reach the SPAD device and respond, the SPAD device can generate avalanche breakdown and output continuous large current. The quenching circuit comprises active quenching and passive quenching, the simplest passive quenching resistance quenching is taken as an example in the figure, when the SPAD device generates avalanche breakdown, the current is subjected to resistance voltage division, the voltage of two ends of the SPAD device is reduced to be near or below the breakdown point, so that quenching is generated, and the SPAD device is gradually restored to a waiting mode. The shaping circuit is used for converting the voltage output in the whole process of SPAD avalanche breakdown and quenching recovery into a pulse voltage signal. The shaping circuit outputs a voltage signal "1" when the SPAD responds, and outputs a voltage signal "0" when there is no response.
Fig. 4 is a schematic structural diagram of a readout circuit in the pixel address coding circuit according to the present invention. The reading circuit consists of 2D triggers, 1 AND gate AND 1 FIFO circuit. Pulse signals generated by the SPAD detection unit are reversely transmitted along 2 time delay chains transmitted upwards and downwards, reach 2 corresponding TDC circuits to trigger TDC timing, and simultaneously two paths of signals respectively trigger two D triggers to generate high level to mark that one time of triggering is generated in a pixel cluster at the moment. And then the FIFO circuit reads the data in the 2 TDC circuits under the drive of the system clock, and the 2 trigger circuits are Reset by the Reset signal after the data reading is finished, so that the next data detection is realized.
Fig. 5 is a schematic diagram of a linear array SPAD detector formed by arranging pixel address coding circuits in a linear array form. The N SPAD detection units are arranged in a row or a column in the one-dimensional direction to form a single-row or single-column linear array SPAD detection array, and 2 delay chains, 2 TDC circuits and a readout circuit are configured to form the linear array SPAD detector. The 2 delay chains are formed by arranging 2N basic delay units on one side of the linear array SPAD detection array in two columns or two rows, and the 2 TDC circuits are respectively arranged on the upper side and the lower side of an area formed by the linear array SPAD detection array and the 2 delay chains; the output of each SPAD detection unit is simultaneously accessed into the basic delay units at the corresponding positions of the 2 delay chains, and the time information recorded by the 2 TDC circuits reversely deduces the one-dimensional address information and the time information of the responding SPAD detection unit.
FIG. 6 is a schematic diagram of an area array SPAD detector formed by arranging pixel address coding circuits in an area array form. The N SPAD detection units are sequentially arranged into a two-dimensional area array with a single-chain structure in a snake-shaped or Hilbert curve mode and the like to form an area array SPAD detection array, and 2 delay chains, 2 TDC circuits and a reading circuit are configured to form the area array SPAD detector. The 2 delay chains are formed by closely arranging 2N basic delay units in the same form in the area array SPAD detection array, and the 2 TDC circuits are respectively arranged on the upper side and the lower side of an area formed by the area array SPAD detection array and the 2 delay chains. The output of each SPAD detection unit is simultaneously accessed into the basic delay unit at the corresponding position of 2 delay chains, the time information recorded by 2 TDC circuits reversely deduces the one-dimensional address information and the time information of the responding SPAD detection unit, and then the two-dimensional address information of the responding SPAD detection unit is obtained by reversely deducing according to the known specific arrangement information.
Fig. 7 shows an area array formed by (a) a serpentine arrangement and (b) a hubert curve arrangement, taking 16 SPAD detection units as an example, according to the present invention. The two planar array structures are sequentially arranged in a certain sequence and can be converted into a one-dimensional single-chain structure essentially. The time information recorded by the 2 TDC circuits can be deduced to obtain the one-dimensional address information of the responding SPAD detection unit, and the two-dimensional address information can be deduced by combining the known specific arrangement information. For example: in the serpentine structure in fig. (a), if the obtained device position i is 6, the two-dimensional coordinate thereof is (3, 2), and the third row and the second column are indicated; in the hilbert curve structure shown in fig. (b), when the obtained device position i is 6, the corresponding two-dimensional coordinates are (4, 1), and the fourth row and the first column are shown.
Fig. 8 is a schematic diagram of a two-dimensional array sensor formed by a plurality of linear array SPAD detectors according to the present invention. The M linear array SPAD detection arrays are densely arranged in the two-dimensional direction to form an N multiplied by M area array, and each linear array SPAD detection array is provided with 2 delay chains, 2 TDC circuits and a read-out circuit to form an area array SPAD detector with M columns working in parallel. Each column of linear arrays can work independently to generate one-dimensional address information, and the two-dimensional address information can be obtained by combining the address information of the column where the linear arrays are located, for example, if the second SPAD detection unit in the third column responds, the row coordinate is 2 by the TDC data, and the column coordinate is 3 by the TDC circuit position of the generated data, so that the two-dimensional coordinate (2, 3) is obtained, which represents the second row and the third column. The nxm array may operate simultaneously in multiple columns to generate multiple address encoding information for simultaneously detecting multiple location information.
Claims (8)
1. A pixel address coding circuit with time information suitable for an SPAD array is characterized by comprising an SPAD detection array consisting of N SPAD detection units, 2 delay chains, 2 TDC circuits and a readout circuit, wherein the SPAD detection units are used for detecting photons and outputting voltage pulses; the 2 delay chains transmit delay in opposite directions, each delay chain comprises N basic delay units with delay time of tau, each SPAD detection unit is simultaneously connected with the corresponding basic delay unit in the 2 delay chains, and voltage pulses output by the SPAD detection units are simultaneously transmitted in opposite directions in the 2 delay chains; the tail ends of the 2 delay chains are respectively connected with 1 TDC circuit; the reading circuit reads data of 2 TDC circuits, and pixel address information and pulse time information are obtained through calculation.
2. The pixel address coding circuit with time information suitable for SPAD array according to claim 1, wherein each delay chain uses two-input OR gates as basic delay unit, the first input end of the two-input OR gates is connected to the output end of SPAD detection unit, the second input end of the two-input OR gates is connected to the output end of the two-input OR gate of the previous stage, the output ends of the two-input OR gates are connected to the second input end of the two-input OR gate of the next stage, and a row of two-input OR gates are connected in the above way to form a delay chain; the second input end of the two-input OR gate of the first stage of the delay chain is grounded, and 0 is always input; the output ends of the two input OR gates of the last stage are connected with the TDC circuit.
3. The pixel address coding circuit with time information suitable for the SPAD array according to claim 1, wherein the SPAD detection unit comprises a SPAD device, a quenching circuit and a shaping circuit, after the SPAD device responds, under the action of the quenching circuit and the shaping circuit, voltage pulses are output externally, the voltage pulses carry time information and are reversely transmitted to 2 TDC circuits in 2 delay chains to trigger the TDC circuits to generate the time information.
4. The pixel address coding circuit with time information suitable for SPAD array as claimed in claim 1, wherein the time when photon reaches the ith SPAD detection unit is T ti The time is transmitted to an upper TDC circuit through an upward-transmitted delay chain, and the detected time is T 1 ＝T ti + i tau, passing through a delay chain passing down to the lower TDC circuit, at a time T 2 ＝T ti + (N-i +1) τ, calculating the position of the responding SPAD detection unit as
While obtaining a photon arrival time of
5. The pixel address coding circuit with time information suitable for the SPAD array according to claim 1, wherein the readout circuit is composed of 2D triggers, 1 AND gate AND 1 FIFO circuit, pulse signals generated by the SPAD detection unit are reversely transmitted along 2 delay chains transmitted upwards AND downwards, the pulse signals reach the corresponding 2 TDC circuits to trigger TDC timing, AND meanwhile, the two paths of signals respectively trigger the 2D triggers to generate high level, so that one trigger is generated in a pixel cluster at the moment; and then the FIFO circuit reads the data in the 2 TDC circuits under the drive of the system clock, and the 2D flip-flop circuits are Reset by a Reset signal after the data reading is finished, so that the next data detection is realized.
6. The pixel address coding circuit with time information suitable for SPAD array according to one of claims 1 to 5, wherein N SPAD detection units are arranged in one row or one column in one dimension direction to form a single row or one column of linear array SPAD detection array, and 2 delay chains, 2 TDC circuits and readout circuits are configured to form a linear array SPAD detector; the 2 delay chains are formed by arranging 2N basic delay units on one side of the linear array SPAD detection array in a two-column or two-row mode, and the 2 TDC circuits are respectively arranged on the upper side and the lower side of an area formed by the linear array SPAD detection array and the 2 delay chains; the output of each SPAD detection unit is simultaneously accessed into the basic delay units at the corresponding positions of the 2 delay chains, and the time information recorded by the 2 TDC circuits reversely deduces the one-dimensional address information and the time information of the responding SPAD detection unit.
7. The pixel address coding circuit with time information suitable for the SPAD array according to claim 6, wherein M linear array SPAD detection arrays are densely arranged in two-dimensional direction to form an N x M area array, each linear array SPAD detection array is provided with 2 delay chains, 2 TDC circuits and a readout circuit to form an M-array area array SPAD detector working in parallel; each line array can work independently to generate one-dimensional address information, and the two-dimensional address information can be obtained by combining the address information of the line where the line array is located.
8. The pixel address coding circuit with time information suitable for the SPAD array according to one of claims 1 to 5, wherein N SPAD detection units are sequentially arranged in a snake-shaped or Hilbert curve manner to form a two-dimensional area array with a single-chain structure to form an area array SPAD detection array, and 2 delay chains, 2 TDC circuits and a readout circuit are configured to form an area array SPAD detector; the 2 delay chains are formed by closely arranging 2N basic delay units in the same form in the area array SPAD detection array, and the 2 TDC circuits are respectively arranged on the upper side and the lower side of an area formed by the area array SPAD detection array and the 2 delay chains; the output of each SPAD detection unit is simultaneously accessed into the basic delay unit at the corresponding position of 2 delay chains, the time information recorded by 2 TDC circuits reversely deduces the one-dimensional address information and the time information of the responding SPAD detection unit, and then the two-dimensional address information of the responding SPAD detection unit is obtained by reversely deducing according to the known arrangement information.
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