CN115334263B - Silicon pixel detector reading system and method - Google Patents
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Abstract
The invention relates to a silicon pixel detector reading system and a method, which are characterized by comprising a pixel array formed by a plurality of pixel units of M rows and N columns; every two columns of pixel units in the pixel array form corresponding double-column pixel modules, n adjacent double-column pixel modules form corresponding super-column pixel modules, and a plurality of super-column pixel modules form column block pixel modules; a plurality of pixel units in the pixel array form a pixel set module, wherein N is less than or equal to N; an analog signal processing circuit is arranged in each pixel unit; each pixel set module is provided with a time-digital conversion circuit; each super column pixel module is provided with a super column controller; each row block pixel module is provided with a row block controller; the read-out controller is used for reading out the data stored in each column of block controller, and the invention can be widely applied to the technical field of semiconductor detectors.
Description
Technical Field
The invention relates to the technical field of semiconductor detectors, in particular to a silicon pixel detector reading system and a silicon pixel detector reading method.
Background
One of the biggest challenges in constructing a pixel detector is designing a suitable pixel chip with thousands of electronic channels. The pixel chips comprise pixel array units which are arranged regularly, and circuits on the pixel chips are transmitted to the bottom of each pixel chip through hit information and then transmitted to the outside of the chip. Each pixel circuit must provide low noise amplification of the sensor charge, hit recognition and suitable readout methods, must ensure a well-defined threshold for analog and digital and sufficient speed. Thus, the digital readout method must handle higher data volumes and must transfer the data out faster.
However, prior art silicon pixel detector readout systems, methods can only read both the hit pixel address and time information, or can only read energy information, even energy analog signals, and cannot handle higher data volumes.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a silicon pixel detector readout system and method that can quickly read out the silicon pixel detector energy, time and position information.
In order to achieve the above purpose, the present invention adopts the following technical scheme: in one aspect, a readout system for a silicon pixel detector is provided, including a pixel array composed of a plurality of pixel units of M rows and N columns;
every two columns of pixel units in the pixel array form corresponding double-column pixel modules, n adjacent double-column pixel modules form corresponding super-column pixel modules, and a plurality of super-column pixel modules form corresponding column block pixel modules; a plurality of pixel units in the pixel array form a corresponding pixel set module, wherein N is less than or equal to N;
each pixel unit is internally provided with an analog signal processing circuit which is used for acquiring an electric signal generated by incident particles when the pixel unit is hit by the particles and generating a corresponding hit zone bit signal;
each pixel set module is provided with a time-to-digital conversion circuit which is used for measuring the hit time information corresponding to the pixel set module and generating a pixel set hit zone bit signal according to all hit zone bit signals corresponding to the pixel set module;
each super column pixel module is provided with a super column controller, and is used for generating a read out hit zone bit signal according to the hit zone bit signals of all pixel sets in the corresponding super column pixel module; generating an energy signal according to all the electric signals in the corresponding super column pixel module; storing data of the pixel set modules corresponding to all effective pixel set hit zone bit signals corresponding to all effective read hit zone bit signals;
each column block pixel module is provided with a column block controller and is used for reading out and storing data stored in each super column controller;
and the readout controller is used for reading out the data stored in each column block controller.
Further, each pixel set module comprises s×s pixel units, and s is less than or equal to n.
Further, each of the analog signal processing circuits includes:
the CMOS pixel sensor is used for acquiring an electric signal generated by incident particles when the pixel unit is hit by the particles;
the amplifying circuit is used for amplifying the electric signals acquired by the CMOS pixel sensor;
the comparator is used for carrying out threshold discrimination on the amplified electric signal, and when the electric signal is greater than the threshold value of the comparator, a hit zone bit signal is generated;
the energy output circuit is used for outputting the amplified electric signals to the corresponding super column controller and outputting the generated hit zone bit signals to the corresponding time-digital conversion circuit;
and the digital signal processing and storage is used for storing the position information of the hit pixel unit and the electric signals output by the corresponding energy output circuit.
Further, the time-to-digital conversion circuit performs an OR operation on the hit flag bit signals corresponding to all the pixel units in the pixel set module, so as to generate a pixel set hit flag bit signal.
Further, each super column controller includes:
the super column reader is used for carrying out OR operation on all pixel set hit zone bit signals generated in the corresponding super column pixel module to generate read hit zone bit signals;
the super column reader is further used for scanning whether the hit zone bit signal of each pixel set is valid or not in sequence when the hit zone bit signal is valid, and outputting an amplified electric signal of each pixel unit in the pixel set module when the hit zone bit signal of each pixel set is valid;
the area analog-to-digital converter is used for generating digital energy signals according to the amplified electric signals of each pixel unit corresponding to the mark bit signals in the effective pixel set based on the control of the super column reader;
and the first-in first-out memory is used for storing the address of the first pixel unit in the pixel set module corresponding to the corresponding all effective pixel set hit bit signal, the time information of the pixel set module and the digital energy signals of all the pixel units in the pixel set module when the read hit signal is effective.
Further, each of the column block controllers includes:
the token ring readout control module is used for reading out the data stored in all the super column controllers in the column block pixel module by adopting a token ring readout mode;
and the second first-in first-out memory is used for storing the data read by the token ring read control module.
Further, the read-out controller reads out the data stored in each column block controller in a token ring read mode.
In another aspect, a method for reading out a silicon pixel detector is provided, including:
setting the readout system of the silicon pixel detector;
when a certain pixel unit is hit by particles, an analog signal processing circuit in the pixel unit acquires an electric signal generated by incident particles and generates a hit zone bit signal;
in the pixel set module corresponding to the pixel unit, the time-to-digital conversion circuit generates a pixel set hit zone bit signal according to all hit zone bit signals in the corresponding pixel set module;
in the super column pixel module corresponding to the pixel set module, the super column controller generates an effective reading hit bit signal according to all pixel set hit bit signals generated in the corresponding super column pixel module;
when the signal of the hit bit is effective, in the super column pixel module corresponding to the pixel set module, the super column controller generates an energy signal according to the electric signals measured by all pixel units in the corresponding super column pixel module, and stores the data of the pixel set module corresponding to the signal of the hit bit of all effective pixel sets;
in a column block pixel module corresponding to the pixel set module, the column block controller reads out and stores data stored in each super column controller;
the read-out controller reads out the data stored in all the column block controllers and transmits the data to the outside.
Further, when a certain pixel unit is hit by a particle, the analog signal processing circuit in the pixel unit acquires an electrical signal generated by the incident particle and generates a hit bit signal, including:
when a certain pixel unit is hit by particles, a CMOS pixel sensor of the analog signal processing circuit in the pixel unit acquires electric signals generated by incident particles;
the amplifying circuit amplifies the electric signals acquired by the CMOS pixel sensor;
the comparator carries out threshold discrimination on the amplified electric signal, and when the electric signal is greater than the threshold value of the comparator, a hit marker bit signal is generated;
the energy output circuit outputs the amplified electric signal to the corresponding super column controller, and outputs the generated hit bit signal to the time-digital conversion circuit;
the digital signal processing and memory stores the position information of the hit pixel unit and the electric signals output by the corresponding energy output circuit, and the stored information is judged and selected by the reading frame and transmitted to the outside of the chip.
Further, when the signal of the hit flag bit is read out effectively, in the super column pixel module corresponding to the pixel set module, the super column controller generates an energy signal according to the electric signals measured by all the pixel units in the corresponding super column pixel module, and stores the data of the pixel set module corresponding to the signal of the hit flag bit in all the effective pixel sets, including:
when the shot bit signal is effective, in the super column pixel module corresponding to the pixel set module, the super column controller scans whether the shot bit signal of each corresponding pixel set is effective or not in sequence, if the shot bit signal of each pixel set is effective, the amplified electric signal of each pixel unit in the pixel set module is output to the area analog-to-digital converter, and the area analog-to-digital converter is controlled to start sampling;
the regional analog-to-digital converter generates digital energy signals according to the amplified electric signals of each pixel unit corresponding to the signal of the hit zone bit of the effective pixel set based on the control of the super column reader;
when the read hit signal is valid, the first-in first-out memory stores the address of the first pixel unit in the pixel set module corresponding to the hit flag bit signal of all the corresponding valid pixel sets, the time information of the pixel set module and the digital energy signals of all the pixel units in the pixel set module.
Due to the adoption of the technical scheme, the invention has the following advantages:
1. according to the invention, as the time-digital conversion circuit and the super column controller are arranged, the pixel set hit zone bit signal is generated through the time-digital conversion circuit, the super column controller generates the read hit signal according to the pixel set hit zone bit signal, and the generated read hit signal is used for controlling whether scanning is performed or not, and whether the area analog-digital converter is started or not, the power consumption brought by the area analog-digital converter can be effectively reduced, and the time measurement precision is improved.
2. Because the bus signals occupy less area in a unit pixel cell, the pixel cells in the pixel array of the present invention are advantageously grouped by columns.
3. According to the invention, when the effective reading hit zone bit signals are generated, the hit zone bit signals of the pixel set are checked one by one through the super column reader, so that the number of reading pixels can be effectively reduced.
4. The column block controller and the readout controller in the invention both adopt a token ring readout mode to read out data, so that the readout speed can be improved.
5. According to the invention, the pixel array is partitioned by the pixel set module, the super column pixel module and the column block pixel module, so that effective information can be detected and screened step by step, and the transmission of effective data quantity is improved.
6. The super column controller is arranged in the invention, so that the area analog-to-digital converter can be started when the signal of the hit zone bit is read out effectively, the power consumption brought by the area analog-to-digital converter is effectively reduced, the effective hit pixel set can be screened, and the position, time and energy signals of the effective hit can be read out clearly.
7. The invention can read out the digital information of the energy, time and position (pixel address) of the silicon pixel detector at the same time.
In summary, the invention can be widely applied to the technical field of semiconductor detectors.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Like parts are designated with like reference numerals throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a read-out system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a signal processing procedure of an analog signal processing circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a readout implementation process according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a chip-scale readout scheme according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.
Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.
For ease of description, spatially relative terms, such as "inner," "outer," "lower," "upper," and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
Due to the experimental requirements of particle physics experiments, the front-end circuit and the detector signal processing circuit are always closely related to the control readout logic. Hit information from the front-end circuitry must be further transferred by the control circuitry and read-out circuitry at the periphery of the chip. The method of readout depends to a large extent on the target application. In particle physics applications more detailed information is required, where all hits must be provided, usually with time and corresponding pulse amplitude. The choice of a suitable readout method depends mainly on the available chips and acceptable hit losses. The system and the method for reading the silicon pixel detector provided by the embodiment of the invention can be used for rapidly reading the effective information of the hit signal, including the energy, time and position information, and correspondingly considering the low power consumption performance of other modules of the circuit. Although existing pixel chips use different geometries, readout principles, and analog circuits, the construction and characteristics of several modules are similar in the main part of the design. Each pixel cell includes one analog signal processing circuit and, in most cases, digital logic for measuring and reading measurement data.
Example 1
As shown in fig. 1, the present embodiment provides a readout system of a silicon pixel detector, which includes a pixel array 1, wherein the pixel array 1 is composed of a plurality of pixel units 11 of M rows and N columns.
Every two Columns of pixel cells 11 in the pixel array 1 constitute corresponding Double Columns (DCol) pixel modules 2 in order to share circuits between the pixel cells 11 and reduce crosstalk between the digital and analog parts. Adjacent N (N is less than or equal to N) double-row pixel modules 2 form corresponding Super row (Super Column) pixel modules 3, and a plurality of Super row pixel modules 3 form corresponding row Block pixel modules 4 (Column Block). Every s×s (s.ltoreq.n) pixel units 11 constitute a corresponding pixel set module 5 (Cluster).
As shown in fig. 1 and 3, the silicon pixel detector readout system further includes an analog signal processing circuit, a time-to-digital conversion circuit 6 (Time to Digital Converter, TDC), a super column controller 7 (Super Column Controller, SCC), a column block controller 8 (Column Block Controller, CBC), and a readout controller 9 (Readout Controller).
An analog signal processing circuit is disposed in each pixel unit 11, and the analog signal processing circuit is configured to obtain an electrical signal generated by an incident particle when the pixel unit 11 is hit by the particle, and generate a hit flag signal (hit flag).
Each pixel set module 5 is provided with a time-to-digital conversion circuit 6, the time-to-digital conversion circuit 6 is used for measuring the Hit time information of the corresponding pixel set module 5, performing an OR operation on the Hit flag bit signals of all the pixel units 11 in the corresponding pixel set module 5, generating a pixel set Hit flag bit signal (Cluster Hit), and taking the pixel set Hit flag bit signal as a start signal of the time-to-digital conversion circuit 6.
Each super column pixel module 3 is provided with a super column controller 7 (SCC), and each super column controller 7 is respectively connected with a time-to-digital conversion circuit 6 of each pixel set module 5 in the corresponding super column pixel module 3, and is used for performing an OR operation on all pixel set hit bit signals generated in the corresponding super column pixel module 3 to generate a read hit bit signal (readout hit); generating an energy signal according to the electrical signals measured by all the pixel units 11 in the corresponding super column pixel module 3; and storing the address of the first pixel unit 11 in the pixel set module 5 corresponding to all valid pixel set hit flag bit signals corresponding to all valid read hit flag bit signals, the time information of the pixel set module 5, and the energy signals of all pixel units 11 in the pixel set module 5.
Each column of block pixel modules 4 is provided with a column block controller 8 (CBC), each column block controller 8 is respectively connected with the super column controller 7 of each super column pixel module 3 in the corresponding column of block pixel module 4, and the column block controller 8 is used for reading and storing the data stored in each super column controller 7 in a token ring reading mode.
The read-out controller 9 is respectively connected to each column of block controllers 8, and the read-out controller 9 is used for reading out the data stored in each column of block controllers 8 by adopting a token ring read-out mode and transmitting the data to the outside.
In a preferred embodiment, the pixel cells 11 in the pixel array 1 are grouped in columns, i.e. the control signals and the output data streams are routed vertically. The column-based formula of the present embodiment is more advantageous because of the principle that bus signals occupy less area in the pixel cell 11.
In a preferred embodiment, as shown in fig. 2, each analog signal processing circuit includes a CMOS pixel sensor 12, an amplifying circuit 13, a comparator 14, an energy output circuit 15, and a digital signal processing and memory 16.
The CMOS pixel sensor 12 is used to acquire an electrical signal generated by incident particles when the pixel unit 11 is hit by the particles.
The amplifying circuit 13 is for amplifying the electric signal acquired by the CMOS pixel sensor 12.
The comparator 14 is configured to perform threshold discrimination on the amplified electric signal, and generate a hit flag signal when the electric signal is greater than the threshold of the comparator 14, and is valid when the hit flag signal is 1, and is invalid when the hit flag signal is 0.
The energy output circuit 15 is configured to output the amplified electric signal to the corresponding supercolumn controller 7, and output the generated hit flag signal to the corresponding time-to-digital conversion circuit 6.
The digital signal processing and memory 16 is used for storing the position information of the hit pixel unit 11 and the electric signal output by the corresponding energy output circuit 15, and transmitting the stored information to the outside of the chip through the readout architecture judgment.
In a preferred embodiment, as shown in FIG. 3, each supercolumn controller 7 includes a supercolumn reader 71 (Super Column Reader, SCR), a Regional analog-to-digital converter 72 (Regional ADC), and a first-in-first-out memory 73.
The supercolumn reader 71 is configured to perform an OR operation on all pixel set hit flag signals generated by the time-to-digital conversion circuit 6 in the corresponding supercolumn pixel module 3, and generate a read hit flag signal.
The super column reader 71 is further configured to sequentially scan, from top to bottom, whether the corresponding hit bit signal of each pixel set is valid (valid when 1 is valid and invalid when 0 is valid) when the hit bit signal is valid, and skip the pixel set module 5 to the next pixel set module 5 if the hit bit signal of each pixel set is invalid; if the sign bit signal of the pixel set hit is valid, the amplified electrical signal of each pixel unit 11 in the pixel set module 5 is output to the area analog-to-digital converter 72, and the area analog-to-digital converter 72 is controlled to start sampling, so as to effectively reduce the power consumption caused by the area analog-to-digital converter 72.
The area analog-to-digital converter 72 is configured to generate an amplitude signal representing energy, i.e., a digital energy signal, from the amplified electrical signal of each pixel cell 11 corresponding to the sign bit signal in the active pixel set based on the control of the super column reader 71.
The first fifo 73 is used for storing the address of the first pixel unit 11 (i.e., the upper left pixel unit 11 in fig. 3) in the pixel set module 5 corresponding to the sign bit signal of all the corresponding valid pixel sets, the time information of the pixel set module 5, and the digital energy signal of all the pixel units 11 in the pixel set module 5 when the read hit signal is valid.
In a preferred embodiment, as shown in FIG. 4, each column of block controllers 8 includes a token ring read control module 81 and a second first-in-first-out memory 82.
The token ring readout control module 81 is configured to read out the data stored in the first fifo 73 in all the super column controllers 7 in the column block pixel module 4 in a token ring readout manner.
The second fifo 82 is used to store the data read by the token ring readout control module 81 to increase the readout speed of each column of the tile pixel modules 4.
Specifically, the generation process of the read hit flag signal is:
as shown in fig. 2, the comparator 14 of the analog signal processing circuit generates a hit flag signal, and the hit flag signal is valid when it is 1, and is invalid when it is 0, and all the pixel units 11 in the pixel set module 5 output respective corresponding hit flag signals, and the hit flag signals are input to the corresponding time-to-digital conversion circuit 6 for performing OR operation to generate a pixel set hit flag signal, and similarly, the hit flag signal is valid when the hit flag signal of the pixel set is 1, and is invalid when it is 0. As shown in fig. 3, each pixel set module 5 outputs a corresponding pixel set hit flag signal, and the pixel set hit flag signals, whether 0 OR 1, are input to the corresponding super column controller 7 for performing an OR operation to generate a read hit flag signal, and the read hit flag signal is valid when 1 and invalid when 0.
Example 2
The embodiment provides a readout method of a silicon pixel detector, which comprises the following steps:
1) The silicon pixel detector readout system of example 1 was set up.
2) When a certain pixel unit 11 is hit by a particle, an analog signal processing circuit in the pixel unit 11 acquires an electrical signal generated by the incident particle and generates a hit flag signal, specifically:
2.1 When a certain pixel cell 11 is hit by a particle, the CMOS pixel sensor 12 of the analog signal processing circuit in the pixel cell 11 acquires an electric signal generated by the incident particle.
2.2 An amplification circuit 13 of the analog signal processing circuit in the pixel unit 11 amplifies the electric signal acquired by the CMOS pixel sensor 12.
2.3 The comparator 14 of the analog signal processing circuit in the pixel unit 11 performs threshold discrimination on the amplified electric signal, generates a hit flag bit signal when the electric signal is greater than the threshold of the comparator 14, and is effective when the hit flag bit signal is 1 and is ineffective when the hit flag bit signal is 0.
2.4 The energy output circuit 15 of the analog signal processing circuit in the pixel unit 11 outputs the amplified electric signal to the corresponding super column controller 7, and outputs the generated hit flag signal to the time-to-digital conversion circuit 6.
2.5 The digital signal processing and memory 16 of the analog signal processing circuit in the pixel unit 11 stores the position information of the hit pixel unit 11 and the electric signal output by the corresponding energy output circuit 15, and transmits the stored information to the outside of the chip through the readout architecture judgment.
3) In the pixel set module 5 corresponding to the pixel unit 11, the time-to-digital conversion circuit 6 performs an OR operation on the hit flag bit signals of all the pixel units 11 in the corresponding pixel set module 5 to generate a pixel set hit flag bit signal, and uses the pixel set hit flag bit signal as a start signal of the time-to-digital conversion circuit 6.
4) In the super column pixel module 3 corresponding to the pixel set module 5, the super column controller 7 performs an OR operation on all the pixel set hit flag bit signals generated in the super column pixel module 3, so as to generate an effective read hit flag bit signal.
Specifically, the super column reader 71 in the super column pixel module 3 corresponding to the pixel set module 5 performs an OR operation on all the pixel set hit flag bit signals generated by the time-to-digital conversion circuit 6 in the corresponding super column pixel module 3, so as to generate a read hit flag bit signal, and the read hit flag bit signal is valid when the read hit flag bit signal is 1, and is invalid when the read hit flag bit signal is 0.
5) When the read hit flag signal is valid, in the super column pixel module 3 corresponding to the pixel set module 5, the super column controller 7 generates an energy signal according to the electrical signals measured by all the pixel units 11 in the corresponding super column pixel module 3, and stores the address of the first pixel unit 11 in the pixel set module 5 corresponding to all the valid pixel set hit flag signals corresponding to the valid read hit flag signal, the time information of the pixel set module 5, and the energy signal of all the pixel units 11 in the pixel set module 5, specifically:
5.1 When the hit bit signal is read out, in the super column pixel module 3 corresponding to the pixel set module 5, the super column controller 7 scans whether the hit bit signal of each corresponding pixel set is valid from top to bottom in sequence, and if the hit bit signal of the pixel set is invalid, the pixel set module 5 is skipped to the next pixel set module 5; if the sign bit signal of the pixel set hit is valid, the amplified electrical signal of each pixel unit 11 in the pixel set module 5 is output to the local analog-to-digital converter 72, and the local analog-to-digital converter 72 is controlled to start sampling.
5.2 Based on the control of the supercolumn reader 71), the area analog-to-digital converter 72 generates an amplitude signal representing energy, i.e., a digital energy signal, from the amplified electrical signal of each pixel cell 11 corresponding to the sign bit signal in the active pixel set.
5.3 The first fifo 73 stores the address of the first pixel unit 11 in the pixel set module 5 corresponding to the valid pixel set hit flag signal, the time information of the pixel set module 5, and the digital energy signal of all the pixel units 11 in the pixel set module 5 when the read hit signal is valid.
6) In the column block pixel module 4 corresponding to the pixel set module 5, the column block controller 8 adopts a token ring reading mode to read and store the data stored in each super column controller 7.
7) The read controller 9 reads out the data stored in all column block controllers 8 by using a token ring read method, and transmits the data to the outside.
The foregoing embodiments are only for illustrating the present invention, wherein the structures, connection modes, manufacturing processes, etc. of the components may be changed, and all equivalent changes and modifications performed on the basis of the technical solutions of the present invention should not be excluded from the protection scope of the present invention.
Claims (9)
1. A silicon pixel detector readout system, comprising a pixel array consisting of a plurality of pixel units of M rows and N columns;
every two columns of pixel units in the pixel array form corresponding double-column pixel modules, n adjacent double-column pixel modules form corresponding super-column pixel modules, and a plurality of super-column pixel modules form corresponding column block pixel modules; a plurality of pixel units in the pixel array form a corresponding pixel set module, wherein N is less than or equal to N; each pixel set module comprises s multiplied by s pixel units, and s is less than or equal to n;
each pixel unit is internally provided with an analog signal processing circuit which is used for acquiring an electric signal generated by incident particles when the pixel unit is hit by the particles and generating a corresponding hit zone bit signal;
each pixel set module is provided with a time-to-digital conversion circuit which is used for measuring the hit time information corresponding to the pixel set module and generating a pixel set hit zone bit signal according to all hit zone bit signals corresponding to the pixel set module;
each super column pixel module is provided with a super column controller, and is used for generating a read out hit zone bit signal according to the hit zone bit signals of all pixel sets in the corresponding super column pixel module; generating an energy signal according to all the electric signals in the corresponding super column pixel module; storing data of the pixel set modules corresponding to all effective pixel set hit zone bit signals corresponding to all effective read hit zone bit signals;
each column block pixel module is provided with a column block controller and is used for reading out and storing data stored in each super column controller;
and the readout controller is used for reading out the data stored in each column block controller.
2. A silicon pixel detector readout system according to claim 1, wherein each of said analog signal processing circuits comprises:
the CMOS pixel sensor is used for acquiring an electric signal generated by incident particles when the pixel unit is hit by the particles;
the amplifying circuit is used for amplifying the electric signals acquired by the CMOS pixel sensor;
the comparator is used for carrying out threshold discrimination on the amplified electric signal, and when the electric signal is greater than the threshold value of the comparator, a hit zone bit signal is generated;
the energy output circuit is used for outputting the amplified electric signals to the corresponding super column controller and outputting the generated hit zone bit signals to the corresponding time-digital conversion circuit;
and the digital signal processing and storage is used for storing the position information of the hit pixel unit and the electric signals output by the corresponding energy output circuit.
3. A silicon pixel detector readout system according to claim 1, wherein said time-to-digital conversion circuit performs an OR operation on hit flag signals corresponding to all of said pixel cells in said pixel set module to generate a pixel set hit flag signal.
4. A silicon pixel detector readout system according to claim 1, wherein each of said supercolumn controllers comprises:
the super column reader is used for carrying out OR operation on all pixel set hit zone bit signals generated in the corresponding super column pixel module to generate read hit zone bit signals;
the super column reader is further used for scanning whether the hit zone bit signal of each pixel set is valid or not in sequence when the hit zone bit signal is valid, and outputting an amplified electric signal of each pixel unit in the pixel set module when the hit zone bit signal of each pixel set is valid;
the area analog-to-digital converter is used for generating digital energy signals according to the amplified electric signals of each pixel unit corresponding to the mark bit signals in the effective pixel set based on the control of the super column reader;
and the first-in first-out memory is used for storing the address of the first pixel unit in the pixel set module corresponding to the corresponding all effective pixel set hit bit signal, the time information of the pixel set module and the digital energy signals of all the pixel units in the pixel set module when the read hit signal is effective.
5. A silicon pixel detector readout system according to claim 1, wherein each of said column block controllers comprises:
the token ring readout control module is used for reading out the data stored in all the super column controllers in the column block pixel module by adopting a token ring readout mode;
and the second first-in first-out memory is used for storing the data read by the token ring read control module.
6. A silicon pixel detector readout system according to claim 1, wherein the readout controller reads out data stored in each of the column block controllers in a token ring readout.
7. A method of readout for a silicon pixel detector, comprising:
providing a silicon pixel detector readout system according to any one of claims 1 to 6;
when a certain pixel unit is hit by particles, an analog signal processing circuit in the pixel unit acquires an electric signal generated by incident particles and generates a hit zone bit signal;
in the pixel set module corresponding to the pixel unit, the time-to-digital conversion circuit generates a pixel set hit zone bit signal according to all hit zone bit signals in the corresponding pixel set module;
in the super column pixel module corresponding to the pixel set module, the super column controller generates an effective reading hit bit signal according to all pixel set hit bit signals generated in the corresponding super column pixel module;
when the signal of the hit bit is effective, in the super column pixel module corresponding to the pixel set module, the super column controller generates an energy signal according to the electric signals measured by all pixel units in the corresponding super column pixel module, and stores the data of the pixel set module corresponding to the signal of the hit bit of all effective pixel sets;
in a column block pixel module corresponding to the pixel set module, the column block controller reads out and stores data stored in each super column controller;
the read-out controller reads out the data stored in all the column block controllers and transmits the data to the outside.
8. The method of claim 7, wherein the analog signal processing circuit in a pixel unit acquires an electrical signal generated by an incident particle and generates a hit flag signal when the pixel unit is hit by the particle, comprising:
when a certain pixel unit is hit by particles, a CMOS pixel sensor of the analog signal processing circuit in the pixel unit acquires electric signals generated by incident particles;
the amplifying circuit amplifies the electric signals acquired by the CMOS pixel sensor;
the comparator carries out threshold discrimination on the amplified electric signal, and when the electric signal is greater than the threshold value of the comparator, a hit marker bit signal is generated;
the energy output circuit outputs the amplified electric signal to the corresponding super column controller, and outputs the generated hit bit signal to the time-digital conversion circuit;
the digital signal processing and memory stores the position information of the hit pixel unit and the electric signals output by the corresponding energy output circuit, and the stored information is judged and selected by the reading frame and transmitted to the outside of the chip.
9. The method for reading out a silicon pixel detector according to claim 8, wherein when the signal of the hit bit is valid, the super column controller generates an energy signal according to the electrical signals measured by all the pixel units in the corresponding super column pixel module in the super column pixel module, and stores the data of the pixel set module corresponding to the signal of the hit bit in all the valid pixel sets, comprising:
when the shot bit signal is effective, in the super column pixel module corresponding to the pixel set module, the super column controller scans whether the shot bit signal of each corresponding pixel set is effective or not in sequence, if the shot bit signal of each pixel set is effective, the amplified electric signal of each pixel unit in the pixel set module is output to the area analog-to-digital converter, and the area analog-to-digital converter is controlled to start sampling;
the regional analog-to-digital converter generates digital energy signals according to the amplified electric signals of each pixel unit corresponding to the signal of the hit zone bit of the effective pixel set based on the control of the super column reader;
when the read hit signal is valid, the first-in first-out memory stores the address of the first pixel unit in the pixel set module corresponding to the hit flag bit signal of all the corresponding valid pixel sets, the time information of the pixel set module and the digital energy signals of all the pixel units in the pixel set module.
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