CN115334263B - A silicon pixel detector readout system and method - Google Patents

Abstract

The invention relates to a silicon pixel detector reading system and a method, which are characterized by comprising a pixel array formed by a plurality of pixel units of M rows and N columns; every two columns of pixel units in the pixel array form corresponding double-column pixel modules, n adjacent double-column pixel modules form corresponding super-column pixel modules, and a plurality of super-column pixel modules form column block pixel modules; a plurality of pixel units in the pixel array form a pixel set module, wherein N is less than or equal to N; an analog signal processing circuit is arranged in each pixel unit; each pixel set module is provided with a time-digital conversion circuit; each super column pixel module is provided with a super column controller; each row block pixel module is provided with a row block controller; the read-out controller is used for reading out the data stored in each column of block controller, and the invention can be widely applied to the technical field of semiconductor detectors.

Description

A silicon pixel detector readout system and method

technical field

The invention relates to the technical field of semiconductor detectors, in particular to a silicon pixel detector readout system and method.

Background technique

One of the biggest challenges in building a pixel detector is designing a suitable pixel chip with thousands of electron channels. The pixel chip includes regularly arranged pixel array units, and the circuit on the pixel chip is transmitted to the bottom of each pixel chip by hitting information, and then transmitted to the outside of the chip. Each pixel circuit must provide low-noise amplification of the sensor charge, hit recognition and a suitable readout method. Both analog and digital must have well-defined thresholds and sufficient speed. Therefore, digital readout methods must handle higher data volumes and must transmit data faster.

However, the silicon pixel detector readout system and method in the prior art can only read the address and time information of the hit pixel at the same time, or only read the energy information, or even read the energy analog signal, and cannot handle more high data volume.

Contents of the invention

In view of the above problems, the purpose of the present invention is to provide a silicon pixel detector readout system and method capable of quickly reading out the energy, time and position information of the silicon pixel detector.

In order to achieve the above object, the present invention adopts the following technical solutions: On the one hand, a silicon pixel detector readout system is provided, including a pixel array composed of several pixel units in M rows and N columns;

Every two columns of pixel units in the pixel array form a corresponding dual-column pixel module, adjacent n double-column pixel modules form a corresponding super-column pixel module, and several super-column pixel modules form a corresponding A column block pixel module; several pixel units in the pixel array form a corresponding pixel set module, where n≤N;

Each pixel unit is provided with an analog signal processing circuit, which is used to obtain the electrical signal generated by the incident particle when the pixel unit is hit by the particle, and generate a corresponding hit flag signal;

Each of the pixel set modules is provided with a time-to-digital conversion circuit, which is used to measure the time information corresponding to the hit of the pixel set module, and generate a pixel set according to all hit flag signals in the corresponding pixel set module hit flag signal;

Each of the super column pixel modules is provided with a super column controller, which is used to generate a readout hit flag bit signal according to the hit flag bit signals corresponding to all pixel sets in the super column pixel module; according to the corresponding super column pixel module All electrical signals in the column pixel module generate energy signals; and store all effective pixel sets corresponding to the hit flag signal corresponding to all effective readouts and hit the data of the pixel set module corresponding to the flag signal;

Each of the column block pixel modules is provided with a column block controller for reading and storing the data stored in each of the super column controllers;

The readout controller is used to read out the data stored in each column block controller.

Further, each pixel set module includes s×s pixel units, s≤n.

Further, each of the analog signal processing circuits includes:

A CMOS pixel sensor, used to acquire the electrical signal generated by the incident particle when the pixel unit is hit by the particle;

an amplification circuit, configured to amplify the electrical signal obtained by the CMOS pixel sensor;

A comparator, configured to perform threshold discrimination on the amplified electrical signal, and generate a hit flag signal when the electrical signal is greater than the threshold of the comparator;

The energy output circuit is used to output the amplified electrical signal to the corresponding super-column controller, and output the generated hit flag signal to the corresponding time-to-digital conversion circuit;

The digital signal processing and memory are used to store the position information of hitting the pixel unit and the electrical signal corresponding to the output of the energy output circuit.

Further, the time-to-digital conversion circuit performs an OR operation on the hit flag signals corresponding to all the pixel units in the pixel set module to generate a pixel set hit flag signal.

Further, each super column controller includes:

The super column reader is used to perform an OR operation on all the pixel set hit flag signals corresponding to the super column pixel module to generate a readout hit flag signal;

The super column reader is also used to sequentially scan whether the hit flag signal of each pixel set is valid when the read hit flag signal is valid, and output the said hit flag signal when the pixel set hit flag signal is valid. an amplified electrical signal of each pixel unit in the pixel set module;

The area analog-to-digital converter is used to generate a digital energy signal based on the control of the super column reader, according to the amplified electrical signal of each pixel unit corresponding to the effective pixel set hit flag signal;

The first first-in-first-out memory is used to store the address of the first pixel unit in the pixel set module corresponding to the corresponding all effective pixel set hit flag signals when the read hit signal is valid, the pixel The time information of the set module and the digital energy signals of all the pixel units in the pixel set module.

Further, each column block controller includes:

The token ring readout control module is used to read out the data stored in all the super column controllers in the column block pixel module by means of token ring readout;

The second FIFO memory is used for storing the data read by the token ring read control module.

Further, the readout controller reads out the data stored in each of the column block controllers in a manner of token ring readout.

In another aspect, a silicon pixel detector readout method is provided, comprising:

Setting the above-mentioned silicon pixel detector readout system;

When a certain pixel unit is hit by a particle, the analog signal processing circuit in the pixel unit acquires the electrical signal generated by the incident particle and generates a hit flag signal;

In the pixel set module corresponding to the pixel unit, the time-to-digital conversion circuit generates a pixel set hit flag signal according to all hit flag signals in the corresponding pixel set module;

In the super column pixel module corresponding to the pixel set module, the super column controller generates an effective readout hit flag signal according to all pixel set hit flag signals generated in the corresponding super column pixel module;

When the read hit flag bit signal is valid, in the super column pixel module corresponding to the pixel set module, the super column controller generates an energy signal according to the electrical signals measured by all pixel units in the corresponding super column pixel module, and stores all effective pixels Set the data of the pixel set module corresponding to the hit flag bit signal;

In the column block pixel module corresponding to the pixel set module, the column block controller reads and stores the data stored in each super column controller;

The readout controller reads out all the data stored in the column block controller and transmits them to the outside.

Further, when a certain pixel unit is hit by a particle, the analog signal processing circuit in the pixel unit acquires the electrical signal generated by the incident particle, and generates a hit flag signal, including:

When a certain pixel unit is hit by a particle, the CMOS pixel sensor of the analog signal processing circuit in the pixel unit acquires the electrical signal generated by the incident particle;

The amplification circuit amplifies the electrical signal obtained by the CMOS pixel sensor;

The comparator performs threshold discrimination on the amplified electrical signal, and generates a hit flag signal when the electrical signal is greater than the threshold of the comparator;

The energy output circuit outputs the amplified electrical signal to the corresponding super column controller, and outputs the generated hit flag signal to the time-to-digital conversion circuit;

The digital signal processing and memory store the position information of the hit pixel unit and the electrical signal output by the corresponding energy output circuit, and transmit the stored information to the outside of the chip through the readout frame selection.

Further, when the read hit flag signal is valid, in the super column pixel module corresponding to the pixel set module, the super column controller generates an energy signal according to the electrical signals measured by all pixel units in the corresponding super column pixel module, And store the data of the pixel set module corresponding to all effective pixel set hit flag signals, including:

When the read hit flag signal is valid, in the super column pixel module corresponding to the pixel set module, the super column controller sequentially scans whether the corresponding pixel set hit flag signal is valid, if the pixel set hit flag signal If it is valid, the amplified electrical signal of each pixel unit in the pixel set module is output to the regional analog-to-digital converter, and the regional analog-to-digital converter is controlled to start sampling;

The area analog-to-digital converter is based on the control of the super column reader, and generates a digital energy signal according to the amplified electrical signal of each pixel unit corresponding to the effective pixel set hitting the flag signal;

The first FIFO memory stores the address of the first pixel unit in the pixel set module corresponding to the corresponding effective pixel set hit signal when the readout hit signal is valid, the time information of the pixel set module, and the pixel set The digital energy signal of all pixel units in the module.

The present invention has the following advantages due to the adoption of the above technical scheme:

1. In the present invention, since the time-to-digital conversion circuit and the super column controller are provided, the time-to-digital conversion circuit generates the pixel set hit flag signal, and the super column controller generates the readout hit signal according to the pixel set hit flag signal , the generated readout hit signal is used to control whether to scan, and whether to turn on the regional analog-to-digital converter, which can effectively reduce the power consumption brought by the regional analog-digital converter and improve the accuracy of time measurement.

2. Because the area occupied by the bus signal in the unit pixel unit is less, the pixel units in the pixel array of the present invention are grouped by columns, which is more advantageous.

3. In the present invention, when an effective readout hit flag signal is generated, the pixel set hit flag signal is checked one by one by the super column reader, which can effectively reduce the number of read pixels.

4. Both the column block controller and the readout controller in the present invention use token ring readout to read out data, which can increase the readout speed.

5. In the present invention, the pixel array is divided into pixel set modules, super column pixel modules and column block pixel modules, which can gradually detect and screen effective information and improve the transmission of effective data volume.

6. The present invention is provided with a super-column controller, which can not only turn on the regional analog-to-digital converter when the read hit flag signal is valid, thereby effectively reducing the power consumption brought by the regional analog-to-digital converter, but also can screen effective hits. Pixel set, unambiguously read out the position, time, and energy signal of a valid hit.

7. The present invention can simultaneously read out the digitized information of silicon pixel detector energy, time and position (pixel address).

In summary, the present invention can be widely applied in the technical field of semiconductor detectors.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiment. The drawings are only for the purpose of illustrating a preferred embodiment and are not to be considered as limiting the invention. Throughout the drawings, the same reference numerals are used to refer to the same parts. In the attached picture:

Fig. 1 is a schematic structural diagram of a readout system provided by an embodiment of the present invention;

2 is a schematic diagram of a signal processing process of an analog signal processing circuit provided by an embodiment of the present invention;

Fig. 3 is a schematic diagram of a specific implementation process of reading provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a chip-level readout method provided by an embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present invention, and to fully convey the scope of the present invention to those skilled in the art.

It should be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" may also be meant to include the plural forms unless the context clearly dictates otherwise. The terms "comprising", "comprising", "containing" and "having" are inclusive and thus indicate the presence of stated features, steps, operations, elements and/or parts but do not exclude the presence or addition of one or Various other features, steps, operations, elements, components, and/or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is specifically indicated. It should also be understood that additional or alternative steps may be used.

Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be referred to as These terms are limited. These terms may be only used to distinguish one element, component, region, layer or section from another region, layer or section. Terms such as "first," "second," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the example embodiments.

For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature as shown in the figures with respect to another element or feature, such as "inner", "outer", "inner". ", "Outside", "Below", "Above", etc. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

Due to the experimental requirements of particle physics experiments, the front-end circuit and detector signal processing circuit are always closely connected with the control readout logic. The hit information obtained by the front-end circuit must be further transmitted and processed by the control circuit and the readout circuit on the periphery of the chip. The method of readout depends largely on the target application. In applications in particle physics where more detailed information is required, the locations of all hits must be provided, often also times and corresponding pulse amplitudes. The choice of a suitable readout method depends primarily on the available chips and the acceptable hit loss. The silicon pixel detector readout system and method provided by the embodiments of the present invention can quickly read out the effective information of the hit signal, including energy, time and position information, and also consider the low power consumption performance of other modules of the circuit. Although existing pixel chips use different geometries, readout principles, and analog circuits, there are several blocks that are similar in build and characteristics in the main part of the design. Each pixel cell contains an analog signal processing circuit and in most cases digital logic for measuring and reading the measured data.

Example 1

As shown in FIG. 1 , this embodiment provides a silicon pixel detector readout system, including a pixel array 1 , wherein the pixel array 1 is composed of several pixel units 11 with M rows and N columns.

Every two columns of pixel units 11 in the pixel array 1 form a corresponding double column (Double Columns, DCol) pixel module 2, so as to share circuits between the pixel units 11 and reduce crosstalk between digital and analog parts. Adjacent n (n≤N) double-column pixel modules 2 form a corresponding super column (Super Colum) pixel module 3, and several super column pixel modules 3 form a corresponding column block pixel module 4 (Column Block). Every s×s (s≤n) pixel units 11 form a corresponding pixel set module 5 (Cluster).

As shown in Figures 1 and 3, the silicon pixel detector readout system also includes an analog signal processing circuit, a time-to-digital conversion circuit 6 (Time to Digital Converter, TDC), a super column controller 7 (Super Column Controller, SCC), Column Block Controller 8 (Column Block Controller, CBC) and Readout Controller 9 (Readout Controller).

Each pixel unit 11 is provided with an analog signal processing circuit for acquiring the electrical signal generated by the incident particle when the pixel unit 11 is hit by the particle, and generating a corresponding hit flag signal (hitflag).

Each pixel set module 5 is provided with a time-to-digital conversion circuit 6, and the time-to-digital conversion circuit 6 is used to measure the time information that the corresponding pixel set module 5 hits, and mark the hits of all pixel units 11 in the corresponding pixel set module 5 OR operation is performed on the bit signal to generate a pixel set hit flag signal (Cluster Hit), and the pixel set hit flag signal is used as the start signal of the time-to-digital conversion circuit 6.

Each super column pixel module 3 is provided with a super column controller 7 (SCC), and each super column controller 7 is respectively connected to the time-to-digital conversion circuit 6 of each pixel set module 5 in the corresponding super column pixel module 3 for Perform an OR operation on all the pixel set hit flag signals generated in the corresponding super column pixel module 3 to generate a readout hit flag signal (readout hit); according to the electrical signals measured by all pixel units 11 in the corresponding super column pixel module 3 , generate an energy signal; and store the address of the first pixel unit 11 in the pixel set module 5 corresponding to all effective pixel sets corresponding to the hit flag signal and the time information of the pixel set module 5 And energy signals of all pixel units 11 in the pixel set module 5 .

Each column block pixel module 4 is provided with a column block controller 8 (CBC), and each column block controller 8 is respectively connected to the super column controller 7 of each super column pixel module 3 in the corresponding column block pixel module 4 , the column block controller 8 is used to read and store the data stored in each super column controller 7 by means of token ring readout.

The readout controller 9 is respectively connected to each column block controller 8, and the readout controller 9 is used to read out the data stored in each column block controller 8 by means of token ring readout, and transmit the data to the outside.

In a preferred embodiment, the pixel units 11 in the pixel array 1 are grouped in columns, ie, the control signals and output data streams are routed vertically. Because of the principle that bus signals occupy less area in the pixel unit 11 , it is more advantageous to adopt the column-based formula of this embodiment.

In a preferred embodiment, as shown in FIG. 2 , each analog signal processing circuit includes a CMOS pixel sensor 12 , an amplification circuit 13 , a comparator 14 , an energy output circuit 15 and a digital signal processing and memory 16 .

The CMOS pixel sensor 12 is used to acquire the electrical signal generated by the incident particle when the pixel unit 11 is hit by the particle.

The amplification circuit 13 is used to amplify the electrical signal obtained by the CMOS pixel sensor 12 .

The comparator 14 is used to carry out threshold value identification on the amplified electrical signal. When the electrical signal is greater than the threshold value of the comparator 14, a hit flag signal is generated. When the hit flag signal is 1, it is valid, and when it is 0, it is invalid.

The energy output circuit 15 is used to output the amplified electrical signal to the corresponding super column controller 7 , and output the generated hit flag signal to the corresponding time-to-digital conversion circuit 6 .

The digital signal processing and memory 16 is used to store the position information of the hit pixel unit 11 and the electrical signal output by the corresponding energy output circuit 15, and transmit the stored information to the outside of the chip through the readout frame selection.

In a preferred embodiment, as shown in Figure 3, each super column controller 7 includes a super column reader 71 (Super Column Reader, SCR), a regional analog-to-digital converter 72 (Regional ADC) and a first FIFO memory 73 .

The super column reader 71 is used to perform an OR operation on all pixel set hit flag signals generated by the time-to-digital conversion circuit 6 in the corresponding super column pixel module 3 to generate a readout hit flag signal.

The super row reader 71 is also used for when the readout hit flag signal is effective, scan each corresponding pixel set sequentially from top to bottom whether the hit flag signal is valid (when it is 1, it is valid, when it is 0, it is is invalid), if the pixel set hit flag signal is invalid, then skip the pixel set module 5 to the next pixel set module 5; if the pixel set hit flag signal is valid, then each pixel set module 5 The amplified electrical signal of the pixel unit 11 is output to the local AD converter 72 , and the local AD converter 72 is controlled to start sampling, so as to effectively reduce the power consumption caused by the local AD converter 72 .

The area analog-to-digital converter 72 is used to generate an amplitude signal representing energy according to the amplified electrical signal of each pixel unit 11 corresponding to the effective pixel set hit flag signal based on the control of the super column reader 71, that is, Digital energy signal.

The first FIFO memory 73 is used to store the first pixel unit 11 (i.e. the pixel in the upper left corner in FIG. The address of the unit 11), the time information of the pixel set module 5 and the digital energy signals of all the pixel units 11 in the pixel set module 5.

In a preferred embodiment, as shown in FIG. 4 , each block controller 8 includes a token ring readout control module 81 and a second FIFO memory 82 .

The token ring readout control module 81 is used to read out the data stored in the first FIFO memory 73 in all the super column controllers 7 of the column block pixel module 4 in a token ring readout manner.

The second FIFO memory 82 is used to store the data read out by the token ring readout control module 81 to increase the readout speed of the block pixel modules 4 in each column.

Specifically, the generation process of reading out the hit flag signal is:

As shown in Figure 2, the comparator 14 of the analog signal processing circuit generates the hit flag signal, when the hit flag signal is 1, it is valid, and when it is 0, it is invalid, and all pixel units in the pixel set module 5 11 respectively output their corresponding hit flag signals, whether these hit flag signals are 0 or 1, they are all input to the corresponding time digital conversion circuit 6 to perform OR operation to generate pixel set hit flag signals, similarly, when the pixel set When the set hit flag bit signal is 1, it is valid, and when it is 0, it is invalid. As shown in FIG. 3 , each pixel set module 5 outputs its corresponding pixel set hit flag signal, whether these pixel set hit flag signals are 0 or 1, they are input to the corresponding super column controller 7 for OR operation Generate a read hit flag signal, when the read hit flag signal is 1, it is valid, and when it is 0, it is invalid.

Example 2

This embodiment provides a silicon pixel detector readout method, including the following steps:

1) Set up the silicon pixel detector readout system of Embodiment 1.

2) When a certain pixel unit 11 is hit by a particle, the analog signal processing circuit in the pixel unit 11 acquires the electrical signal generated by the incident particle, and generates a hit flag signal, specifically:

2.1) When a certain pixel unit 11 is hit by a particle, the CMOS pixel sensor 12 of the analog signal processing circuit in the pixel unit 11 acquires the electrical signal generated by the incident particle.

2.2) The amplifier circuit 13 of the analog signal processing circuit in the pixel unit 11 amplifies the electrical signal acquired by the CMOS pixel sensor 12 .

2.3) The comparator 14 of the analog signal processing circuit in the pixel unit 11 performs threshold value discrimination on the amplified electrical signal. When the electrical signal is greater than the threshold of the comparator 14, a hit flag signal is generated. When the hit flag signal is 1 It is valid, and it is invalid when it is 0.

2.4) The energy output circuit 15 of the analog signal processing circuit in the pixel unit 11 outputs the amplified electrical signal to the corresponding super column controller 7, and outputs the generated hit flag signal to the time-to-digital conversion circuit 6.

2.5) The digital signal processing of the analog signal processing circuit in the pixel unit 11 and the memory 16 store the position information of the hit pixel unit 11 and the electrical signal output by the corresponding energy output circuit 15, and the stored information is judged and transmitted through the readout framework to the outside of the chip.

3) In the pixel set module 5 corresponding to the pixel unit 11, the time-to-digital conversion circuit 6 performs an OR operation on the hit flag signals of all pixel units 11 in the corresponding pixel set module 5 to generate a pixel set hit flag signal, and The pixel set hitting flag bit signal is used as the start signal of the time-to-digital conversion circuit 6 .

4) In the super column pixel module 3 corresponding to the pixel set module 5, the super column controller 7 performs an OR operation on all pixel set hit flag signals generated in the super column pixel module 3 to generate an effective readout hit flag Signal.

Specifically, the super column reader 71 in the super column pixel module 3 corresponding to the pixel set module 5 performs an OR operation on all the pixel set hit flag signals generated by the time-to-digital conversion circuit 6 in the corresponding super column pixel module 3, Generate a read hit flag signal, when the read hit flag signal is 1, it is valid, and when it is 0, it is invalid.

5) When the read hit flag bit signal is valid, in the super column pixel module 3 corresponding to the pixel set module 5, the super column controller 7 generates energy according to the electrical signals measured by all pixel units 11 in the corresponding super column pixel module 3 signal, and store the address of the first pixel unit 11 in the pixel set module 5 corresponding to the effective readout hit flag signal, the time information of the pixel set module 5, and the pixel set corresponding to the hit flag signal. The energy signals of all pixel units 11 in the collection module 5 are specifically:

5.1) When the read hit flag signal is valid, in the super column pixel module 3 corresponding to the pixel set module 5, the super column controller 7 sequentially scans whether the corresponding pixel set hit flag signal is valid from top to bottom , if the pixel set hit flag signal is invalid, skip the pixel set module 5 to the next pixel set module 5; if the pixel set hit flag signal is valid, then each pixel unit 11 in the pixel set module 5 The amplified electrical signal is output to the regional analog-to-digital converter 72, and the regional analog-to-digital converter 72 is controlled to start sampling.

5.2) The area analog-to-digital converter 72 is based on the control of the super column reader 71, and generates an amplitude signal representing energy according to the amplified electrical signal of each pixel unit 11 corresponding to the effective pixel set hit flag signal, namely Digital energy signal.

5.3) The first first-in-first-out memory 73 stores the address of the first pixel unit 11 in the pixel set module 5 corresponding to the corresponding all effective pixel set hit flag signals, and the address of the pixel set module 5 when the readout hit signal is valid. Time information and digital energy signals of all pixel units 11 in the pixel set module 5 .

6) In the column block pixel module 4 corresponding to the pixel set module 5, the column block controller 8 reads out and stores the data stored in each super column controller 7 by means of token ring readout.

7) The readout controller 9 reads out all the data stored in the column block controller 8 by means of token ring readout, and transmits them to the outside.

The above-mentioned embodiments are only used to illustrate the present invention, wherein the structure, connection mode and manufacturing process of each component can be changed to some extent, and any equivalent transformation and improvement carried out on the basis of the technical solution of the present invention should not excluded from the protection scope of the present invention.

Claims (9)

1. A silicon pixel detector readout system, characterized in that, comprises a pixel array composed of some pixel units of M rows and N columns; Every two columns of pixel units in the pixel array form a corresponding dual-column pixel module, adjacent n double-column pixel modules form a corresponding super-column pixel module, and several super-column pixel modules form a corresponding A column block pixel module; several pixel units in the pixel array form a corresponding pixel set module, where n≤N; each of the pixel set modules includes s×s pixel units, s≤n; Each pixel unit is provided with an analog signal processing circuit, which is used to obtain the electrical signal generated by the incident particle when the pixel unit is hit by the particle, and generate a corresponding hit flag signal; Each of the pixel set modules is provided with a time-to-digital conversion circuit, which is used to measure the time information corresponding to the hit of the pixel set module, and generate a pixel set according to all hit flag signals in the corresponding pixel set module hit flag signal; Each of the super column pixel modules is provided with a super column controller, which is used to generate a readout hit flag signal according to the hit flag signal of all pixel sets in the corresponding super column pixel module; All electrical signals in the column pixel module generate energy signals; and store all effective pixel sets corresponding to the hit flag signal corresponding to all effective readouts and hit the data of the pixel set module corresponding to the flag bit signal; Each of the column block pixel modules is provided with a column block controller for reading and storing the data stored in each of the super column controllers; The readout controller is used to read out the data stored in each column block controller. 2. A kind of silicon pixel detector readout system as claimed in claim 1, is characterized in that, each described analog signal processing circuit all comprises: A CMOS pixel sensor, used to acquire the electrical signal generated by the incident particle when the pixel unit is hit by the particle; an amplification circuit, configured to amplify the electrical signal obtained by the CMOS pixel sensor; A comparator, configured to perform threshold discrimination on the amplified electrical signal, and generate a hit flag signal when the electrical signal is greater than the threshold of the comparator; The energy output circuit is used to output the amplified electrical signal to the corresponding super-column controller, and output the generated hit flag signal to the corresponding time-to-digital conversion circuit; The digital signal processing and memory are used to store the position information of hitting the pixel unit and the electrical signal corresponding to the output of the energy output circuit. 3. A kind of silicon pixel detector readout system as claimed in claim 1, is characterized in that, described time-to-digital conversion circuit carries out OR operation to generate a pixel set hit flag bit signal. 4. A kind of silicon pixel detector readout system as claimed in claim 1, is characterized in that, each described super row controller all comprises: The super column reader is used to perform an OR operation on all the pixel set hit flag signals corresponding to the super column pixel module to generate a readout hit flag signal; The super column reader is also used to sequentially scan whether the hit flag signal of each pixel set is valid when the read hit flag signal is valid, and output the said hit flag signal when the pixel set hit flag signal is valid. an amplified electrical signal of each pixel unit in the pixel set module; The area analog-to-digital converter is used to generate a digital energy signal based on the control of the super column reader, according to the amplified electrical signal of each pixel unit corresponding to the effective pixel set hit flag signal; The first first-in-first-out memory is used to store the address of the first pixel unit in the pixel set module corresponding to the corresponding all effective pixel set hit flag signals when the read hit signal is valid, the pixel The time information of the set module and the digital energy signals of all the pixel units in the pixel set module. 5. A kind of silicon pixel detector readout system as claimed in claim 1, is characterized in that, each described column block controller all comprises: The token ring readout control module is used to read out the data stored in all the super column controllers in the column block pixel module by means of token ring readout; The second FIFO memory is used for storing the data read by the token ring read control module. 6. A kind of silicon pixel detector readout system as claimed in claim 1, is characterized in that, described readout controller reads out the data stored in each described row block controller adopts token ring readout Way. 7. A silicon pixel detector readout method, characterized in that, comprising: The silicon pixel detector readout system according to any one of claims 1 to 6 is set; When a pixel unit is hit by a particle, the analog signal processing circuit in the pixel unit acquires the electrical signal generated by the incident particle and generates a hit flag signal; In the pixel set module corresponding to the pixel unit, the time-to-digital conversion circuit generates a pixel set hit flag signal according to all hit flag signals in the corresponding pixel set module; In the super column pixel module corresponding to the pixel set module, the super column controller generates an effective readout hit flag signal according to all pixel set hit flag signals generated in the corresponding super column pixel module; When the read hit flag bit signal is valid, in the super column pixel module corresponding to the pixel set module, the super column controller generates an energy signal according to the electrical signals measured by all pixel units in the corresponding super column pixel module, and stores all effective pixels Set the data of the pixel set module corresponding to the hit flag bit signal; In the column block pixel module corresponding to the pixel set module, the column block controller reads and stores the data stored in each super column controller; The readout controller reads out all the data stored in the column block controller and transmits them to the outside. 8. The silicon pixel detector readout method according to claim 7, wherein when a certain pixel unit is hit by a particle, the analog signal processing circuit in the pixel unit obtains the electrical signal generated by the incident particle , and generate a hit flag signal, including: When a certain pixel unit is hit by a particle, the CMOS pixel sensor of the analog signal processing circuit in the pixel unit acquires the electrical signal generated by the incident particle; The amplification circuit amplifies the electrical signal obtained by the CMOS pixel sensor; The comparator performs threshold discrimination on the amplified electrical signal, and generates a hit flag signal when the electrical signal is greater than the threshold of the comparator; The energy output circuit outputs the amplified electrical signal to the corresponding super column controller, and outputs the generated hit flag signal to the time-to-digital conversion circuit; The digital signal processing and memory store the position information of the hit pixel unit and the electrical signal output by the corresponding energy output circuit, and transmit the stored information to the outside of the chip through the readout frame selection. 9. The silicon pixel detector readout method according to claim 8, characterized in that, when the readout hit flag signal is effective, in the super column pixel module corresponding to the pixel set module, the super column controller according to Corresponding to the electrical signals measured by all pixel units in the super column pixel module, an energy signal is generated, and the data of the pixel set module corresponding to the hit flag signal of all effective pixel sets is stored, including: When the read hit flag signal is valid, in the super column pixel module corresponding to the pixel set module, the super column controller sequentially scans whether the corresponding pixel set hit flag signal is valid, if the pixel set hit flag signal If it is valid, the amplified electrical signal of each pixel unit in the pixel set module is output to the regional analog-to-digital converter, and the regional analog-to-digital converter is controlled to start sampling; The area analog-to-digital converter is based on the control of the super column reader, and generates a digital energy signal according to the amplified electrical signal of each pixel unit corresponding to the effective pixel set hitting the flag signal; The first FIFO memory stores the address of the first pixel unit in the pixel set module corresponding to the corresponding effective pixel set hit signal when the readout hit signal is valid, the time information of the pixel set module, and the pixel set The digital energy signal of all pixel units in the module.

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