CN114968099A

CN114968099A - NVM (non-volatile memory) access method and NVM controller

Info

Publication number: CN114968099A
Application number: CN202210539163.1A
Authority: CN
Inventors: 孙明浩; 王祎磊
Original assignee: Beijing Starblaze Technology Co ltd
Current assignee: Beijing Starblaze Technology Co ltd
Priority date: 2016-01-06
Filing date: 2016-01-06
Publication date: 2022-08-30
Also published as: CN106951374A; CN106951374B

Abstract

The invention discloses a method for accessing NVM and an NVM controller, comprising the following steps: processing a first user command for indicating reading an NVM by executing a microinstruction sequence, and checking whether a block address and a page address corresponding to the first user command are the same as a block address and a page address corresponding to a second user command according to a block/page read address check microinstruction in the microinstruction sequence, wherein the second user command indicates reading the NVM, and the second user command appears before the first user command; and if the block address and the page address corresponding to the first user command are the same as those corresponding to the second user command, reading data from a first cache corresponding to a first parallel unit to be accessed by the first user command for responding to the first user command. Through the technical scheme of the invention, a user of the storage equipment can participate in flexible control of cache utilization without depending on whether the data is cached or not judged by the storage controller.

Description

NVM (non-volatile memory) access method and NVM controller

Technical Field

The present invention relates to Solid State Storage Devices (SSDs), and more particularly, to the execution of block/page address checking microinstructions in a memory controller.

Background

Like mechanical hard disks, solid State Storage Devices (SSDs) are also large capacity, non-volatile storage devices for computer systems. Solid-state Memory devices generally use a Non-Volatile Memory (NVM), such as Flash Memory (Flash), as a storage medium. Fig. 1 is a block diagram of a prior art memory system. Which mainly includes a host system 110 and a solid-state storage device 120. The solid-state storage device 120 includes an interface module 130, a storage controller 140, and a Flash array 160 composed of a plurality of Flash memory granules 150. The Interface module 130 is mainly used for implementing an Interface protocol for communicating with a host System, such as SATA (Serial Advanced Technology Attachment), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express), nvme (nvm Express), SCSI (Small Computer System Interface), iSCSI (internet Small Computer System Interface), IDE (Integrated Drive Electronics), and the like. Through the interface module 130, the solid-state storage device presents to the host system a standard storage device that possesses a certain logical address space or physical address space. The memory controller 140 is a control core of the entire memory device, and is mainly responsible for transmission of control signals and data between the interface module 130 and the flash memory array 160, flash memory management, conversion or mapping of host logical addresses to flash memory physical addresses, wear leveling, and/or bad block management. The storage controller 140 may be implemented in a variety of ways, including software, hardware, firmware, or a combination thereof.

Memory controller 140 accesses flash granule 150 by sending commands to flash granule 150 in flash array 160. Commands to access the flash granule 150 include, for example, read, program, and/or erase, etc. Data is written to or read from the flash memory granule 150 on a page-by-page basis. The flash granule 150 provides a predetermined page size, each page being, for example, 2KB, 4KB, 8KB, or 16 KB.

The file system or device driver of the host 110 also accesses the storage device in data blocks of a predetermined size. A block of data of a predetermined size may be referred to as a block, a page, or a sector. Where the size of the data block is the same or different than the page size of flash granule 150.

In chinese patent application publication No. CN1414468A, a scheme is provided for Processing a CPU (Central Processing Unit) instruction by executing a micro instruction sequence. When the CPU is to process a specific instruction, the conversion logic circuit converts the specific instruction into a micro instruction sequence corresponding to the specific instruction, and the function of the specific instruction is realized by executing the micro instruction sequence. The micro instruction sequence or a template of the micro instruction sequence is stored in a ROM (Read Only Memory). In converting a particular instruction into a micro instruction sequence, the micro instruction sequence template may be populated to correspond to the particular instruction.

The memory Target (Target) is one or more Logic units (Logic units) that share a Chip Enable (CE) signal within the package of the flash memory particles 150. Each logical Unit has a Logical Unit Number (LUN). One or more dies (Die) may be included within the NAND flash memory package. Typically, a logic cell corresponds to a single die. The logical unit may include a plurality of planes (planes). Multiple planes within a logical unit may be accessed in parallel, while multiple logical units within a NAND flash memory chip may execute commands and report status independently of each other. The meaning for target, logical Unit, LUN, Plane (Plane) is provided in "Open NAND Flash Interface Specification (replacement 3.0)" available from http:// www.micron.com// media/Documents/Products/Other% 20Documents/ONF I3_0gold.

Chinese patent application publication No. CN102177556A discloses a Flash Translation Layer (FTL) which shows an example of a lookup table for parallel units of the FTL. Since the Logic units (Logic units) in the flash memory chip can be accessed in parallel, the parallel units may be Logic units. Multiple planes (planes) may be included within a logical unit, and parallel units may also be planes.

Disclosure of Invention

In some application scenarios, the page size of the NVM is different from the page size requested by the application. For example, the data unit size of an IO access request of an operating system is 512 bytes, while the page size of the NVM is 4KB, 8KB or 16 KB. After reading data from the NVM in response to an IO access request, a large amount of the read data is not used by the current IO request. But due to locality of data access or other reasons, data read from NVM may be used in subsequent IO access requests. Thus, when data needs to be read from a flash memory die, a flexible way of determining whether the data is already present in the memory controller's cache is desirable. There are various reasons why data is cached, and it is desirable to be able to adapt the manner in which it is determined whether data is already present in the cache of the storage controller to different reasons. And it is desirable that users of storage devices can engage in flexible control of cache utilization rather than relying on the storage controller to determine whether data is cached.

To achieve the above objects, the present invention responds to commands from a host or user through the execution of a sequence of micro instructions. Execution of the micro instruction sequence by the micro instruction execution unit issues operation commands to the flash memory granule and/or receives data or other information read from the flash memory granule. A user of the storage device can participate in flexible control of cache utilization by the storage controller through programming, updating, and/or modifying the micro-instruction sequence.

According to a first aspect of the present invention, there is provided a method of accessing an NVM, comprising: processing a first user command instructing to read NVM, checking whether a block address and a page address corresponding to the first user command are the same as a block address and a page address corresponding to a second user command instructing to read NVM, wherein the second user command occurs before the first user command, and the second command accesses the same first parallel unit as the first user command; and if the block address and the page address corresponding to the first user command are the same as those corresponding to the second user command, reading data from the first cache corresponding to the first parallel unit for responding to the first user command.

According to an embodiment of the first aspect of the present invention, further comprising: and if the block address and the page address corresponding to the first user command are different from the block address and the page address corresponding to the second user command, sending an NVM reading command to the NVM.

According to one embodiment of the first aspect of the present invention, a first cache is provided for a first user command to access a first parallel unit and a second cache is provided for a first user command to access a second parallel unit.

According to one embodiment of the first aspect of the present invention, in response to the second user command, data read out from the NVM corresponding to a block address and a page address corresponding to the second user command is written into the first buffer.

According to one embodiment of the first aspect of the present invention, if the block address and the page address corresponding to the first user command are the same as the block address and the page address corresponding to the second user command, a flag register is set; and clearing the mark register if the block address and the page address corresponding to the first user command are different from the block address and the page address corresponding to the second user command.

According to an embodiment of the first aspect of the present invention, if the block address and the page address corresponding to the first user command are the same as the block address and the page address corresponding to the second user command, skipping to execute the first micro instruction sequence to read out data from the first cache corresponding to the first parallel unit; and if the block address and the page address corresponding to the first user command are different from the block address and the page address corresponding to the second user command, skipping to execute a second micro-instruction sequence so as to send an NVM read command to the NVM.

According to one embodiment of the first aspect of the present invention, in response to the first user command, if the block address and the page address corresponding to the first user command are different from the block address and the page address corresponding to the second user command, the data corresponding to the block address and the page address corresponding to the first user command are further read from the NVM and written into the first buffer.

According to one embodiment of the first aspect of the present invention, the first user command corresponds to a first sector address, and the second user command corresponds to a second sector address.

According to one embodiment of the first aspect of the present invention, the first user command indicates to obtain data of a first address range, and the second user command indicates to obtain data of a second address range.

According to one embodiment of the first aspect of the present invention, in response to the second user command, page data corresponding to a block address and a page address corresponding to the second user command is read from the NVM and written to the first buffer, and the page data includes first sector data and second sector data.

According to an embodiment of the first aspect of the present invention, further comprising: and processing a third user command indicating reading the NVM, accessing a second parallel unit according to the third user command, and writing data read out from the NVM and corresponding to the block address and the page address corresponding to the third user command into a second cache.

According to one embodiment of the first aspect of the present invention, if the flag register is set, skipping execution of a first micro instruction sequence to read data from a first cache corresponding to the first parallel unit; and if the flag register is cleared, skipping to execute the second micro-instruction sequence so as to send out an NVM read command to the NVM.

According to a second aspect of the present invention, there is also provided a method of accessing an NVM, comprising: processing a first user command indicating reading NVM, checking whether a block address and a page address corresponding to the first user command are the same as a block address and a page address corresponding to a second user command, wherein the second user command indicates writing NVM, the second user command occurs before the first user command, and the second command accesses the same parallel unit as the first user command; and if the block address and the page address corresponding to the first user command are the same as the block address and the page address corresponding to the second user command, reading data from the cache corresponding to the parallel unit for responding to the first user command.

According to an embodiment of the second aspect of the invention, further comprising: and if the block address and the page address corresponding to the user command are different from the block address and the page address corresponding to the second user command, sending an NVM reading command to the NVM.

According to a third aspect of the present invention, there is also provided an NVM controller comprising: a micro instruction memory for storing a micro instruction sequence; the microinstruction execution unit is used for decoding the microinstruction and executing the operation corresponding to the microinstruction; a program counter for indicating a storage location of the microinstructions in the microinstruction memory; a general purpose register set, wherein registers in the general purpose register set are accessible by microinstructions in the microinstruction sequence; a user command storage for storing user commands; and the context memory is used for storing context information corresponding to the micro-instruction sequence.

According to one embodiment of the third aspect of the present invention, the microinstruction execution unit fetches a first microinstruction from the microinstruction memory according to a program counter; the microinstruction execution unit decodes the first microinstruction, and when the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses a user command memory according to an offset value of the read address check microinstruction to obtain a first block address and a first page address; the microinstruction execution unit accesses the context memory and obtains a second block address and a second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares a first block address with a second block address and a first page address with a second page address, and if the first block address is the same as the second block address and the first page address is the same as the second page address, the microinstruction execution unit sets a general register indicated by a register index in a general register group according to the register index of the read address check microinstruction.

According to an embodiment of the third aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the microinstruction execution unit clears the general register indicated by the register index in the general register set according to the register index of the read address check microinstruction; and the microinstruction execution unit increments the program counter.

According to one embodiment of the third aspect of the present invention, the microinstruction execution unit accesses the user command memory and further obtains a first parallel unit address; and the micro-instruction execution unit accesses a user command memory and obtains a second block address and a second page address stored in the context information of the current micro-instruction sequence according to the first parallel unit address.

According to an embodiment of the third aspect of the present invention, in which the execution of the microinstruction sequence is initiated in response to a user command in the user command memory, the first context memory is executed for the microinstruction sequence in accordance with the parallel unit accessed by the user command, and the microinstruction execution unit accesses the first context memory to obtain the second block address and the second page address stored in the context information of the current microinstruction sequence.

According to a fourth aspect of the present invention, there is also provided an NVM controller comprising: a micro instruction memory for storing a micro instruction sequence; the micro instruction execution unit is used for decoding the micro instruction and executing the operation corresponding to the micro instruction; a program counter for indicating a storage location of the microinstructions in the microinstruction memory; a user command storage for storing user commands; and the context memory is used for storing context information corresponding to the micro-instruction sequence.

According to an embodiment of the fourth aspect of the present invention, the microinstruction execution unit fetches a first microinstruction from the microinstruction memory according to the program counter, decodes the first microinstruction, and when the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses the user command memory according to the offset value of the read address check microinstruction to fetch a first block address and a first page address; the microinstruction execution unit accesses the context memory and obtains a second block address and a second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares a first block address with a second block address and a first page address with a second page address, wherein if the first block address is the same as the second block address and the first page address is the same as the second page address, the microinstruction execution unit sets the program counter according to the first address of the read address check microinstruction; if the first block address is different from the second block address or the first page address is different from the second page address, the microinstruction execution unit increments the program counter to the second address.

According to an embodiment of the fourth aspect of the present invention, the microinstruction execution unit fetches a first microinstruction from the microinstruction memory according to the program counter, decodes the first microinstruction, and when the first microinstruction is a read address check microinstruction, the microinstruction execution unit accesses the user command memory according to the offset value of the read address check microinstruction to fetch a first block address and a first page address; the microinstruction execution unit accesses the context memory and obtains a second block address and a second page address stored in the context information of the current microinstruction sequence; the microinstruction execution unit compares a first block address with a second block address and a first page address with a second page address, wherein if the first block address is different from the second block address or the first page address is different from the second page address, the microinstruction execution unit sets the program counter according to the first address of the read address check microinstruction; if the first block address is the same as the second block address and the first page address is the same as the second page address, the microinstruction execution unit increments the program counter to the second address.

According to one embodiment of the fourth aspect of the present invention, the context memory further stores therein data read out in the second block address and the second page address of the NVM before processing the user command.

According to one embodiment of the fourth aspect of the present invention, wherein the context memory further stores therein data written into a second block address and a second page address of the NVM prior to processing the user command.

According to one embodiment of the fourth aspect of the present invention, the micro instruction memory stores a sequence of micro instructions for fetching data from a cache starting from the first address.

According to one embodiment of the fourth aspect of the present invention, the microinstruction memory stores, starting from the second address, a microinstruction sequence for issuing NVM read commands to NVM.

According to one embodiment of the fourth aspect of the present invention, the microinstruction memory stores, starting from the first address, a microinstruction sequence for issuing an NVM read command to an NVM.

According to one embodiment of the fourth aspect of the present invention, the micro instruction memory stores a micro instruction sequence for fetching data from a cache starting from the second address.

According to a fifth aspect of the present invention, there is also provided a method of executing a read address check microinstruction in an NVM interface controller, comprising: fetching a first microinstruction; decoding the first microinstruction, and determining that the first microinstruction is a read address check microinstruction, wherein the read address check microinstruction comprises a register index and an offset value, the register index is used for indicating a flag register for storing an execution result of the read address check instruction, and the offset value is used for indicating a storage location of a user command; acquiring a first block address and a first page address corresponding to the user command according to the offset value; acquiring a second block address and a second page address according to the context information of the read address check micro-instruction, and setting a flag register according to a register index if the first block address is the same as the second block address and the first page address is the same as the second page address; and clearing the flag register according to the register index if the first block address is different from the second block address or the first page address is different from the second page address.

According to a sixth aspect of the present invention, there is also provided a method of executing a read address check microinstruction in an NVM interface controller, comprising: fetching the read address check microinstruction, wherein the read address check microinstruction comprises a register index and an offset value, the register index is used for indicating a flag register for storing an execution result of the read address check instruction, and the offset value is used for indicating a storage position of a user command; decoding the read address check microinstruction; obtaining a first block address and a first page address corresponding to the user command according to the deviation value; acquiring a second block address and a second page address according to the context information of the read address check micro-instruction, and setting a flag register according to a register index if the first block address is the same as the second block address and the first page address is the same as the second page address; and if the first block address is different from the second block address or the first page address is different from the second page address, clearing the flag register according to the register index.

According to one embodiment of the sixth aspect of the present invention, the second block address and the second page address are a block address and a page address of the accessing NVM corresponding to a user command occurring before the user command.

According to one embodiment of the sixth aspect of the present invention, the user command indicates to read data of a storage location corresponding to the first block address and the first page address of the NVM.

According to one embodiment of the sixth aspect of the present invention, wherein the remaining user commands are commands instructing reading data from or writing data to the NVM.

According to a seventh aspect of the present invention, there is also provided a method of executing a read address check microinstruction in an NVM interface controller, comprising: fetching the read address check microinstruction, wherein the read address check microinstruction comprises a register index and an offset value, the register index is used for indicating a flag register for storing an execution result of the read address check instruction, and the offset value is used for indicating a storage position of a user command; decoding the read address check microinstruction; acquiring a first parallel unit address, a first block address and a first page address corresponding to the user command according to the deviation value; acquiring a second block address and a second page address according to the first parallel unit address, wherein if the first block address is the same as the second block address and the first page address is the same as the second page address, a flag register is set according to a register index; and if the first block address is different from the second block address or the first page address is different from the second page address, clearing the flag register according to the register index.

According to one embodiment of the seventh aspect of the present invention, the second block address and the second page address are the block address and the page address of the accessed NVM corresponding to the rest of the user commands occurring before the user command.

According to one embodiment of the seventh aspect of the present invention, the user command indicates to read data of a storage location corresponding to the first block address and the first page address of the NVM.

According to one embodiment of the seventh aspect of the present invention, wherein the remaining user commands are commands instructing reading data from or writing data to the NVM.

According to an eighth aspect of the present invention, there is also provided a method of executing a read address check microinstruction in an NVM interface controller, comprising: fetching the read address check microinstruction, wherein the read address check microinstruction comprises a register index and an offset value, the register index is used for indicating a flag register for storing an execution result of the read address check instruction, the offset value is used for indicating a storage location of a user command, and the read address check instruction further comprises a first address; decoding the read address check microinstruction; acquiring a first block address and a first page address corresponding to the user command according to the offset value; acquiring a second block address and a second page address according to the context information of the read address check micro-instruction, wherein if the first block address is the same as the second block address and the first page address is the same as the second page address, a program counter of the NVM interface controller is set to be the first address; wherein the sequence of micro instructions to fetch data from the cache is stored beginning at the first address.

According to one embodiment of the eighth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the program counter of the NVM interface controller is set to the second address; wherein the second address begins storing a sequence of microinstructions that issue an NVM read command to the NVM.

According to an embodiment of the eighth aspect of the present invention, if the first block address is the same as the second block address and the first page address is the same as the second page address, the method further includes: and setting a flag register according to the register index.

According to an embodiment of the eighth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the method further comprises: the flag register is cleared according to the register index.

According to a ninth aspect of the present invention, there is also provided a method of executing a read address check microinstruction in an NVM interface controller, comprising: fetching the read address check microinstruction, wherein the read address check microinstruction comprises a register index and an offset value, the register index is used for indicating a flag register for storing an execution result of the read address check instruction, the offset value is used for indicating a storage location of a user command, and the read address check instruction further comprises a first address; decoding the read address check microinstruction; acquiring a first block address and a first page address corresponding to the user command according to the offset value; acquiring a second block address and a second page address according to the context information of the read address check micro-instruction, and setting a program counter of the NVM interface controller to be the first address if the first block address is the same as the second block address and the first page address is different from the second page address; wherein a sequence of microinstructions that issue NVM read commands to the NVM is stored beginning with the first address.

According to one embodiment of the ninth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the program counter of the NVM interface controller is set to the second address; wherein the second address begins storing a sequence of micro instructions that fetch data from a cache.

According to an embodiment of the ninth aspect of the present invention, if the first block address is the same as the second block address and the first page address is the same as the second page address, the method further includes: and setting a flag register according to the register index.

According to an embodiment of the ninth aspect of the present invention, if the first block address is different from the second block address, or the first page address is different from the second page address, the method further includes: the flag register is cleared according to the register index.

According to a tenth aspect of the present invention there is provided a computer program comprising computer program code to, when loaded into a computer system and executed thereon, cause said computer system to perform the method as described above.

According to an eleventh aspect of the present invention there is provided a program comprising program code which, when loaded into and executed on a storage device, causes the storage device to carry out the method described above.

By the technical scheme of the invention, whether the data exists in the cache of the storage controller or not can be flexibly judged, and a user of the storage equipment can participate in flexible control of cache utilization without depending on the storage controller to judge whether the data is cached or not.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. Wherein like reference numerals are followed by like parts throughout the several views, the last letter designation thereof will be omitted when referring generally to these parts. In the drawings:

FIG. 1 shows a block diagram of a prior art storage system;

FIG. 2 illustrates a block diagram of the components of a memory controller that process microinstructions, according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating the format of a block/page read address check microinstruction according to one embodiment of the present invention;

FIG. 4-1 illustrates a flow diagram of a method of accessing an NVM according to one embodiment of the present invention;

FIG. 4-2 illustrates a flow diagram of a method of accessing an NVM according to one embodiment of the present invention;

4-3 illustrate a flow diagram of a method of accessing an NVM according to one embodiment of the present invention;

FIG. 5 shows a flowchart of a method of accessing an NVM according to another embodiment of the present invention;

FIG. 6A illustrates a flow diagram of a method of executing a read address check microinstruction in an NVM interface controller according to one embodiment of another aspect of the present invention;

FIG. 6B illustrates a flowchart of a method of performing a read address check microinstruction and its subsequent operations in an NVM interface controller, according to another embodiment of another aspect of the present invention;

FIG. 7A illustrates a flow diagram of a method of executing a read address check microinstruction in an NVM interface controller according to one embodiment of another aspect of the present invention; and

FIG. 7B illustrates a flowchart of the method of executing a read address check microinstruction and its subsequent operations in an NVM interface controller, according to one embodiment of another aspect of the present invention.

In the drawings, the same or similar reference numbers are used to refer to the same or similar elements.

Detailed Description

The invention is further described with reference to the following figures and detailed description of embodiments.

FIG. 2 illustrates a block diagram of the components of a memory controller that process microinstructions, according to one embodiment of the present invention. To enable processing of microinstructions, a memory controller of the storage device may include a microinstruction execution unit 210, a command queue 220, an interface controller 230, a microinstruction memory 240, a context memory 260, and/or general purpose registers 250.

The micro instruction memory 240 is used to store micro instructions. The microinstruction execution unit 210 reads and executes the microinstructions from the microinstruction memory 240. The microinstructions cause the microinstruction execution unit 210 to issue commands to the flash granule, including, for example, commands to read, program, erase, pause, read and/or set flash granule characteristics, to the flash granule through the interface controller 230. The micro instructions also cause the micro instruction execution unit 210 to obtain data read from the flash granule through the interface controller 230. The micro instruction or micro instructions may correspond to one of the commands to read, program, erase, and/or suspend, etc., access the flash memory granule. The microinstructions also include branch, jump microinstructions that cause the microinstruction execution unit to change the order in which the microinstructions are executed. The microinstructions also include a block/page read address check microinstruction. The block/page read address check microinstructions are described in detail below in conjunction with FIG. 3.

One or more micro instruction sequences may be stored in the micro instruction memory 240. By way of example, n micro instruction sequences are stored in the micro instruction memory 240 of FIG. 2, including micro instruction sequence 1, micro instruction sequence 2 … …, and micro instruction sequence n. Each of the micro instruction sequence 1, the micro instruction sequence 2 … …, and the micro instruction sequence n includes a plurality of micro instructions.

Multiple microinstructions in the microinstruction sequence may be executed by the microinstruction execution unit 210. Each micro instruction sequence has its own execution state so that execution of each micro instruction can be suspended and resumed. The microinstruction execution unit 210 is capable of suspending the microinstruction sequence being executed and selecting execution of other microinstruction sequences. Yield microinstructions may also be provided in the microinstruction sequence, and when the yield microinstructions are executed, the microinstruction execution unit 210 may schedule and execute other microinstruction sequences. When the microinstruction execution unit 210 suspends the microinstruction sequence being executed or executes the yield microinstruction, the execution state of the microinstruction sequence being executed is saved; when the microinstruction execution unit resumes execution of the microinstruction sequence, the saved execution state is read out, thereby resuming execution of the resumed microinstruction sequence.

Interface controller 230 is coupled to the flash granule for issuing commands to the flash granule to access the flash granule, including, for example, read, program, erase, suspend and/or resume, etc.; and also for obtaining data read from the flash memory granule.

The command queue 220 is used to buffer commands from a user or an upper system. Commands from a user or upper system may include read, write, delete, mark as invalid, and may also include read storage device status, read/set flash granule feature, and may also include user-defined commands. The command queue 220 may be implemented by memory, a first-in-first-out memory register file, or the like. The microinstruction execution unit 210 may access the command queue 220. For example, upon execution of a microinstruction, the microinstruction execution unit 210 accesses the command queue 220 based on the microinstruction.

When a command in the command queue 220 is processed, a micro instruction sequence corresponding to the command is obtained and executed by the micro instruction execution unit 210 to complete the processing of the command in the command queue 220. The conversion from commands in the process command queue 220 to a sequence of microinstructions may be accomplished by conversion circuitry (not shown). The conversion from commands in the process command queue 220 to micro instruction sequences may also be implemented by the micro instruction execution unit 210. In retrieving the microinstruction sequence, the microinstruction sequence may be stuffed or adapted based on the commands in the command queue 220 to conform the microinstruction sequence to the commands in the command queue 220. The micro instruction sequence also controls the micro instruction execution unit 210 to access and process commands in the command queue 220. And selects the corresponding micro instruction sequence to be executed according to the commands in the command queue 220.

General purpose registers 250 are coupled to the microinstruction execution unit 210 for saving and providing the execution state of the microinstruction sequences. The execution state of the micro instruction sequence includes a Program Counter (PC), general purpose registers (GR), physical address registers and/or timers, etc. The program counter is used to indicate the address of the currently executing microinstruction in the microinstruction sequence. The physical address register is used to indicate the address of the flash granule accessed by the micro instruction sequence.

The context memory 260 is used to store the execution state of the micro instruction sequences. The execution state of the microinstruction sequence held by the context memory 260 may include the contents of the general purpose registers 250. In context memory 260, the execution state of one or more microinstruction sequences may be saved. The micro instruction sequences, which have state information stored in context memory 260, may be scheduled to resume execution. The microinstruction execution unit 210 may resume execution of a sequence of microinstructions by restoring state information corresponding to the sequence of microinstructions stored in the context memory 260 into the general purpose registers 250. The sequence of microinstructions that are executed is referred to as a thread. The same micro instruction sequence has its own execution state at each execution, so that multiple threads can be created based on the same micro instruction sequence. In the context memory 260, an execution state is stored for each thread.

In an embodiment according to the invention, threads are created or used based on the parallel units to be accessed. For example, a 1 st thread is used to access a 1 st parallel unit and/or a 2 nd thread is used to access a 2 nd parallel unit. In one example, context memory 260 may accommodate the same number of threads as the number of parallel units of the flash granule to which the means for processing microinstructions of FIG. 2 are coupled; allocating or reserving threads for each parallel unit; when a request for a parallel unit is processed, the thread corresponding to the parallel unit is scheduled. In one example, the context memory 260 may accommodate a number of threads that is less than the number of parallel units coupled to the means for processing microinstructions of FIG. 2. When processing a request for a parallel unit, the thread that has been assigned to process the parallel unit is used or a new thread is assigned to process the request.

Parallel unit buffers are provided to store data read from or written to the parallel units. Parallel unit caching is provided for each thread. The size of the parallel unit buffer corresponds to the page size of the flash granule 150 (see fig. 1). Providing a larger size of parallel unit cache is advantageous for improved performance. In one example, a parallel unit cache is provided in context memory 260. In another example, the parallel unit cache is provided by DRAM or other memory external to the component of FIG. 2 that processes the microinstructions.

FIG. 3 illustrates the format of a block/page read address check microinstruction according to an embodiment of the present invention. The block/page read address check microinstruction includes an OpCode (OpCode) field, a register (Reg) field, and an Offset field. The opcode field indicates that the microinstruction is a block/page read address check microinstruction by a particular identifier or value. The register field indicates the name or number of the general register (see FIG. 2, general register 250) that is modified by the block/page read address check microinstruction. The offset value field indicates the location in the command queue 220 (see FIG. 2) of the command to which the block/page read address check microinstruction corresponds. In one example, the offset value field indicates the storage location of the command to be examined in the command queue 220. For example, the command to be checked is a read command or a program command that is processed before the command currently being processed.

In one example, the value indicated by the offset value field is accumulated at the base address to obtain the location of the command in the command queue 220. Note that the base address field is not included in the block/page read address check microinstruction, but rather a global base address register or base address index is provided for the thread or individual microinstruction so that the base address is available when the block/page read address check microinstruction is executed. In another example, the offset value field alone is used to obtain the storage location of the command in the command queue 220. In yet another example, the offset value field indicates the offset of the command with check from the command currently being processed. In yet another example, the offset value field is a register address or number, such that the contents of the register can be modified by execution of the micro instruction sequence to modify the offset value information at runtime.

In the commands within command queue 220, the parallel cell address, block address, and page address accessed by the command are provided such that the particular block and page of a particular flash granule 150 (see FIG. 1) may be determined based on the parallel cell address, block address, and page address. For example, the combination of a block address and a page address provided by a command indexed by the offset value field in the command queue 220 (refer to fig. 2) is denoted by user _ cmd [ base + offset ]. block _ page _ address.

In an embodiment according to the invention, a block address register and a page address register are provided for each thread, which can serve as thread contexts, for storing block addresses and page addresses, respectively. The block address and page address may be stored in a variety of ways, such as storing the block address and page address combination in the same register. For example, a combination of a block address and a page address as a context of a certain thread is represented by block _ page _ address. Microinstructions belonging to the same thread may access block addresses and page addresses as thread contexts.

In executing a block/page read address check microinstruction according to the present invention, the microinstruction execution unit 210 (see fig. 2) compares whether the block address and page address as the thread context are the same as the block address and page address of the command in the command queue 220 processed by the thread, and if so, checks the general register set indicated by the register (Reg) field of the microinstruction at the block/page read address. If the block address and page address of the context as a thread is different from the block address and page address of the command in the command queue 220 being processed by the thread, the general purpose register indicated by the register (Reg) field of the block/page read address check microinstruction is cleared. A register set operation may correspond to writing a logical "1" or a logical "0" at a particular location of a register, where a register clear operation writes a value opposite to the register set operation. By way of example, the semantics of the block/page read address check microinstruction are represented as follows: GR [ Reg ] (block _ page _ address)? 1:0. When block _ page _ address is the same as user _ cmd [ base + offset ]. block _ page _ address, set general register GR [ Reg ] to 1, otherwise to 0.

In an embodiment in accordance with the invention, a conditional branch microinstruction is also provided. The conditional branch microinstructions, when executed, check the specified general purpose registers. The conditional branch microinstruction sets a Program Counter (PC) to one of two different values, depending on whether the specified general purpose register is set or cleared, to instruct the microinstruction execution unit 210 to fetch the next microinstruction to be executed from a different location in the microinstruction memory 240.

In yet another embodiment according to the present invention, a merge microinstruction is provided that combines the operation of a block/page read address check microinstruction with a conditional branch microinstruction. The fused microinstruction, in addition to an OpCode (OpCode) field, a register (Reg) field, and an Offset field, includes a branch target field.

In executing the fused microinstruction, the microinstruction execution unit 210 (see FIG. 2) compares the block address and page address as the thread context with the block address and page address of the command in the command queue 220 being processed by the thread. Depending on the comparison, the Program Counter (PC) is set to a different value to instruct the microinstruction execution unit 210 to fetch the next microinstruction to be executed from a different location in the microinstruction memory. For example, when the comparison result is true, the microinstruction execution unit 210 is instructed to fetch the microinstruction to be executed from the address of the next microinstruction of the current microinstruction; and when the comparison result is false, the microinstruction execution unit 210 is instructed to fetch the microinstruction to be executed from the address indicated by the branch target field. In this manner, the conditional branch semantics are fused into the execute block/page read address check microinstructions without having to use separate block/page read address check microinstructions and conditional branch microinstructions, thereby reducing the length of the microinstruction sequence and reducing the storage space occupied by the microinstruction sequence in the microinstruction memory 240.

In another embodiment according to the present invention, in executing yet another fused microinstruction, the microinstruction execution unit 210 (see FIG. 2) compares the block address and page address as the thread context with the block address and page address of the command in the command queue 220 being processed by the thread. Setting a Program Counter (PC) to different values to instruct the microinstruction execution unit 210 to fetch a next microinstruction to be executed from a different location in the microinstruction memory based on the comparison; and the general register indicated by the register (Reg) field of the block/page read address check microinstruction is set or cleared.

FIG. 4-1 shows a flow diagram of a method of accessing an NVM according to one embodiment of the present invention.

As shown in FIG. 4-1, a method of accessing an NVM includes: step 410: processing the first user command; step 420: checking whether the block address and the page address of the first user command are the same as the block address and the page address corresponding to the second user command; step 430: and if the block address and the page address of the first user command are the same as those corresponding to the second user command, the data are obtained from the first cache.

At step 410, the first user command is, by way of example, a first read command, and processing of the first read command begins. Referring back to FIG. 2, the next pending processor's command is fetched from the command queue 220 and determined to be the first read command. The microinstruction execution unit 210 executes the corresponding microinstruction sequence to process the first read command. In step 420, the microinstruction execution unit 210 executes a block/page read address check microinstruction (see also fig. 3) provided according to the present invention to determine whether the block address and/or page address of the first read command is the same as the block address and/or page address of the second user command. The second user command is a command that the microinstruction execution unit 210 fetches and processes from the command queue 210 before processing the first read command. If so, proceed to step 430, obtain the data required by the first read instruction from the cache. In an embodiment according to the invention, the second user command may be a read command or a write command, and when processing the second user command, data corresponding to the block address and/or the page address of the second user command is carried into the cache. Therefore, when the first read command and the second user command have the same block address and/or page address, the data required by the first read command is already in the cache, the data to be read by the first read command can be obtained from the cache, and the NVM read command does not need to be issued, so that the processing speed of the first read command is increased.

FIG. 4-2 shows a flow diagram of a method of accessing an NVM according to one embodiment of the present invention.

As shown in fig. 4-2, a method of accessing an NVM includes: step 410: processing the first user command; step 420: checking whether the block address and the page address of the first user command are the same as the block address and the page address corresponding to the second user command; step 430: and if the block address and the page address of the first user command are the same as the block address and the page address corresponding to the second user command, acquiring the data from the first cache. The method of accessing an NVM shown in fig. 4-2 further includes the step 440 of: and if the block address and the page address of the first user command are not the same as the block address and the page address corresponding to the second user command, sending an NVM read command to the NVM.

Fig. 4-3 shows a flow diagram of a method of accessing an NVM according to one embodiment of the present invention.

As shown in fig. 4-3, a method of accessing an NVM includes: step 410: processing the first user command; step 420: checking whether the block address and the page address of the first user command are the same as the block address and the page address corresponding to the second user command; step 430: if the block address and the page address of the first user command are the same as the block address and the page address corresponding to the second user command, data are obtained from the first cache; step 440: and if the block address and the page address of the first user command are different from the block address and the page address corresponding to the second user command, sending an NVM read command to the NVM. The method for accessing an NVM shown in fig. 4-3, after issuing an NVM read command to the NVM in step 440, further comprises step 450: data is read from the NVM and written to the first buffer.

In step 450, in response to a second user command, data read from NVM corresponding to a block address and a page address corresponding to the second user command is written to the first cache.

In a further embodiment, a dedicated cache is allocated for each parallel unit (LUN) of the NVM, so that when accessing the cache (e.g. moving data to or from the cache), the address of the cache can be easily obtained and the overhead of cache management is reduced.

Example 1

In embodiment 1 according to the present invention, a plurality of sectors are included in a page of NVM, a first read command accesses the same parallel unit as a second user command, and carries the same block address and page address, but different sectors are accessed, where the first command accesses a first sector and the second user command accesses a second sector. The second user command is a read command and is placed in the command queue (see FIG. 2, command queue 220) prior to the first read command. While the second user command reads the second sector of data, the NVM interface can transfer the data in page size, and upon accessing the NVM according to the second user command, transfer the entire page of data including the second sector into the cache. The first read command is then placed into the command queue 220. The first read command is processed by executing the microinstructions (see FIG. 4-1, step 410). The block/page read address check microinstruction is executed, the block address and the page address of the first read command and the second user command are compared (see fig. 4-1, step 420), and the block address of the first read command is found to be the same as the block address of the second user command, and the page address of the first read command is found to be the same as the page address of the second user command. This means that the data required for the first read command has been moved into the cache due to the execution of the second user command. By way of example, a block/page read address check microinstruction is executed, which sets a flag in a general purpose register (see FIG. 2, general purpose register 250) depending on the result of the comparison. The next micro instruction determines to execute the micro instruction corresponding to step 430 according to the set flag. Thus, execution of the microinstructions continues to fetch data from the cache (see FIG. 4-1, step 430). In this way, the data to be accessed can be obtained without issuing a data read command to the NVM, the execution time of the first read command is saved, and the efficiency is improved.

Example 2

In embodiment 2 according to the present invention, the page is a basic unit for reading the NVM, and the first read command and the second user command access the same parallel unit and carry the same block address and page address. The second user command is a read command and is placed in the command queue (see FIG. 2, command queue 220) prior to the first read command. The first read command and the second user command are thus consecutive read commands to the same address. The entire page of data is transferred to the cache upon accessing the NVM according to the previous second user command. The first read command is then placed into the command queue 220. The first read command is processed by executing the microinstructions (see FIG. 4-1, step 410). A block/page read address check microinstruction is executed, the block address and page address of the first read command and the second user command are compared (step 420), and it is found that the block address of the first read command is the same as the block address of the second user command and the page address of the first read command is the same as the page address of the second user command. This means that the data required for the first read command has been moved into the cache due to the execution of the second user command. Thus, the micro instructions continue to be executed to retrieve data from the cache (step 430). In this way, the data to be accessed can be obtained without issuing a data read command to the NVM, the execution time of the first read command is saved, and the efficiency is improved.

Example 3

In embodiment 3 according to the present invention, the page is a basic unit for reading the NVM, and the first read command and the second user command access the same parallel unit. But the first read command and the second user command carry different block addresses and/or page addresses. The second user command is a read command and is placed in the command queue (see FIG. 2, command queue 220) prior to the first read command. The entire page of data is transferred to the cache upon accessing the NVM according to the previous second user command. The first read command is then placed into the command queue 220. The first read command is processed by executing a microinstruction (see fig. 4-3, step 410). A block/page read address check microinstruction is executed, the block address and the page address of the first read command and the second user command are compared (step 420), and the block address of the first read command is found to be different from the block address of the second user command or the page address of the first read command is found to be different from the page address of the second user command. The data required by the first read command is not in the cache with a high probability. By way of example, a block/page read address check microinstruction is executed, which sets a flag in a general register (see FIG. 2, general register 250) depending on the result of the comparison. The next micro instruction determines to execute the micro instruction corresponding to step 440 according to the set flag. Thus, the micro instructions continue to be executed to issue NVM read commands to the NVM (step 440). The microinstructions issue the NVM read command by operating the interface controller (see fig. 2, interface controller 230). And receiving data read from the NVM by executing the micro instructions and writing the data to the cache (step 450). When the block address and the page address of the third user command appearing in the command queue (refer to fig. 2, command queue 220) after the first read command are the same as the block address and the page address of the first read command, respectively, it means that the data to be accessed by the third user command is already present in the buffer. The data required by the third user command can be retrieved from the cache without issuing a data read command to the NVM.

FIG. 5 shows a flowchart of a method of accessing an NVM according to another embodiment of the present invention. By executing the micro instruction sequence, the micro instruction execution unit 210 (see FIG. 2) is caused to perform the method of accessing the NVM shown in FIG. 5.

As shown in fig. 5, a method of accessing an NVM includes: step 510: processing the first read command; step 520: reading first data from the NVM, and writing the first data into a first cache; step 530: processing the second read command: step 540: checking whether a block address and a page address of the first read command are the same as a block address and a page address of the second read command; step 550: if the block address and the page address of the first read command are the same as those of the second read command, acquiring first data from the first cache; step 560: if the block address and the page address of the first read command are different from the block address and the page address of the second read command, sending an NVM read command; step 570: second data read from the NVM is retrieved and written to the cache.

At step 510, upon the occurrence of an unprocessed first read command in the command queue 220 (shown in FIG. 2), the first read command is processed by executing the micro instruction sequence. At step 520, data is read from the NVM according to the first read command by executing the micro instruction sequence and the read data is written to the cache. In one example, when data is read from the NVM in accordance with a first read command, a block/page read address check microinstruction in accordance with the present invention is also executed and it is determined that the block address and page address of the first read command are different from the block address and page address of the previous read/write command, thereby sending the NVM read command to the NVM in accordance with the first read command. In another example, it is determined that the data required by the first read command is not present in the buffer, based on whether the first read command is the only read command or write command in the command queue 220 (see FIG. 2). At step 530, in response to the second read command appearing in the command queue, the second read command is processed by executing the sequence of microinstructions. At step 540, a block/page read address check microinstruction according to the present invention is executed and it is determined whether the block address and page address of the second read command are the same as the block address and page address of the previous read/write command (in this case, the first read command).

If the block address and the page address of the second read command are the same as the block address and the page address of the first read command, respectively, it means that the data required by the second read command has been transferred to the buffer by executing the first read command, and in step 550, the data required by the second read command is obtained from the buffer by executing the corresponding micro-command. In a further example, the processing of the first read command is not yet completed, the processing of the second read command is temporarily suspended, and it is arranged to resume the processing of the second read command after retrieving data from the first read command, and to retrieve data required for the second read command from the buffer.

If the block address and the page address of the second read command are different from the block address and the page address of the first read command, which means that the data required by the second read command has a very low probability of being in the cache, the NVM read command is issued to the NVM by executing the microinstruction in step 560. At step 570, the data read from the NVM is retrieved by executing the micro-instructions and written to the cache.

The details are described by the following specific examples:

example 4

In embodiment 4 according to the present invention, the first preceding user command in the command queue 220 (see fig. 2) is a write command, and the second following user command is a read command. The first user command and the second user command access the same parallel unit and carry the same block address and page address. In response to the unprocessed first user command appearing in the command queue 220, the data to be written by the first user command is carried into the cache by executing the micro instruction sequence and an NVM programming command is issued to the NVM via the interface controller 230 (see FIG. 2). In response to the presence of an unprocessed second user command in the command queue 220, execution of the block/page read address check microinstruction according to the present invention by the microinstruction execution unit 210 (see FIG. 2) determines that the block address and the page address, respectively, accessed by the first user command and the second user command are the same. Accordingly, the data required by the second user command is judged to be in the cache, and the data is obtained from the cache by executing the micro-instruction.

Example 5

In embodiment 5 according to the present invention, the first preceding user command in the command queue 220 (see fig. 2) is a write command, and the second following user command is a read command. The first user command and the second user command access the same parallel unit and carry the same block address and page address. A first user command is to write a full page of data and a second user command is to read out portions of the page of data. The portion of the page data to be read out is indicated by the address range carried in the second user command. In response to the unprocessed first user command appearing in the command queue 220, the entire page of data to be written by the first user command is moved into the cache by executing the micro instruction sequence and an NVM programming command is issued to the NVM via the interface controller 230 (see FIG. 2). In response to the presence of an unprocessed second user command in the command queue 220, execution of the block/page read address check microinstruction according to the present invention by the microinstruction execution unit 210 (see FIG. 2) determines that the block address and the page address, respectively, accessed by the first user command and the second user command are the same. And judging that the data required by the second user command exists in the cache according to the first user command, and acquiring required partial page data from the cache by executing the micro instruction.

Example 6

In embodiment 6 according to the present invention, the first user command preceding in the command queue 220 (see fig. 2) is a read command, the second user command following the first user command is a read ID command, and the third user command following the second user command is a read command. The first user command and the third user command access the same parallel unit and carry the same block address and page address. In response to the unprocessed first user command appearing in the command queue 220, the data to be written by the first user command is carried into the cache by executing the micro instruction sequence and an NVM programming command is issued to the NVM via the interface controller 230 (see FIG. 2). In response to the presence of an unprocessed second user command in command queue 220, an NVM read ID command is issued to the NVM by executing the microinstruction sequence. In response to the presence of an unprocessed third user command in the command queue 220, the block/page read address check microinstruction according to the present invention is executed by the microinstruction execution unit 210 (see fig. 2) to determine that the block address and the page address accessed by the first user command and the second user command are different, and the block/page read address check microinstruction according to the present invention is executed again to determine that the block address and the page address accessed by the first user command and the third user command are respectively the same. Accordingly, the data required by the third user command is judged to be in the cache, and the data is obtained from the cache by executing the micro-instruction.

Example 7

In embodiment 7 according to the present invention, the first user command preceding in the command queue 220 (see fig. 2) is a read command, the second user command following the first user command is a Set Feature command, and the third user command following the second user command is a read command. The first user command and the third user command access the same parallel unit and carry the same block address and page address. In response to the unprocessed first user command appearing in the command queue 220, the data to be written by the first user command is carried into the cache by executing the micro instruction sequence and an NVM programming command is issued to the NVM via the interface controller 230 (see FIG. 2). In response to the presence of an unprocessed second user command in command queue 220, an NVM Set Feature command is issued to the NVM by executing a microinstruction sequence. In response to the presence of an unprocessed third user command in the command queue 220, it is determined by the execution of the microinstruction that the second user command in the command queue will cause the data expected by the third user command to be different from the data read by the first user command, and thus the block/page read address check microinstruction according to the present invention is no longer executed or the check result of the block/page read address check microinstruction is ignored, and an NVM read command is issued to the NVM in accordance with the third user command.

FIG. 6A illustrates a flow diagram of a method of executing a read address check microinstruction in an NVM interface controller according to one embodiment of another aspect of the present invention.

As shown in FIG. 6A, a method of executing a read address check microinstruction in an NVM interface controller comprises: step 610: acquiring a first microinstruction; step 620: decoding the first microinstruction to determine that the first microinstruction is a read address check microinstruction; step 630: acquiring a first block address and a first page address corresponding to a user command; step 640: check if the first block address and the first page address are the same as the stored block address and page address, and if so, proceed to step 650: setting a flag register; if not, go to step 660: the flag register is cleared.

At step 610, the microinstruction execution unit 210 fetches a block/page read address check microinstruction from a specified location in the microinstruction memory 240 (see FIG. 2) according to a Program Counter (PC) in the general purpose register 250. By way of example, a block/page read address check microinstruction is one of the microinstruction sequences used to process read commands. At step 620, the microinstruction execution unit 210 decodes the microinstruction read from the microinstruction memory 240 and determines that the microinstruction is a block/page read address check microinstruction. At step 630, the microinstruction execution unit 210 checks the offset field of the microinstruction (see FIG. 3) according to the block/page read address to access the command queue 220 and obtains therefrom the block address and page address of the first command prior to the current read command. The microinstruction execution unit 210 also retrieves the block address and page address of the current read command from the context memory 260. In step 640, the microinstruction execution unit 210 compares whether the block address and the page address of the first command are the same as the block address and the page address of the current read command, respectively. If so, in step 650, the microinstruction execution unit 210 checks the general register index provided by the Reg field (see FIG. 3) of the microinstruction according to the block/page read address to set the flag register in the general register 250; if not, at step 660, the microinstruction execution unit 210 checks the general register index provided in the Reg field (see FIG. 3) of the microinstruction to clear the flag register in the general register 250 according to the block/page read address.

In the above example, the microinstruction execution unit 210 retrieves the block address and page address of the current read command from the context memory 260.

Optionally, in another embodiment according to the present invention, a second offset value field is provided in the block/page read address check microinstruction to indicate the storage location of the current read command in the command queue 220 (see FIG. 2). And the microinstruction execution unit 210 retrieves the block address and the page address of the current read command from the command queue 220 according to the second offset field and compares the block address and the page address of the first command indicated by the first offset field.

Still alternatively, in yet another embodiment according to the present invention, the microinstruction execution unit 210 (see FIG. 2) maintains a context identifier for identifying the context of the microinstruction sequence, particularly the location in the context memory 260 (see FIG. 2) where the context of the microinstruction sequence is stored. Thus, a context identifier need not be indicated in each microinstruction. The microinstruction execution unit 210 retrieves the block address and page address of the current read instruction from the context memory 260 according to the context identifier.

Still alternatively, in yet another embodiment according to the present invention, the unprocessed commands in the command queue 220 (see FIG. 2) cause the microinstruction execution unit 210 (see FIG. 2) to execute the microinstruction sequence, providing a context identifier in the command to identify the context of the microinstruction sequence, and in particular the location in the context memory 260 (see FIG. 2) where the context of the microinstruction sequence is stored. And stores the block and page addresses carried in the command in context store 260. When executing the block/page address check microinstructions, the microinstruction execution unit 210 (see FIG. 2) retrieves the block address and page address of the current read instruction from the context memory 260 according to the context identifier.

Still alternatively, in yet another embodiment according to the present invention, the unprocessed commands in the command queue 220 (see FIG. 2) cause the microinstruction execution unit 210 (see FIG. 2) to execute the microinstruction sequence, provide a parallel unit identifier in the command, and use the parallel unit identifier to identify a context of the microinstruction sequence, particularly a storage location of the context of the microinstruction sequence in the context memory 260 (see FIG. 2). Thereby assigning the same context to commands accessing the same parallel unit. And store the block and page addresses carried in the command in context store 260. When executing the block/page address check microinstructions, the microinstruction execution unit 210 retrieves the block address and page address of the current read instruction from the context memory 260 based on the parallel unit identifier.

Still optionally, in yet another embodiment according to the invention, the microinstruction execution unit 210 (see FIG. 2) maintains a thread identifier to identify the thread to which the microinstruction sequence belongs. And stores the context information of the threads in context memory 260 (see fig. 2). And determines the location of the thread context in context memory 260 based on the thread identifier. The microinstruction execution unit 210 retrieves the block address and page address of the current read instruction from the context memory 260 according to the thread identifier.

FIG. 6B illustrates a flowchart of a method of performing a read address check microinstruction and its subsequent operations in an NVM interface controller, according to another embodiment of another aspect of the present invention.

As shown in fig. 6B, after the read address check microinstruction is executed in the NVM interface controller, step 680 is executed to read data from the first cache according to the execution result of the read address check microinstruction; or step 670 is executed: the second data is read from the NVM and written to the first buffer.

In block 680, the block/page read address checks the flag register for a subsequent microinstruction (e.g., branch microinstruction) of the microinstruction, modifies the value of the Program Counter (PC) accordingly based on the flag register being set, such that the microinstruction execution unit fetches the next microinstruction based on the updated value of the Program Counter (PC) and reads the data required by the current read command from the cache by executing the next microinstruction and the subsequent microinstruction sequence. In step 670, a subsequent microinstruction (e.g., branch microinstruction) of the block/page read address check microinstruction checks the flag register, modifies the value of the program counter PC accordingly based on the flag register being cleared, such that the microinstruction execution unit fetches the next microinstruction based on the updated value of the program counter PC, and issues an NVM read command to the NVM by executing the next microinstruction and the subsequent microinstruction sequence to fetch the data read from the NVM and write the data to the cache.

FIG. 7A illustrates a flow diagram of a method for executing a read address check microinstruction in an NVM interface controller according to one embodiment of another aspect of the present invention.

As shown in FIG. 7A, the method for executing a read address check microinstruction in an NVM interface controller includes the step 710: acquiring a first microinstruction; step 720: decoding the first microinstruction to determine that the first microinstruction is a read address check microinstruction; step 730: acquiring a first block address and a first page address corresponding to a user command; step 740: check if the first block address and the first page address are the same as the stored second block address and second page address, and if so, proceed to step 750: setting a program counter to a first address; if not, go to step 760: the program counter is set to the second address.

At step 710, the microinstruction execution unit 210 fetches a first microinstruction from a specified location in the microinstruction memory 240 (see FIG. 2) according to the Program Counter (PC) in the general register 250. At step 720, the microinstruction execution unit 210 decodes the first microinstruction read from the microinstruction memory 240 and determines that the first microinstruction is a block/page read address check microinstruction. At step 730, the microinstruction execution unit 210 checks the offset field of the microinstruction (see FIG. 3) according to the block/page read address to access the command queue 220 and obtains therefrom the block address and page address of the first command prior to the current read command. The microinstruction execution unit 210 also retrieves the block address and page address of the current read command from the context memory 260. At step 740, the microinstruction execution unit 210 compares whether the block address and the page address of the first command are the same as the block address and the page address of the current read command, respectively. If so, at step 750, the microinstruction execution unit 210 sets a Program Counter (PC) in the general register 250 to a first value; if not, the microinstruction execution unit 210 sets the Program Counter (PC) in the general register 250 to the second value in step 760. To this end, the block/page read address checks that the microinstruction execution is complete.

As shown in fig. 7B, after the read address check microinstruction is executed in the NVM interface controller, the step 770 is further executed according to the execution result of the read address check microinstruction: the second microinstruction is fetched from the address indicated by the program counter.

In step 770, the microinstruction execution unit 210 (see fig. 2) fetches the next microinstruction according to the updated value of the program counter PC, and by executing the next microinstruction and the subsequent microinstruction sequence, when the value of the program counter PC is set to the first value in step 750, the microinstruction execution unit reads the data required by the current read command from the cache by executing the next microinstruction and the subsequent microinstruction sequence; when the value of the program counter PC is set to the second value in step 760, the microinstruction execution unit issues an NVM read command to the NVM by executing the next microinstruction and subsequent microinstruction sequences to retrieve the data read from the NVM and write the data to the cache.

In an alternative embodiment, by executing a block/page read address check microinstruction, when the microinstruction execution unit 210 (see FIG. 2) sets the Program Counter (PC) to the first value, the general register index provided by the Reg field (see FIG. 3) of the microinstruction is also checked against the block/page read address to set the flag register in the general register 250; when the microinstruction execution unit 210 sets the Program Counter (PC) to the second value, the general register index provided by the Reg field of the microinstruction (see fig. 3) is also checked against the block/page read address to clear the flag register in general register 250.

An example of an NVM in the present invention is a flash memory. Those skilled in the art will recognize that embodiments of the present invention are also applicable to other types of storage media, such as phase change memory, resistive memory, ferroelectric memory, and the like.

According to an aspect of the present invention, there is also provided a computer program comprising computer program code to, when loaded into a computer system and executed thereon, cause said computer system to perform the method as described above.

According to another aspect of the present invention, there is also provided a program comprising program code which, when loaded into and executed on a storage device, causes the storage device to carry out the method described above.

It will be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, respectively, can be implemented by various means including computer program instructions. These computer program instructions may be loaded onto a general purpose computer, special purpose computer, or other programmable data control apparatus to produce a machine, such that the instructions which execute on the computer or other programmable data control apparatus create means for implementing the functions specified in the flowchart block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data control apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including computer-readable instructions for implementing the function specified in the flowchart block or blocks. The computer program instructions may also be loaded onto a computer or other programmable data control apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks.

Accordingly, blocks of the block diagrams and flowchart illustrations support combinations of means for performing the specified functions, combinations of steps for performing the specified functions and program instruction means for performing the specified functions. It will also be understood that each block of the block diagrams and flowchart illustrations, and combinations of blocks in the block diagrams and flowchart illustrations, can be implemented by special purpose hardware-based computer systems that perform the specified functions or steps, or combinations of special purpose hardware and computer instructions.

At least a portion of the various blocks, operations, and techniques described above may be performed using hardware, by controlling a device to execute firmware instructions, by controlling a device to execute software instructions, or any combination thereof. When implemented using a control device executing firmware and software instructions, the software or firmware instructions may be stored on any computer-readable storage medium, such as a magnetic disk, optical disk or other storage medium, in RAM or ROM or flash memory, a control device, hard disk, optical disk, magnetic disk, or the like. Likewise, the software and firmware instructions may be delivered to a user or a system via any known or desired delivery means including, for example, on a computer readable disk or other portable computer storage mechanism or via a communications medium. Communication media typically embodies computer readable instructions, data structures, sequence modules or other data in a modulated data signal such as a carrier wave or other transport mechanism. By way of example, and not limitation, communication media includes wired media such as a wired network or single-wire connection, and wireless media such as acoustic, radio frequency, infrared and other wireless media. Thus, the software and firmware instructions may be transmitted to a user or a system via a communication channel such as a telephone line, a DSL line, a cable television line, a fiber optic cable, a wireless channel, the Internet, etc. (such software is provided via a portable storage medium and is viewed as being the same or interchangeable). The software or firmware instructions may include machine-readable instructions that, when executed by the control device, cause the control device to perform various actions. When implemented in hardware, the hardware may include one or more discrete components, integrated circuits, Application Specific Integrated Circuits (ASICs), and the like.

It is to be understood that the present invention may be implemented in software, hardware, firmware, or a combination thereof. The hardware may be, for example, a control device, an application specific integrated circuit, a large scale integrated circuit, or the like.

Although the present invention has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the invention, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the invention.

Many modifications and other embodiments of the inventions set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the inventions are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A method of accessing an NVM, comprising:

processing a first user command for indicating reading an NVM by executing a microinstruction sequence, and checking whether a block address and a page address corresponding to the first user command are the same as a block address and a page address corresponding to a second user command according to a block/page read address check microinstruction in the microinstruction sequence, wherein the second user command indicates reading the NVM, and the second user command appears before the first user command;

and if the block address and the page address corresponding to the first user command are the same as the block address and the page address corresponding to the second user command, reading data from a first cache for caching data corresponding to the block address and the page address corresponding to the second user command, and responding to the first user command.

2. The method of claim 1, wherein checking whether a block address and a page address corresponding to the first user command are the same as a block address and a page address corresponding to the second user command according to a block/page read address check microinstruction in the microinstruction sequence comprises:

accessing a user command memory according to an offset value (offset) of the block/page read address check microinstruction, and acquiring a block address and a page address corresponding to a first user command; accessing the context memory to obtain a block address and a page address corresponding to the second user command; and checking whether the block address and the page address corresponding to the first user command are the same as the block address and the page address corresponding to the second user command.

3. The method according to claim 1 or 2, wherein if the block address and the page address corresponding to the first user command are the same as those corresponding to the second user command, a flag register is set; and

and if the block address and the page address corresponding to the first user command are different from the block address and the page address corresponding to the second user command, clearing the flag register.

4. The method of claim 3 wherein the sequence of microinstructions further comprises conditional branch microinstructions that check that a flag register is set or cleared by executing the conditional branch microinstruction and set a value of a program counter; the position of the next microinstruction to be executed is fetched based on the value of the program counter.

5. The method of claim 4, wherein if the flag register is set, skipping execution of a first micro instruction sequence to read data from the first cache; and if the flag register is cleared, skipping to execute the second micro-instruction sequence so as to send out an NVM read command to the NVM.

6. An MVN controller, comprising:

a micro instruction memory for storing a plurality of micro instruction sequences;

the microinstruction execution unit is used for decoding the microinstruction and executing the operation corresponding to the microinstruction;

a program counter for indicating a storage location of the microinstructions in the microinstruction memory;

a general purpose register set, wherein registers in the general purpose register set are accessible by microinstructions in the microinstruction sequence;

a user command storage for storing user commands; and

the context memory is used for storing context information corresponding to the micro-instruction sequence; the micro-instruction execution unit accesses the user command memory, responds to a user command in the user command memory to initiate execution of a micro-instruction sequence, and executes the context memory for the micro-instruction sequence according to the parallel unit to be accessed by the user command to acquire context information corresponding to the micro-instruction sequence.

7. The NVM controller of claim 6, wherein the microinstruction execution unit fetches a first microinstruction from the microinstruction memory based on a program counter,

the microinstruction execution unit decodes the first microinstruction, and when the first microinstruction is a block/page read address check microinstruction, the microinstruction execution unit accesses the user command memory according to an offset value (offset) of the block/page read address check microinstruction to obtain a first block address and a first page address; the microinstruction execution unit accesses the context memory and obtains a second block address and a second page address stored in the context information of the current microinstruction sequence; the micro-instruction execution unit compares a first block address with a second block address, and a first page address with a second page address; if the first block address is the same as the second block address and the first page address is the same as the second page address, the microinstruction execution unit sets a general register indicated by a register index in a general register group according to the register index of the block/page read address check microinstruction; if the first block address is different from the second block address or the first page address is different from the second page address, the microinstruction execution unit clears the general register indicated by the register index in the general register group according to the register index of the read address check microinstruction.

8. The NVM controller of claim 7, wherein the microinstruction execution unit fetches a first microinstruction; decoding the first microinstruction, and determining that the first microinstruction is a read address check microinstruction, wherein the read address check microinstruction comprises a register index and an offset value, the register index is used for indicating a flag register for storing an execution result of the read address check instruction, and the offset value is used for indicating a storage location of a user command; acquiring a first block address and a first page address corresponding to the user command according to the offset value; acquiring a second block address and a second page address according to the context information of the read address check micro-instruction, and setting a flag register according to a register index if the first block address is the same as the second block address and the first page address is the same as the second page address; and clearing the flag register according to the register index if the first block address is different from the second block address or the first page address is different from the second page address.

9. The NVM controller of claim 8,

the microinstruction execution unit compares a first block address with a second block address and a first page address with a second page address, wherein if the first block address is the same as the second block address and the first page address is the same as the second page address, the microinstruction execution unit sets the program counter according to the first address of the read address check microinstruction; if the first block address is different from the second block address or the first page address is different from the second page address, the microinstruction execution unit increments the program counter to the second address.

10. The NVM controller of any of claims 6-9,

the microinstruction execution unit responds to a user command in the user command memory to initiate execution of a microinstruction sequence, executes a first context memory for the microinstruction sequence according to a parallel unit accessed by the user command, and accesses the first context memory to obtain a second block address and a second page address stored in context information of the current microinstruction sequence.