CN114967317A

CN114967317A - Mask plate, manufacturing method, liquid crystal display panel and device

Info

Publication number: CN114967317A
Application number: CN202210702663.2A
Authority: CN
Inventors: 王波; 谢建云; 方业周; 王凤国; 石臻; 苗伟; 蔚国将; 孙静
Original assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Current assignee: BOE Technology Group Co Ltd; Ordos Yuansheng Optoelectronics Co Ltd
Priority date: 2022-06-21
Filing date: 2022-06-21
Publication date: 2022-08-30

Abstract

The embodiment of the invention discloses a mask plate, a manufacturing method, a liquid crystal display panel and a device. In one embodiment, the mask includes: the light transmittance of the mask areas is increased from the center to the edge. In this embodiment, the top surface flatness of the film structure can be improved when the mask plate is used to pattern the film, for example, when the mask plate is used to pattern the spacer material layer of the array substrate to fabricate a plurality of first spacers on the array substrate, the top surface flatness of the first spacers can be improved.

Description

Mask plate, manufacturing method, liquid crystal display panel and device

Technical Field

The invention relates to the technical field of display. More particularly, the invention relates to a mask plate, a manufacturing method, a liquid crystal display panel and a device.

Background

Currently, for example, in a liquid crystal display device of a Virtual Reality (VR) type, a bright point (Zara) defect may occur during display, which may affect a display effect. The cause of such a bright spot phenomenon is unknown and there is no good solution.

Disclosure of Invention

The invention aims to provide a mask plate, a manufacturing method, a liquid crystal display panel and a device, which are used for solving at least one of the problems in the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

a first aspect of the present invention provides a mask, including: the light transmittance of the mask areas is increased from the center to the edge.

Optionally, the transmittance of the masked area increases from 0 to 100% from the center to the edge.

Optionally, the mask plate includes a transparent substrate and a plurality of mask layers stacked on the transparent substrate, and the mask layers are located in the mask region.

Optionally, the masked region includes a plurality of regions from the center to the edge, wherein the length of each region in a first direction in a plane parallel to the transparent substrate is the same, and the light transmittance equal difference of the plurality of regions from the center to the edge increases.

Optionally, the plurality of regions is 5-10 regions.

Optionally, the mask layers include a metal layer and a plurality of metal oxide layers sequentially stacked on the transparent substrate with the center of the mask region as the center, and the area of the metal oxide layers decreases progressively in the direction away from the transparent substrate.

Optionally, the mask layers include a metal layer and a metal oxide layer sequentially stacked on the transparent substrate with the center of the mask region as the center, and the thickness of the metal oxide layer decreases from the center of the mask region to the edge.

Optionally, the metal layer is a chromium layer, and the metal oxide layer is a chromium oxide layer.

Optionally, the thickness of the metal oxide layer is y angstrom, where y is selected from the following:

the light transmittance x for the mask region is equal to 0, 95%]-1014.3x + 1055; or the light transmittance x ∈ [0,100% ] for the mask region]Y-263.5 x ³ +350.08x ² -1124.7x+1060。

Optionally, the mask plate is used for manufacturing a plurality of first spacers on the array substrate, and the distribution of the plurality of mask regions corresponds to the distribution of the plurality of first spacers.

A second aspect of the present invention provides a method for manufacturing a mask provided in the first aspect of the present invention, including:

providing a light-transmitting substrate; and

and forming a plurality of mask areas and a plurality of unmasked areas on the light-transmitting substrate, wherein the light transmittance of the mask areas is increased from the center to the edge.

Optionally, the forming a plurality of mask regions on the transparent substrate includes:

and determining a mask area according to the distribution of the first spacers, and forming a plurality of mask areas in the plurality of mask area areas on the light-transmitting substrate.

Optionally, the forming a plurality of mask regions in the plurality of mask region regions on the transparent substrate includes: and forming a mask layer in a mask area on the light-transmitting substrate, wherein the thickness of the mask layer is gradually reduced from the center to the edge of the mask area.

Optionally, the forming a mask layer in the mask region on the transparent substrate includes:

dividing a plurality of mask area regions of the transparent substrate into M regions from the center to the edge, and marking the M regions from the edge to the center of the mask area regions as 1 st to Mth regions respectively, wherein the length of each region in a first direction in a plane parallel to the transparent substrate is the same; and

and sequentially forming an (M-1) metal oxide layer and a metal layer on the light-transmitting substrate, wherein after the mth metal oxide layer is formed, etching the non-mask region and the ith region of the mask region of the mth metal oxide layer, and after the metal layer is formed, etching the non-mask region and the ith region of the mask region of the metal layer, i belongs to [1, M-1], so as to remove the (M-1) metal oxide layer and the metal layer in the non-mask region and form mask regions in the mask regions, wherein the mask regions comprise the metal oxide layer with the thickness decreasing from the center to the edge of the mask region and the metal layer positioned in the center of the mask region.

sequentially forming (N-1) metal oxide layers and a metal layer on the light-transmitting substrate, wherein the (N-1) metal oxide layers and the metal layer form a mask material layer;

dividing a plurality of mask area regions of the mask material layer into N regions from the center to the edge, and marking the N regions from the center to the edge of the mask area regions as 1 st to Nth regions respectively, wherein the length of each region in a first direction in a plane parallel to the transparent substrate is the same; and

and respectively carrying out etching for 1 time to (N-1) times on the 2 nd to the Nth areas in the plurality of mask area areas of the mask material layer and carrying out etching for (N +1) times on the non-mask area areas of the mask material layer so as to remove the mask material layer in the non-mask area areas and form a plurality of mask areas in the plurality of mask area areas, wherein the mask areas comprise metal oxide layers with gradually reduced thickness from the centers to the edges of the mask areas and metal layers positioned in the centers of the mask areas.

Optionally, before the etching, the method further includes:

forming a plurality of first metal oxide layers with different set thicknesses on a first light-transmitting substrate of a mask plate for testing, wherein the first metal oxide layers with each set thickness are respectively arranged on the first light-transmitting substrate in an array manner;

etching the test spacer formed on the test substrate by using the test mask plate; and

obtaining the average value of the thicknesses of the etched spacers corresponding to the first metal oxide layers with the set thicknesses, and determining the light transmittance corresponding to each set thickness of the first metal oxide layers according to the average value of the thicknesses of the etched spacers to obtain the corresponding relation between the thicknesses of the metal oxide layers and the light transmittance;

when a plurality of metal oxide layers and a metal layer are sequentially formed on the light-transmitting substrate, the thickness of each metal oxide layer in the plurality of metal oxide layers is determined according to the corresponding relation between the thickness of the metal oxide layer and the light transmittance.

The third aspect of the present invention provides a method for manufacturing an array substrate, including:

providing a first substrate;

sequentially forming a driving circuit layer, a planarization layer, pixel electrodes arranged in an array, a passivation layer and a common electrode on the first substrate;

a plurality of first spacers are formed on the common electrode by using the mask plate provided by the first aspect of the invention.

The invention provides a liquid crystal display panel in a fourth aspect, which comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, and is characterized in that the array substrate is manufactured by the method in the third aspect, the color film substrate comprises a second substrate, and a color film layer and a plurality of second spacers which are sequentially stacked on the second substrate, and orthographic projections of the plurality of second spacers on the first substrate correspond to orthographic projections of the plurality of first spacers on the first substrate.

The fifth aspect of the present invention provides a liquid crystal display device comprising the liquid crystal display panel provided by the fourth aspect of the present invention.

Optionally, the liquid crystal display device is a virtual reality liquid crystal display device.

The invention has the following beneficial effects:

the mask plate provided by the invention can improve the top surface flatness of a film layer structure when patterning a film layer, for example, when the mask plate is used for patterning a spacer material layer of an array substrate to manufacture a plurality of first spacers on the array substrate, the top surface flatness of the first spacers can be improved, so that polyimide solution can be prevented from accumulating on the top surface of the first spacers when a first alignment film of polyimide materials such as the array substrate is formed, and therefore, a bright spot caused by friction generated when a second spacer of a color film substrate and the first spacers of the array substrate which is aligned to the top move relatively after the array substrate and the color film substrate are aligned can be avoided, the reliability of a display panel can be improved, and poor display can be avoided.

Drawings

The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.

Fig. 1 shows a schematic view of a first spacer of an array substrate prepared based on an existing mask.

Fig. 2 is a schematic view illustrating the first spacer shown in fig. 1 after a first alignment film is formed.

Fig. 3 shows a schematic diagram of the relative movement of the first and second spacers shown in fig. 2 after aligning the cassette.

Fig. 4 is a schematic diagram illustrating a mask according to an embodiment of the present invention.

Fig. 5 shows a schematic view of an array substrate.

Fig. 6 shows another schematic diagram of a mask provided in an embodiment of the present invention.

Fig. 7 is a schematic diagram illustrating a first spacer of an array substrate prepared on the basis of a mask plate according to an embodiment of the present invention.

Fig. 8 shows another schematic diagram of a mask provided in an embodiment of the present invention.

Fig. 9 is a flowchart illustrating a method for manufacturing a mask according to an embodiment of the present invention.

Fig. 10 is a schematic diagram showing the thickness distribution of the first metal oxide layer on the mask for testing.

Fig. 11 is another schematic thickness distribution diagram of the first metal oxide layer on the mask for testing.

Fig. 12 to 16 are schematic diagrams illustrating stages corresponding to a method for manufacturing a mask according to an embodiment of the present invention.

Fig. 17 to 20 are schematic diagrams illustrating stages corresponding to another method for manufacturing a mask according to an embodiment of the present invention.

Fig. 21 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention.

Fig. 22 is a schematic diagram of a liquid crystal display panel in the liquid crystal display device according to the embodiment of the present invention.

Detailed Description

In order to more clearly illustrate the present invention, the present invention will be further described with reference to the following examples and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.

The terms "on … …", "formed on … …" and "disposed on … …" as used herein may mean that one layer is formed or disposed directly on another layer or that one layer is formed or disposed indirectly on another layer, i.e., there is another layer between the two layers.

It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer, and/or a first portion discussed below could be termed a second component, a second member, a second element, a second region, a second layer, and/or a second portion without departing from the teachings of the present invention.

In the present invention, unless otherwise specified, the term "disposed in the same layer" is used to mean that two layers, components, members, elements or portions can be formed by the same manufacturing process (e.g., patterning process, etc.), and the two layers, components, members, elements or portions are generally formed of the same material, but may be at different heights or have different thicknesses. For example, two or more functional layers are arranged in the same layer, which means that the functional layers arranged in the same layer can be formed by using the same material layer and using the same manufacturing process, so that the manufacturing process of the display substrate can be simplified.

In the present invention, unless otherwise specified, the expression "patterning process" generally includes steps of coating of a photoresist, exposure, development, etching, stripping of the photoresist, and the like. The expression "one-time patterning process" means a process of forming a patterned layer, member, or the like using one mask plate.

For the existing liquid crystal display device such as a Virtual Reality (VR) liquid crystal display device, etc., which has a bright spot (Zara) defect during display, the inventor has observed that such a bright spot defect usually occurs, for example, after a substrate polishing process or after the display device is pressed by a screen during use. Based on the above findings, the inventors further conducted analysis verification, and found that the root cause is that in the existing virtual reality liquid crystal display device, the top surface of the first spacer of the array substrate prepared based on the existing mask plate has a depression, for example, as shown in fig. 1, the existing mask plate includes a light-transmitting substrate 101 having a light transmittance of 100% and a plurality of light-shielding layers 102 having a light transmittance of 0 formed on the light-transmitting substrate 101 and distributed corresponding to the design of the first spacer 111, wherein fig. 1 shows only one light-shielding layer 102, and correspondingly, only one first spacer 111 is also shown. The first spacer 111 is made of a positive photoresist such as an acrylic material, and the first spacer material layer corresponding to the exposure region (region with 100% transmittance) of the mask is completely etched while the first spacer material layer corresponding to the non-exposure region (region with 0 transmittance) is theoretically completely remained, so that a plurality of spaced first spacers 111 are formed on, for example, an array substrate, but it is found through analysis and verification that the top surface of the first spacer 111 formed in this way has a recess, as shown in fig. 1, that is, the top surface of the first spacer 111 formed in this way has a recess with high edges and low middle. Thus, as shown in fig. 2, when a first alignment film 112 (which may be referred to as a PI film) of, for example, a Polyimide (PI) material of the array substrate is formed later, a PI solution may be accumulated in the recess of the top surface of the first spacer 111. As shown in fig. 3, when the second spacer 121 of the color filter substrate and the first spacer 111 of the array substrate facing the top move relatively to each other to generate friction after the array substrate and the color filter substrate are stacked together, for example, under an external force such as a substrate polishing process or a screen is pressed, PI debris 1121 is formed from PI material accumulated in the recess of the top surface of the first spacer 111, the PI debris 1121 is released into the liquid crystal layer, and a bright point (Zara) defect occurs during display, thereby affecting the display effect.

In view of this, the present invention provides the following embodiments.

Example one

An embodiment provides a mask, as shown in fig. 4, the mask includes:

a plurality of masked areas 402 and a plurality of unmasked areas, the transmittance of masked areas 402 increasing from the center to the edge.

In one possible implementation, as shown in fig. 4, the mask plate includes a transparent substrate 401, and a mask region 402 is formed on the transparent substrate 401. It can be understood that, in the illustration shown in fig. 4, the region of the transparent substrate 401 where the masked region 402 is not formed is the unmasked region with a transmittance of 100%, and a plurality of unmasked regions may be arranged at intervals or may be connected.

It should be noted that fig. 4 only shows one mask region 402 for a proportion reason, actually, the mask plate for patterning the film layer to form the film layer structure includes a plurality of mask regions 402, for example, the mask plate is used to manufacture two first spacers 501 on the array substrate including a plurality of pixel electrodes corresponding to a plurality of pixels, the scan lines G and the data lines S as shown in fig. 5, and as shown in fig. 6, the mask plate includes two mask regions 402, and the distribution of the two mask regions 402 corresponds to the design distribution of the plurality of first spacers 501. As further shown in fig. 5 and 6, for the typical Thin Film Transistor (TFT) design between the first spacer and the adjacent effective pixel as shown in fig. 6, the size of the mask region 402 in the first embodiment is smaller than the pixel level size. In addition, in fig. 6, a plurality of unmasked regions are connected.

The mask plate provided by the first embodiment can improve the top surface flatness of the film layer structure when the film layer is patterned. For example, when the mask plate provided in the first embodiment is used to pattern the spacer material layer of the array substrate to fabricate a plurality of first spacers on the array substrate, the top surface flatness of the first spacers can be improved without increasing the number of patterning process steps, as shown in fig. 7, the first spacers 711 formed on the array substrate by using the mask plate including the transparent substrate 401 with 100% transmittance and the mask region 402 with gradually changed transmittance provided in the first embodiment has a flat top surface. Therefore, a polyimide solution can be prevented from being accumulated on the top surface of the first spacer 711 when a first alignment film made of a polyimide material, for example, of the array substrate is formed, so that a bright spot caused by polyimide chips generated by friction generated by relative motion between the second spacer of the color film substrate and the first spacer 711 of the opposite array substrate after the array substrate and the color film substrate are aligned is avoided, the reliability of the display panel can be improved, and poor display is avoided.

In one possible implementation, the transmittance of masked region 402 increases from 0 to 100% from the center to the edge. In order to effectively improve the top surface flatness of the first spacer 711, the light transmittance variation range of the mask area 402 needs to be limited, and through the measurement and verification of the inventor on the top surface recess of the first spacer 111 shown in fig. 1 formed in the existing manner, in combination with the exposure process parameters (such as the distance between the mask plate and the spacer material layer, etc.), the light transmittance of the mask area 402 adopted in the implementation manner is gradually increased from the center to the edge to the variation range gradually increased from 0 to 100%, which is beneficial to preparing the first spacer with high top surface flatness.

In one possible implementation, masked region 402 includes a plurality of regions from the center to the edge, where the length of each region in a first direction in a plane parallel to transparent substrate 401 (i.e., the horizontal plane in fig. 7) is the same, and the light transmittance of the plurality of regions from the center to the edge increases in equal difference. The inventor finds that the top surface depression of the first spacer 111 shown in fig. 1 is a relatively smooth curved surface depression, and therefore, theoretically, it is most favorable for achieving the top surface flatness of the first spacer that the light transmittance of the mask area 402 increases from the center to the edge in a smooth increasing manner, but the light transmittance of the mask area 402 increases from the center to the edge in a smooth increasing manner, which has high requirements on the manufacturing process of the mask area 402, and therefore, the top surface flatness of the first spacer and the manufacturing process of the mask area 402 are comprehensively considered, and the implementation mode adopts a scheme that the light transmittance of the mask area 402 increases in a step-by-step manner from the center to the edge in equally spaced areas. For example, in a general first spacer as shown in fig. 6, which is cylindrical, the masked region 402 has a circular cross section in a plane parallel to the transparent substrate 401, and if N regions from the center to the edge of the masked region 402 are respectively the 1 st region to the nth region, the 1 st region is a circular region with a radius a, the 2 nd region is an annular region with an inner radius a and an outer radius 2a, the 3 rd region is an annular region with an inner radius 2a and an outer radius 3a, and so on.

In one possible implementation manner, as shown in fig. 8, the mask plate includes a transparent substrate 401, and a plurality of mask layers stacked on the transparent substrate 401, where the mask layers are located in the mask region 402.

In one possible implementation manner, as shown in fig. 8, the mask layers include a metal layer 4022 and a plurality of metal oxide layers 4021 sequentially stacked on the transparent substrate 401 with the center of the mask region 402 as the center, and the areas of the metal oxide layers 4021 decrease progressively in the direction away from the transparent substrate 401.

In a possible implementation manner, as shown in fig. 8, the mask layers include a metal layer 4022 and a metal oxide layer 4021 sequentially stacked on the transparent substrate 401 with the center of the mask region 402 as the center, and the thickness of the metal oxide layer 4021 decreases from the center to the edge of the mask region 402.

Further, the metal layer 4022 is a chromium layer, and the metal oxide layer 4021 is a chromium oxide layer. For example, the light transmittance of the metal layer 4022 of the chromium layer is 0, and the light transmittance of the metal oxide layer 4021 of the chromium oxide layer increases with the decrease in thickness, so that the implementation method can realize a scheme that the light transmittance of the mask area 402 is increased in a stepping manner from the center to the edge at equal intervals, and the preparation process of the mask area 402 is simple, the light transmittance of different areas is easy to control, and the light transmittance design of different areas is easy to realize with high precision.

In one possible implementation, the plurality of regions is 5-10 regions. For example, the thickness of the metal oxide layer 4021 in fig. 8 includes 4 step changes, the masked region 402 in fig. 8 includes 5 regions, which are respectively denoted as the 1 st to 5 th regions from the center to the edge, and the thicknesses of the metal oxide layers 4021 in the 1 st to 5 th regions decrease progressively, and it can be seen from fig. 8 that the cross-sectional area of the masked region 402 parallel to the transparent substrate 401 decreases progressively in a direction perpendicular to the surface of the transparent substrate 401 where the masked region 402 is formed and away from the transparent substrate 401. The inventor tests and verifies that in the scheme that the light transmittance of the mask area 402 is increased in a stepping mode from the center to the edge at equal intervals, the mask area 402 is divided into 5-10 areas, and factors such as the top surface flatness of the film layer structure of the first spacer and the preparation process simplicity of the mask area 402 can be well balanced.

In one possible implementation, the inventors verify that the thickness of the chromium oxide layer in different areas of mask region 402 can be selected based on the transmittance of the corresponding area design by:

the thickness of the chromium oxide layer is y angstrom

Wherein, the value mode of y is as follows:

the light transmittance x epsilon [0,95 ] of the mask area％]-1014.3x + 1055; or the light transmittance x ∈ [0,100% ] for the mask region]Of (a), y is-263.5 x ³ +350.08x ² -1124.7x+1060。

Wherein, through experimental verification, in the two formulas, y is-1014.3 x +1055 to [0, 95%]Goodness of fit R of light transmittance interval ² ＝0.9988，y＝-263.5x ³ +350.08x ² -1124.7x +1060 applies to [0,100% ]]Interval of light transmittance, goodness of fit R ² ＝0.9994。

Example two

An embodiment provides a method for manufacturing a mask plate provided in the first embodiment, as shown in fig. 9, including the following steps:

s901, providing a light-transmitting substrate 401; and

s902, forming a plurality of masked regions 402 and a plurality of unmasked regions on the transparent substrate 401, wherein the light transmittance of the masked regions 402 increases from the center to the edge.

In one possible implementation manner, the forming of the plurality of mask regions 402 on the transparent substrate 401 in step S902 includes:

a mask region is determined according to the distribution of the first spacers, and a plurality of mask regions 402 are formed in the plurality of mask regions on the transparent substrate 401.

In one possible implementation, forming a plurality of mask regions 402 on a plurality of mask regions on a transparent substrate 401 includes: a mask layer is formed in a mask region on the transparent substrate 401, and the thickness of the mask layer decreases from the center of the mask region to the edge.

In a possible implementation manner, a first specific manner of forming a mask layer in a mask region on the transparent substrate 401 includes:

sequentially forming an (N-1) metal oxide layer and a metal layer on the light-transmitting substrate, wherein the (N-1) metal oxide layer and the metal layer form a mask material layer;

Therefore, a scheme that the light transmittance of the mask region 402 is increased step by step from the center to the edge of the equally spaced region can be obtained, wherein the formation of the multiple metal oxide layers can facilitate the control of the etching precision in the subsequent multiple etching.

In a possible implementation manner, a second specific manner of forming a mask layer in a mask region on the transparent substrate 401 includes:

In a possible implementation manner, before the etching is performed, the method for manufacturing a mask plate according to the second embodiment includes a step of determining a correspondence between a thickness of the metal oxide layer and a light transmittance, which is specifically as follows:

when a plurality of metal oxide layers and a metal layer are sequentially formed on the transparent substrate 401, the thickness of each metal oxide layer in the plurality of metal oxide layers is determined according to the corresponding relationship between the thickness of the metal oxide layer and the light transmittance.

Thus, when the corresponding relation between the thickness of the metal oxide layer and the light transmittance is obtained, the metal oxide layer with the corresponding thickness can be formed in each area according to the designed light transmittance when the mask plate is prepared. Because the mask plate for testing is influenced by gravity, the distances between different positions from the edge to the center and the spacer for testing can be different, and therefore, in order to eliminate errors possibly caused by the difference, the first metal oxide layers with each set thickness are respectively arranged on the first light-transmitting substrate in an array mode, and the thickness average value of the spacer after etching is taken, so that the accuracy is improved.

In one embodiment, the metal oxide is chromium oxide, the spacer is a positive photoresist made of acrylic material, and the different set thicknesses include a thickness H with equal spacing ₁ -H _M For example, the thickness distribution of the first metal oxide layer on the mask for testing may be as shown in fig. 10 or fig. 11, and the obtained thickness of the chromium oxide layer corresponds to the transmittanceThe relationship is shown in Table 1, for example.

TABLE 1

According to table 1, the following selection manner of the thickness of the chromium oxide layer in different areas of the mask area 402 can be obtained:

selecting the light transmittance based on the corresponding area design by the following method:

the chromium oxide layer has a thickness of y angstroms

Wherein, the value mode of y is as follows:

the transmittance x ∈ [0, 95% for masked area 402]-1014.3x + 1055; alternatively, the transmittance x ∈ [0,100% for masked area 402]Y-263.5 x ³ +350.08x ² -1124.7x+1060。

Wherein, through experimental verification, in the two formulas, y is-1014.3 x +1055 to [0, 95%]Goodness of fit R of light transmittance interval ² ＝0.9988，y＝-263.5x ³ +350.08x ² -1124.7x +1060 applies to [0,100%]In the light transmittance interval, the goodness of fit R2 was 0.9994.

Furthermore, it can be seen from Table 1 that the thickness of the chromium oxide layer is y angstroms

The relationship to the average z micrometer (μm) of the test spacer thickness after etching is: and y is 500 z.

Continuing with the foregoing example, taking a mask region as an example, for example, the metal oxide is chromium oxide, the metal layer is chromium, the mask region of the mask material layer is divided into 5 equidistant regions from the center to the edge, which are respectively marked as the 1 st to 5 th regions from the center to the edge of the mask region, and the flow of the first specific manner of forming the mask layer in the mask region on the transparent substrate 401 is, for example:

first, a thickness is formed on a light-transmitting substrate 401 sequentially by, for example, a sputtering coating process

First chromium oxide layer 4031, thickness

Second chromium oxide layer 4032, thickness

Chromium trioxide layer 4033 and thickness

Then, a chromium layer 404 is formed on the fourth chromium oxide layer 4034 by, for example, a sputtering coating process, so as to obtain the structure shown in fig. 12;

then, patterning the chrome layer 404, for example, performing processes such as PR glue coating, PR glue exposure and development, chrome layer 404 etching, PR glue stripping and cleaning, and the like to obtain the structure shown in fig. 13, and forming the 1 st region of the mask region 402 in the mask plate shown in fig. 8;

then, patterning the fourth chromium oxide layer 4034, for example, performing processes such as PR glue coating, PR glue exposure and development, etching the fourth chromium oxide layer 4034, PR glue stripping and cleaning, to obtain the structure shown in fig. 14, and forming the 2 nd region of the mask region 402 in the mask plate shown in fig. 8;

then, patterning the third chromium oxide layer 4033, for example, performing processes such as PR glue coating, PR glue exposure and development, etching the third chromium oxide layer 4033, PR glue stripping and cleaning, and the like to obtain a structure as shown in fig. 15, and forming a 3 rd region of the mask area 402 in the mask plate as shown in fig. 8;

then, patterning the second chromium oxide layer 4032, for example, performing processes such as PR glue coating, PR glue exposure and development, etching the second chromium oxide layer 4032, PR glue stripping and cleaning, and the like to obtain a structure shown in fig. 16, and forming a 4 th region of the mask region 402 in the mask plate shown in fig. 8;

finally, patterning the first chromium oxide layer 4031, for example, performing processes such as PR glue coating, PR glue exposure and development, etching the first chromium oxide layer 4031, PR glue stripping and cleaning, and the like to form a 5 th region of the mask region 402 shown in fig. 8, and performing processes such as size measurement, inspection, repair, protection film encapsulation, and the like to obtain a mask plate which can be delivered from a factory and is shown in fig. 8, wherein light transmittances of 5 equidistant regions of the mask region 402 from the center to the edge are 0, 20%, 40%, 60%, and 80%, respectively.

Continuing with the foregoing example, taking a mask region as an example, for example, the metal oxide is chromium oxide, the metal layer is chromium, the mask region of the mask material layer is divided into 5 equidistant regions from the center to the edge, which are respectively marked as the 1 st to 5 th regions from the edge to the center of the mask region, and the flow of the second specific manner of forming the mask layer in the mask region on the transparent substrate 401 is, for example:

first, a thickness is formed on a light-transmitting substrate 401 by, for example, a sputtering plating process

A first chromium oxide layer of (a);

then, patterning the first chromium oxide layer, for example, performing processes such as coating a PR glue, exposing and developing the PR glue, etching the first chromium oxide layer, stripping and cleaning the PR glue, and the like to obtain an etched first chromium oxide layer 4051, as shown in fig. 17;

then, a thickness is formed on the light-transmitting substrate 401 by, for example, a sputtering plating process

A second chromium oxide layer of (a);

then, patterning the second chromium oxide layer, for example, performing processes such as PR glue coating, PR glue exposure and development, etching the second chromium oxide layer, PR glue stripping and cleaning, and the like, to obtain an etched second chromium oxide layer 4052, as shown in fig. 18;

A third chromium oxide layer of (2);

then, patterning the third chromium oxide layer, for example, performing processes such as PR glue coating, PR glue exposure and development, third chromium oxide layer etching, PR glue stripping and cleaning, and the like, to obtain an etched third chromium oxide layer 4053, as shown in fig. 19;

The fourth chromium oxide layer of (3);

then, patterning the fourth chromium oxide layer, for example, performing processes such as PR glue coating, PR glue exposure and development, etching the fourth chromium oxide layer, PR glue stripping and cleaning, to obtain an etched fourth chromium oxide layer 4054, as shown in fig. 20;

then, a chromium layer is formed on the light-transmitting substrate 401 by, for example, a sputtering plating process;

finally, the chromium layer is patterned, for example, PR glue coating, PR glue exposure and development, chromium layer etching, PR glue stripping and cleaning, and other processes are performed to obtain the etched chromium layer, 5 regions of the mask region 402 shown in fig. 8 are formed, and then the mask plate which can be delivered from the factory and is shown in fig. 8 is obtained through processes of size measurement, inspection, repair, protection film encapsulation, and the like, wherein the light transmittance of 5 equidistant regions from the center to the edge of the mask region 402 of the mask plate is respectively 0, 20%, 40%, 60%, and 80%.

EXAMPLE III

An embodiment three provides a method for manufacturing an array substrate using the mask plate provided in the embodiment one, and as shown in fig. 21, the method includes the following steps:

s1701, providing a first substrate;

s1702, sequentially forming a driving circuit layer, a planarization layer, pixel electrodes arranged in an array, a passivation layer and a common electrode on the first substrate;

and S1703, forming a plurality of first spacers on the common electrode by using the mask plate.

In one specific example, in step S1703, for example, a first spacer material layer of a positive photoresist such as an acrylic material is formed on the common electrode by a coating process, and then the first spacer material layer is patterned by using a mask plate provided in the first embodiment, in which the transmittance of the mask region 402 increases from the center to the edge, so as to obtain a plurality of first spacers. In the method for manufacturing an array substrate according to the third embodiment, the flatness of the top surface of the first spacer can be improved without increasing the number of patterning process steps.

Example four

The fourth embodiment provides a liquid crystal display device, which mainly comprises a frame, a cover plate glass, a liquid crystal display panel, a backlight module, a circuit board and other electronic accessories.

For example, the longitudinal section of the frame is U-shaped, the liquid crystal display panel, the backlight module, the circuit board and other electronic components are disposed in the frame, the backlight module is disposed under the liquid crystal display panel, the circuit board is disposed under the backlight module, and the cover glass is disposed on a side of the liquid crystal display panel away from the backlight module.

Illustratively, the backlight module comprises a light source, a light guide plate and an optical film arranged on the light-emitting side of the light guide plate. In the fourth embodiment, the optical film may include a diffusion sheet, a brightness enhancement film, or the like. The Brightness Enhancement Film may include a prism Film (BEF), a reflection type polarization Brightness Enhancement Film (DBEF), and the like, and both of them may be used in combination. The light guide plate may be wedge-shaped or flat. The light source can be disposed on a side surface of the light guide plate, in which case the backlight module is a side-in type backlight module. In addition, the light source may also be disposed on a side of the light guide plate away from the light exit side, in which case the backlight module is a direct type backlight module. The Light source may be, for example, a Light-Emitting Diode (LED). Under the condition that the backlight module is a direct type backlight module, the lamp panel can be manufactured by adopting the array-type arranged tiny blue light LEDs, and the light emitting direction of the lamp panel faces to the liquid crystal display panel. The backlight module can also comprise a reflector plate, and the reflector plate is arranged on one side of the light guide plate far away from the light emergent side.

The liquid crystal display panel comprises an array substrate, a color film substrate and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate is manufactured by the method provided by the third embodiment, the array substrate comprises a first substrate, and a driving circuit layer, a planarization layer, pixel electrodes arranged in an array manner, a passivation layer, a common electrode and a plurality of first spacers which are sequentially stacked on the first substrate, the color film substrate comprises a second substrate, and a color film layer and a plurality of second spacers which are sequentially stacked on the second substrate, orthographic projections of the plurality of second spacers on the first substrate correspond to orthographic projections of the plurality of first spacers on the first substrate, and the first spacers and the second spacers play a role of enabling the liquid crystal display panel to keep a certain Cell thickness (Cell Gap) when the liquid crystal display panel is pressed by external force, and the first spacer and the second spacer both have elastic recovery rates, so that poor pressing can be improved, and the defects of Mura and black and white spots caused by fracturing of passivation layers and other films possibly caused by stress due to the fact that the second spacer is arranged on the color film substrate are avoided.

In one specific example, the liquid crystal display panel divides a display area (also referred to as an AA area) and a peripheral area. The display region is provided with a plurality of pixels, which are red pixels (R), green pixels (G), and blue pixels (B), respectively. Illustratively, along the extending direction (horizontal direction) of the scanning line G, the red pixel, the green pixel, and the blue pixel are arranged periodically; along the extending direction (vertical direction) of the data line S, the red, green, and blue pixels are arranged in columns, respectively.

In a specific example, the array substrate and the color film substrate are adhered together by frame sealing glue, so that the liquid crystal layer is limited in an area surrounded by the frame sealing glue.

As shown in fig. 22, the color filter substrate includes a second substrate 1821, and a color filter layer 1822 and a plurality of second spacers 1823 sequentially stacked on the second substrate 1821, wherein the color filter layer 1822 includes a red photoresist unit facing the red pixel, a green photoresist unit facing the green pixel, and a blue photoresist unit facing the blue pixel. Illustratively, the red, green and blue photoresist units are periodically arranged along the extension direction (horizontal direction) of the scanning line G, and the red, green and blue photoresist units are arranged in rows and columns along the extension direction (vertical direction) of the data line S.

On this basis, as shown in fig. 22, in order to avoid mutual crosstalk between lights emitted from adjacent pixels, the color film layer 1822 may further include a Black Matrix pattern (BM) for spacing the red, green, and blue light blocking units. In the case that the color film layer 1822 includes a red photoresist unit, a green photoresist unit, a blue photoresist unit, and a black matrix pattern, the second spacer 1823 is disposed opposite to the black matrix pattern.

The process of forming the color filter substrate may be, for example: a color film layer 1822 is formed on a second substrate 1821, and a plurality of second spacers 1823 are formed thereon. In some embodiments, the process of manufacturing the color filter substrate further includes: a second alignment film (not shown) is formed on the exposed portion of the color film layer 1822, wherein the second alignment film is formed by, for example, first coating a Polyimide (PI) solution, and then curing to form a second alignment film of a polyimide material, since the second spacer 1823 is convex, the PI solution will flow down along the sidewall, and the second alignment film will not be formed on the second spacer 1823, even if there is a residual solution on the top surface or the side surface, the residual solution is only a thin layer, which can be ignored.

As shown in fig. 22, in the array substrate, the front film layer structure of the first spacer 1811 includes, for example, a driving circuit layer, a planarization layer, pixel electrodes arranged in an array, a passivation layer, and a common electrode, which are sequentially disposed on the first substrate 1812 from bottom to top. The front film layer structure of the first spacer 1811 may refer to a film layer structure on the first substrate 1812 before the first spacer 1811 is formed, which may be different according to circumstances. For example, as shown in fig. 22, the front film structure of the first spacer 1811 includes a Light Shield (LS) 1813 layer, a buffer layer (buffer)1814, an active layer 1815 such as a polysilicon (P-SI), a Gate Insulator (GI) 1816, a Gate 1817, an inter-layer Dielectric (ILD) 1818, a source 1819 and a drain 1820, a Planarization Layer (PLN)1821, a Pixel electrode (PITO, Pixel Oxide)1822, a passivation layer (PVX)1823 covering the Pixel electrode 1822, and a Common electrode (CITO, Common Oxide)1824, which are sequentially disposed from bottom to top on the first substrate 1812.

In each pixel region, a pixel electrode 1822 and a Thin Film Transistor (TFT) of a driving circuit layer are disposed. The thin film transistor may be a top gate thin film transistor as shown in fig. 22, a bottom gate thin film transistor, or a double gate thin film transistor. The thin film transistor shown in fig. 22 includes an active layer 1815, a gate insulating layer 1816, a gate electrode 1817, an interlayer dielectric layer 1818, a source electrode 1819, and a drain electrode 1820 disposed on a first substrate 1812. The array substrate further comprises a scanning line G and a data line S, a grid electrode 1817 of the thin film transistor is electrically connected with the scanning line G, and a source electrode 1819 of the thin film transistor is electrically connected with the data line S.

The material of the gate insulating layer 1816 and the interlayer dielectric layer 1818 may be, for example, one or more of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy).

For example, the interlayer dielectric layer 1818 includes a first interlayer dielectric layer and a second interlayer dielectric layer which are stacked, and a material of the first interlayer dielectric layer is different from a material of the second interlayer dielectric layer. Illustratively, the material of the first inter-sub-layer dielectric layer is silicon oxide, and the material of the second inter-sub-layer dielectric layer is silicon oxide.

As shown in fig. 22, the planarization layer 1821 has vias; the pixel electrode 1822 is recessed at the via hole to form a recess, and the pixel electrode 1822 is electrically connected to the drain 1820 of the thin film transistor through the via hole on the planarization layer 1821.

Here, the pixel electrode 1822 and the common electrode 1824 may be made of Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), for example.

As shown in fig. 22, a first spacer 1811 using a positive photoresist such as an acryl material is disposed at a position corresponding to the recess of the pixel electrode 1822. For example, the first spacers 1811 may be formed by coating a photoresist layer, performing a mask exposure process, performing a developing process, and the like using the mask provided in the first embodiment. Thus, the formed first spacer 1811 has a high top surface flatness, and when, for example, a Polyimide (PI) solution is coated first and then cured to form the first alignment film 1825 of a polyimide material, the Polyimide (PI) solution does not accumulate on the top surface of the first spacer 1811 but flows down along the side walls, and the first alignment film is not formed on the first spacer 1811.

It should be understood that the orthographic projection of the first spacer 1811 and the corresponding second spacer 1823 on the black matrix pattern of the color filter substrate is located within the boundary of the black matrix pattern.

In addition, the liquid crystal display panel can also comprise an upper polarizer arranged on one side of the color film substrate far away from the liquid crystal layer and a lower polarizer arranged on one side of the array substrate far away from the liquid crystal layer, wherein the light transmission axes of the upper polarizer and the lower polarizer are mutually vertical or parallel.

In one possible implementation, the liquid crystal display device in the fourth embodiment is a Virtual Reality (VR) liquid crystal display device. In addition, the liquid crystal display device in the fourth embodiment is not limited to the VR liquid crystal display device, and can be applied to various display products having a design in which the first spacer is provided on the array substrate, for example, liquid crystal display devices of MNT (display), TV (television), LTPO (low temperature poly-silicon and oxide integration technology), LTPA (low temperature poly-silicon and amorphous silicon integration technology), and the like.

It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations and modifications can be made on the basis of the above description, and all embodiments cannot be exhaustive, and all obvious variations and modifications belonging to the technical scheme of the present invention are within the protection scope of the present invention.

Claims

1. The mask plate is characterized by comprising a plurality of mask areas and a plurality of non-mask areas, wherein the light transmittance of the mask areas is increased from the center to the edge.

2. A mask according to claim 1, wherein the transmittance of the mask region increases from 0 to 100% from the center to the edge.

3. A mask according to claim 1 or 2, wherein the mask comprises a transparent substrate and a plurality of mask layers stacked on the transparent substrate, and the mask layers are located in the mask region.

4. A mask according to claim 3, wherein the mask region comprises a plurality of regions from the center to the edge, wherein the length of each region in a first direction in a plane parallel to the light-transmitting substrate is the same, and the light transmittance of the plurality of regions from the center to the edge is gradually increased.

5. A mask according to claim 4, wherein the plurality of regions is 5-10 regions.

6. A mask according to claim 3, wherein the mask layers include a metal layer and a plurality of metal oxide layers sequentially stacked on the transparent substrate with a center of a mask region as a center, and an area of the metal oxide layer decreases in a direction away from the transparent substrate.

7. A mask according to claim 3, wherein the mask layers comprise a metal layer and a metal oxide layer which are sequentially stacked on the transparent substrate with the center of the mask region as the center, and the thickness of the metal oxide layer decreases from the center of the mask region to the edge.

8. A mask according to claim 6 or 7, wherein the metal layer is a chromium layer and the metal oxide layer is a chromium oxide layer.

9. A mask according to claim 8 wherein the thickness of the metal oxide layer is y angstroms, wherein y is chosen in the following manner:

the light transmittance x for the mask region is equal to 0, 95%]-1014.3x + 1055; or the light transmittance x ∈ [0,100% ] for the mask region]Of (a), y is-263.5 x ³ +350.08x ² -1124.7x+1060。

10. A mask plate according to claim 1, wherein the mask plate is used for manufacturing a plurality of first spacers on an array substrate, and the distribution of the plurality of mask regions corresponds to the distribution of the plurality of first spacers.

11. A method of manufacturing a mask according to any one of claims 1 to 10, comprising:

providing a light-transmitting substrate; and

and forming a plurality of masked areas and a plurality of unmasked areas on the light-transmitting substrate, wherein the light transmittance of the masked areas is increased from the center to the edge.

12. The method of claim 11, wherein forming a plurality of masked regions on the transparent substrate comprises:

13. The method of claim 12, wherein forming masked regions on the transparent substrate in masked region areas comprises: and forming a mask layer in the mask area on the light-transmitting substrate, wherein the thickness of the mask layer is gradually reduced from the center of the mask area to the edge.

14. The method of claim 13, wherein forming a masking layer over the masked area on the transparent substrate comprises:

15. The method of claim 13, wherein forming a masking layer over the masked area on the transparent substrate comprises:

16. The method of claim 14 or 15, wherein prior to performing the etching, the method further comprises:

17. A method for manufacturing an array substrate comprises the following steps:

providing a first substrate;

forming a plurality of first spacers on the common electrode using a mask as claimed in any one of claims 1 to 10.

18. A liquid crystal display panel, characterized by comprising an array substrate, a color film substrate, and a liquid crystal layer disposed between the array substrate and the color film substrate, wherein the array substrate is manufactured by the method of claim 17, the color film substrate comprises a second substrate, and a color film layer and a plurality of second spacers sequentially stacked on the second substrate, and orthographic projections of the plurality of second spacers on the first substrate correspond to orthographic projections of the plurality of first spacers on the first substrate.

19. A liquid crystal display device comprising the liquid crystal display panel according to claim 18.

20. The liquid crystal display device according to claim 19, wherein the liquid crystal display device is a virtual reality liquid crystal display device.