CN114945117B - Error code tester reset signal time sequence determining method and related components - Google Patents

Error code tester reset signal time sequence determining method and related components Download PDF

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Publication number
CN114945117B
CN114945117B CN202210884385.7A CN202210884385A CN114945117B CN 114945117 B CN114945117 B CN 114945117B CN 202210884385 A CN202210884385 A CN 202210884385A CN 114945117 B CN114945117 B CN 114945117B
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transmission delay
time
determining
tester
reset signal
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CN114945117A (en
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彭兴贵
廉哲
胡海洋
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Suzhou Lianxun Instrument Co ltd
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Stelight Instrument Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/07—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems
    • H04B10/075—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal
    • H04B10/077—Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
    • H04B10/0775—Performance monitoring and measurement of transmission parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q2011/0079—Operation or maintenance aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0062—Network aspects
    • H04Q2011/0079—Operation or maintenance aspects
    • H04Q2011/0083—Testing; Monitoring

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Dc Digital Transmission (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

The invention discloses a method for determining the timing sequence of a reset signal of an error code tester and a related component, and relates to the field of communication testing.

Description

Error code tester reset signal time sequence determining method and related components
Technical Field
The invention relates to the field of communication test, in particular to a method for determining the timing sequence of a reset signal of an error code tester and a related component.
Background
In a high-speed optical communication system, bit errors are caused by channel non-ideality and noise interference, so that errors occur when a receiving end judges code elements, and the quality of transmitted information is damaged. An error code tester is a basic instrument for evaluating the transmission performance of an optical communication system. When the error code tester is used for testing a to-be-tested Optical communication system, a code transmitter in the error code tester sends a test signal, the test signal is coded and sent to an input end of an Optical Network Unit (ONU) in the to-be-tested Optical communication system, the ONU converts the test signal from an electrical signal into an Optical signal and sends the Optical signal to an Optical Line Terminal (OLT) in the to-be-tested Optical communication system, and the OLT converts the test signal from the Optical signal into an electrical signal and sends the electrical signal to a synchronizer in the error code tester. The synchronizer carries out clock synchronization on the test signal and then sends the test signal to the code receiving device, the code receiving device generates the test signal which is the same as the test signal sent by the code sending device, the synchronous signal is compared with the received test signal, if the two signals are inconsistent, the error code is generated, the error code tester counts the bit number of the error code, and then records, stores, analyzes and displays the test result.
The OLT consists of an optical detector, a trans-impedance amplifier and a limiting amplifier. Because a DC BLOCK capacitor exists between the trans-impedance amplifier and the limiting amplifier, a discontinuous test signal passes through the OLT to generate baseline offset, so that the limiting amplifier cannot identify the next test signal. It is therefore necessary to use the error tester to send a reset signal to the OLT to eliminate the baseline shift due to the transmission of a discontinuous test signal. The issuance of the reset signal is timing dependent and typically requires that the reset occur near the preamble of the test signal. Referring to fig. 2, fig. 2 is a schematic timing relationship diagram of a test signal and a reset signal. In the prior art, the sending time of the reset is adjusted in a manual adjusting mode, and the sending time of the reset is adjusted to be the correct time, so that the reset signal appears near a lead code of a test signal.
Disclosure of Invention
The invention aims to provide a method for determining the time sequence of a reset signal of an error code tester and a related component, which can automatically determine the sending time of the reset signal without manual adjustment and improve the working efficiency.
In order to solve the above technical problem, the present invention provides a method for determining a timing sequence of a reset signal of an error code tester, comprising:
determining a first time when the OLT receives a lead code of the test signal;
determining a first transmission delay of a reset signal from an error code tester to the OLT;
and subtracting the first transmission delay from the first time to obtain the sending time of the reset signal.
Preferably, the determining a first time when the OLT receives the preamble of the test signal includes:
determining a second moment when a code receiver of the error code tester receives the lead code of the test signal;
determining a second transmission delay of the test signal from the synchronizer of the error code tester to the code receiver of the error code tester;
and subtracting the first transmission delay and the second transmission delay from the second time to obtain the first time.
Preferably, the determining a second time when the code receiver of the error code tester receives the preamble of the test signal includes:
determining a third moment when a code sender of the error code tester sends the test signal;
determining a third propagation delay from the transmission of the test signal by the code sender to the reception of the test signal by the code receiver;
and adding the third transmission delay to the third time to obtain the second time.
Preferably, before the first time is obtained by subtracting the first transmission delay and the second transmission delay from the second time, the method further includes:
determining a fourth transmission delay of a preamble of the test signal from the OLT to a synchronizer of the error tester;
subtracting the first transmission delay and the second transmission delay from the second time to obtain the first time, including:
and subtracting the fourth transmission delay and the second transmission delay from the second time to obtain the first time.
Preferably, the determining a first transmission delay of the reset signal sent from the error tester to the OLT includes:
determining the length of a radio frequency cable between the error code tester and the OLT;
determining the transmission delay of the reset signal in the transmission unit length on the radio frequency cable;
and multiplying the length by the transmission delay of the unit length to obtain the first transmission delay.
The invention also provides a system for determining the time sequence of the reset signal of the error code tester, which comprises the following components:
a first time determination unit, configured to determine a first time at which the OLT receives a preamble of the test signal;
a first transmission delay determining unit, configured to determine a first transmission delay of a reset signal sent from an error code tester to the OLT;
and the reset signal sending time determining unit is used for subtracting the first transmission delay from the first time to obtain the sending time of the reset signal.
The invention also provides a device for determining the time sequence of the reset signal of the error code tester, which comprises:
a memory for storing a computer program;
and the processor is used for realizing the steps of the method for determining the time sequence of the reset signal of the error code tester when executing the computer program.
The invention also provides an error code tester, which comprises an error code tester body and the error code tester reset signal time sequence determining equipment.
The invention also provides a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the above method for determining the timing sequence of the reset signal of an error code tester.
After the first time when the OLT receives the lead code of the test signal is determined, in order to enable the reset signal to be near the lead code of the test signal, the OLT needs to receive the lead code of the test signal while receiving the reset signal sent by the error code tester, therefore, the first transmission delay of the reset signal sent from the error code tester to the OLT needs to be determined, the reset signal is sent at the time when the first transmission delay is subtracted from the first time, the OLT can simultaneously receive the reset signal and the lead code of the test signal at the first time, the time sequence requirement on the reset signal is met, the automatic determination of the sending time of the reset signal is realized, manual adjustment is not needed, and the working efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a method for determining a timing sequence of a reset signal of an error code tester according to the present invention;
FIG. 2 is a timing relationship diagram of a test signal and a reset signal;
FIG. 3 is a schematic view of a scenario for testing a system under test using an error code tester;
FIG. 4 is a schematic diagram of a hardware structure for testing a system under test by using an error code tester;
fig. 5 is a schematic structural diagram of a system for determining a timing sequence of a reset signal of an error code tester according to the present invention;
fig. 6 is a schematic structural diagram of an error code tester reset signal timing sequence determining device provided in the present invention.
Detailed Description
The core of the invention is to provide a method for determining the timing sequence of the reset signal of the error code tester and a related component, which realizes the automatic determination of the sending time of the reset signal, does not need manual adjustment and improves the working efficiency.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a method for determining a timing sequence of a reset signal of an error code tester according to the present invention.
A method for determining the time sequence of a reset signal of an error code tester comprises the following steps:
s1: determining a first time when the OLT receives a lead code of the test signal;
in order to eliminate the baseline offset generated by the limiting amplifier in the OLT, the reset signal needs to be present near the preamble of the test signal, and specifically, when the OLT receives the preamble of the test signal, the OLT also receives the reset signal sent by the error tester. Therefore, it is necessary to determine the first time instant at which the OLT receives the preamble of the test signal. When the first time is determined, in the prior art, an oscilloscope is usually additionally connected to an error code tester, then the waveform of the oscilloscope is observed and adjusted manually, and finally the first time is calculated by using the experience of a worker. Based on this, considering that for a fixed test system, the delay of the transmission of the test signal between the parts in the test system is fixed, the recording time can be started at the same time as the sending time of the test signal, the recording time is stopped when the OLT receives the test signal, a preliminary first time is obtained based on this, and then the internal delay caused by the hardware structure, such as the delay caused by the length of the reset cable, is subtracted, and since these delay times can be calculated, the accurate first time can be obtained. In addition, the function of recording time can be realized by a timer inside the error code tester.
S2: determining a first transmission delay of a reset signal sent from an error code tester to an OLT;
considering that a certain transmission delay, i.e., a first transmission delay, is required in a process of sending a reset signal from an error code tester to an OLT through a radio frequency cable, and the first transmission delays of different systems to be tested and different cable lengths are different, the first transmission delay needs to be determined according to specific conditions of the systems to be tested, such as the cable length between the OLT and the error code tester, the transmission speed of the reset signal on the cable, and the like. The reset signal may be, but is not limited to, a pulse signal, and the present application does not limit this.
S3: and subtracting the first transmission delay from the first time to obtain the sending time of the reset signal.
In order to enable the OLT to receive the reset signal when receiving the preamble of the test signal, in this embodiment, the sending time of the error code tester sending the reset signal is a first time, for example, the first time of the OLT receiving the preamble of the test signal is t, the first transmission delay is 10s, and the time of the error code tester sending the reset signal is t-10s. The OLT can receive the lead code of the test signal at the time t and simultaneously receive the reset signal sent by the error code tester.
In summary, in this embodiment, after determining the first time when the OLT receives the preamble of the test signal, in order to enable the reset signal to appear near the preamble of the test signal, the OLT needs to receive the preamble of the test signal while receiving the reset signal sent by the error tester, and therefore needs to determine the first transmission delay for sending the reset signal from the error tester to the OLT, and send the reset signal at the time when the first transmission delay is subtracted from the first time, so that the OLT can receive the reset signal and the preamble of the test signal at the same time at the first time, thereby satisfying the timing requirement for the reset signal, and implementing automatic determination of the sending time of the reset signal, without manual adjustment, and improving the working efficiency.
On the basis of the above-described embodiment:
as a preferred embodiment, determining a first time when the OLT receives the preamble of the test signal includes:
determining a second moment when a code receiving device of the error code tester receives the lead code of the test signal;
determining a second transmission delay of the test signal from the synchronizer of the error code tester to the code receiver of the error code tester;
and subtracting the first transmission delay and the second transmission delay from the second time to obtain the first time.
Considering that the type of the error code tester is determined, the second transmission delay of the test signal sent from the synchronizer of the error code tester to the code receiver of the error code tester is determined, so the second transmission delay can be determined according to the specific type of the error code tester. For a fixed system under test, the delay of the test signal transmission between the various parts of the test system is fixed. Therefore, after the system to be tested is determined, as long as the error code tester sends out the test signal, the receiving device of the error code tester is calculated according to the sending time of the test signal and the transmission delay required by the transmission of the test signal in the system to be testedA second time instant at which the preamble of the test signal is received. Assuming that the first time when the OLT receives the lead code of the test signal is T, the first transmission delay of the reset signal sent from the error code tester to the OLT is T 1 The second transmission delay of the test signal from the synchronizer of the error code tester to the code receiver of the error code tester is T 2 If the code receiver of the error code tester receives the lead code of the test signal, the second time t 2 =t+T 1 +T 2 From this, the first time t = t 2 -T 1 -T 2 I.e. the first time equals the second time minus the first transmission delay and the second transmission delay.
As a preferred embodiment, determining a second time when the code receiver of the error tester receives the preamble of the test signal includes:
determining a third moment when a code sender of the error code tester sends a test signal;
determining a third transmission delay of the test signal from the code transmitter to the code receiver;
and adding the third transmission delay to the third time to obtain a second time.
For a fixed system to be tested, the third transmission delay from sending to receiving of the test signal sent by the error code tester is determined, so that the second time when the code receiver of the error code tester receives the lead code of the test signal can be determined after the third time when the code transmitter of the error code tester sends the test signal and the third transmission delay from sending the test signal by the code transmitter to receiving the test signal by the code receiver of the error code tester are determined. The third moment of sending the test signal can be obtained by a timer in the error code tester, and the third transmission delay can be determined according to the length of a transmission cable in the system to be tested and the speed of the test signal passing through the transmission cable. The third transmission delay here may be, but is not limited to, 4ns.
Referring to fig. 3 and 4, fig. 3 is a schematic view of a scenario in which an error code tester is used to test a system under test, and fig. 4 is a schematic view of a hardware structure in which an error code tester is used to test a system under test.
As a preferred embodiment, before subtracting the first transmission delay and the second transmission delay from the second time to obtain the first time, the method further includes:
determining a fourth transmission delay of a lead code of the test signal from the OLT to a synchronizer of the error code tester;
subtracting the first transmission delay and the second transmission delay from the second time to obtain a first time, including:
and subtracting the fourth transmission delay and the second transmission delay from the second moment to obtain the first moment.
Considering that the first transmission delay is specifically the transmission delay of the reset signal sent from a reset signal generator, such as a pulse signal generator, in the error tester to the OLT, and when the first time is determined by using the second time, the first time is equal to the second time minus the fourth transmission delay of the preamble of the test signal sent from the OLT to the synchronizer of the error tester and minus the transmission delay of the preamble of the test signal sent from the synchronizer of the error tester to the code receiver of the error tester. In the case of no error, the first transmission delay is approximately equal to a fourth transmission delay of the preamble of the test signal sent from the OLT to the synchronizer of the error tester, so that the first time can be obtained by subtracting the first transmission delay and the second transmission delay from the second time. In order to further improve the accuracy of the time sequence of the reset signal, in this embodiment, a fourth transmission delay of the preamble of the test signal sent from the OLT to the synchronizer of the error code tester is also determined, and the first time is obtained by subtracting the fourth transmission delay and the second transmission delay from the second time.
As a preferred embodiment, determining a first transmission delay of the reset signal from the error tester to the OLT includes:
determining the length of a radio frequency cable between the error code tester and the OLT;
determining the transmission delay of the reset signal in the transmission unit length on the radio frequency cable;
the length is multiplied by the transmission delay per unit length to obtain a first transmission delay.
In order to enable the application to be applicable to systems to be tested with different lengths of cables, the first transmission delay of the reset signal sent from the error code tester to the OLT is determined according to different systems to be tested, because the first transmission delay is related to the transmission speed of the cable of the reset signal in the system to be tested, the transmission delay of the reset signal in a unit length on the radio frequency cable needs to be determined because the cables with different materials and different reset signals cause different speeds of the reset signal during transmission, and the longer the length of the cable is, the longer the time for the reset signal to be transmitted back to the error code tester through the system to be tested is, so the length of the radio frequency cable between the error code tester and the OLT needs to be determined. Specifically, the first transmission delay of the reset signal from the error code tester to the OLT can be obtained by multiplying the transmission delay of the transmission unit length of the reset signal on the radio frequency cable by the length of the radio frequency cable between the error code tester and the OLT. The transmission delay of the reset signal in the radio frequency cable per unit length can be, but is not limited to, 3.4ns/m.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a system for determining a timing sequence of a reset signal of an error code tester according to the present invention.
The invention also provides a system for determining the time sequence of the reset signal of the error code tester, which comprises the following components:
a first time determination unit 21 configured to determine a first time at which the OLT receives the preamble of the test signal;
a first transmission delay determining unit 23, configured to determine a first transmission delay for the reset signal to be sent from the error code tester to the OLT;
and a reset signal sending time determining unit 22, configured to subtract the first transmission delay from the first time to obtain a sending time of the reset signal.
For a related introduction of the error code tester reset signal timing determining system, please refer to the above embodiments, which are not described herein again.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an error tester reset signal timing sequence determining apparatus provided in the present invention.
The invention also provides a device for determining the time sequence of the reset signal of the error code tester, which comprises:
a memory 31 for storing a computer program;
the processor 32 is configured to implement the steps of the method for determining the timing of the error tester reset signal as described above when executing the computer program.
For a related introduction of the error tester reset signal timing determining apparatus, please refer to the above embodiments, which are not described herein again.
The invention also provides an error code tester, which comprises an error code tester body and the error code tester reset signal time sequence determining equipment.
For the related description of the error tester, please refer to the above embodiments, which are not described herein again.
The invention also provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the steps of the method for determining the time sequence of the reset signal of the error code tester.
For the related description of the computer-readable storage medium, please refer to the above embodiments, which are not repeated herein.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (6)

1. A method for determining the time sequence of a reset signal of an error code tester is characterized by comprising the following steps:
determining a first moment when the OLT receives a lead code of the test signal;
determining a first transmission delay of a reset signal sent from an error code tester to the OLT;
subtracting the first transmission delay from the first time to obtain the sending time of the reset signal;
determining a first time at which the OLT receives the preamble of the test signal, comprises:
determining a second moment when a code receiving device of the error code tester receives the lead code of the test signal;
determining a second transmission delay of the test signal from the synchronizer of the error code tester to the code receiver of the error code tester;
subtracting the first transmission delay and the second transmission delay from the second time to obtain the first time;
determining a second time when a code receiver of the error code tester receives a preamble of the test signal, including:
determining a third moment when a code sender of the error code tester sends the test signal;
determining a third propagation delay from the transmission of the test signal by the transmitter to the reception of the test signal by the receiver;
adding the third transmission delay to the third time to obtain the second time;
determining a first transmission delay of a reset signal sent from an error tester to the OLT, comprising:
determining the length of a radio frequency cable between the error code tester and the OLT;
determining the transmission delay of the reset signal in the transmission unit length on the radio frequency cable;
and multiplying the length by the transmission delay of the unit length to obtain the first transmission delay.
2. The method for determining the timing of the error code tester reset signal according to claim 1, wherein the step of subtracting the first transmission delay and the second transmission delay from the second time to obtain the first time further comprises:
determining a fourth transmission delay of a preamble of the test signal from the OLT to a synchronizer of the error tester;
subtracting the first transmission delay and the second transmission delay from the second time to obtain the first time, including:
and subtracting the fourth transmission delay and the second transmission delay from the second time to obtain the first time.
3. A system for determining the timing of a reset signal of an error tester, comprising:
a first time determination unit, configured to determine a first time at which the OLT receives a preamble of the test signal;
a first transmission delay determining unit, configured to determine a first transmission delay of a reset signal sent from an error code tester to the OLT;
a reset signal sending time determining unit, configured to subtract the first transmission delay from the first time to obtain a sending time of the reset signal;
the first time determination unit is specifically configured to:
determining a second moment when a code receiver of the error code tester receives the lead code of the test signal;
determining a second transmission delay of the test signal sent from the synchronizer of the error code tester to the code receiver of the error code tester;
subtracting the first transmission delay and the second transmission delay from the second moment to obtain the first moment;
determining a second time when a code receiver of the error code tester receives a preamble of the test signal, including:
determining a third moment when a code transmitter of the error code tester sends the test signal;
determining a third propagation delay from the transmission of the test signal by the transmitter to the reception of the test signal by the receiver;
adding the third transmission delay to the third time to obtain the second time;
the first transmission delay determining unit is specifically configured to:
determining the length of a radio frequency cable between the error code tester and the OLT;
determining the transmission delay of the reset signal in the transmission unit length on the radio frequency cable;
and multiplying the length by the transmission delay of the unit length to obtain the first transmission delay.
4. An error tester reset signal timing determination apparatus, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the method for determining the timing of the error tester reset signal according to claim 1 or 2 when executing said computer program.
5. An error tester comprising an error tester body and an error tester reset signal timing determination device as claimed in claim 4.
6. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the method for error tester reset signal timing determination as claimed in claim 1 or 2.
CN202210884385.7A 2022-07-26 2022-07-26 Error code tester reset signal time sequence determining method and related components Active CN114945117B (en)

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