CN114938346B

CN114938346B - Method and device for realizing service fast switching by cooperation of chip and CPU

Info

Publication number: CN114938346B
Application number: CN202210523456.0A
Authority: CN
Inventors: 周杰; 何志川; 单哲; 王全刚
Original assignee: Suzhou Centec Communications Co Ltd
Current assignee: Suzhou Centec Communications Co Ltd
Priority date: 2022-05-13
Filing date: 2022-05-13
Publication date: 2023-06-06
Anticipated expiration: 2042-05-13
Also published as: CN114938346A

Abstract

The invention discloses a method and a device for realizing service fast switching by cooperation of a chip and a CPU, wherein the method comprises the steps that the chip judges whether an MEP generates an error or judges whether the MEP recovers from the error according to a processing result of a CCM message and an updating result of the MEP, stores the error into an MEP table when the MEP has the error, and clears the error in the MEP table when the MEP recovers from the error; further judging whether to report errors based on the detection report enabling table, and setting the bit positions of the MEPs in the OAM detection table for generating errors as a preset value or the bit positions of the corresponding MEPs recovered from the errors as a preset value when reporting; further scanning each table item in the OAM detection table, and reporting the index of the table item with the preset value to the CPU; and the CPU reads the corresponding table entry according to the index, judges whether an error is generated or recovered from the error, and performs corresponding service protection switching. The invention can improve the protection switching efficiency.

Description

Method and device for realizing service fast switching by cooperation of chip and CPU

Technical Field

The invention relates to the technical field of networks, in particular to a method for realizing service fast switching by cooperation of a chip and a CPU and a device for realizing the method.

Background

In order to ensure the reliability of the service, the carrier network needs to switch the service to the backup link within a certain time under the condition of link interruption, thereby ensuring that the service is not interrupted. To ensure that no interruption is required, G.8031/G.8032/G.8131/G.8132 propose an APS protection mechanism, while Y.1731 defines a link monitoring mechanism.

Typically, an OAM (MEP) is deployed in a telecommunications network, and the MEP (maintenance end point) detects the state of the link, and upon link failure, initiates APS protection switching to switch traffic to a protection link. The link detection function of the MEP is usually realized by an ASIC chip, and the CPU is immediately reported after detecting the link abnormality, and the CPU configures the table of the ASIC chip according to the deployment condition of the APS to realize protection switching.

Currently, after detecting a link abnormality, the MEP records a corresponding error, such as a loss of continuity error. And further reporting the errors to the CPU in an interrupt mode. In order to avoid losing errors, the chip records whether the related MEP generates errors (or clears the errors) based on the hardware index of the MEP, meanwhile, the chip scans the state of the MEP at regular time and reports the state to the CPU, the CPU firstly confirms the hardware index of the MEP generating the errors, then reads the error information of the MEP, further analyzes the error reasons, and if protection switching is needed, carries out related operations. However, in this process, the CPU performs excessive IO operations, and the CPU performance may be degraded when the CPU reads the error information and parses the error information, so that the protection switching efficiency may be low.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a method for realizing service fast switching by cooperation of a chip and a CPU, which can improve the protection switching efficiency. Meanwhile, a device for realizing the service fast switching by the cooperation of the chip and the CPU is also provided.

In order to achieve the above object, an embodiment of the present invention provides a method for implementing service fast switching by cooperation of a chip and a CPU, where the method includes:

the chip judges whether the MEP generates an error or not according to the processing result of the CCM message and the updating result of the MEP, or judges whether the MEP recovers from the error or not;

the chip responds to the MEP with errors, and the errors are stored in an MEP table; or in response to the MEP recovering from the error, clearing the corresponding error in the MEP table;

the chip judges whether to report errors or not based on the detection report enabling table;

responding to the reported error, the chip takes the bit position used for marking the error generated by the corresponding MEP in the OAM detection table as a preset value or takes the bit position recovered from the error by the corresponding MEP as a preset value;

the chip scans each table item in the OAM detection table and reports an index corresponding to the table item with a preset value to the CPU;

and the CPU reads the corresponding table entry according to the index, judges whether an error is generated or recovered from the error, and performs service protection switching.

In one or more embodiments of the invention, the storing, by the chip, the error into the MEP table in response to the MEP having the error includes:

and setting the field position configured in the MEP table for identifying the error as a first preset value so as to store the error into the MEP table.

In one or more embodiments of the present invention, the chip, in response to the MEP recovering from the error, clearing the corresponding error in the MEP table includes:

and setting the field position configured in the MEP table for identifying the error as a second preset value so as to clear the error from the MEP table.

In one or more embodiments of the present invention, the determining, by the chip, whether to report the error based on the detection report enabling table includes:

the chip inquires whether a bit for identifying errors in the detection report enabling table is a preset value or not;

and the chip determines the reporting error in response to the bit for identifying the error being a preset value.

In one or more embodiments of the present invention, the OAM detection table includes a plurality of entries, each entry corresponding to at least one MEP, each MEP corresponding to a bit in the entry for indicating that the MEP generated an error and a bit for indicating that the MEP recovered from the error.

In one or more embodiments of the invention, the chip scans each entry in the OAM detection table at regular time.

In one or more embodiments of the present invention, the CPU determining whether to generate or recover from an error includes:

the CPU judges the bit used for marking MEP to produce the mistake and the bit used for marking MEP to recover from the mistake which bit is the preset value in the table item;

the CPU responds to the bit for marking the MEP to generate errors as a preset value, and determines that the errors are generated; in response to the bit indicating that the MEP recovered from the error being a preset value, recovery from the error is determined.

In one or more embodiments of the invention, the errors include lost connection, detection cycle mismatch, far-end MAC address mismatch, far-end port status mismatch, far-end interface status mismatch, far-end generated RDI error, detection endpoint mismatch, detection domain information mismatch, detection class mismatch.

In one or more embodiments of the invention, the MEP is updated periodically by a timer.

The invention also discloses a device for realizing the method, which comprises the following steps:

the first judging module is used for enabling the chip to judge whether the MEP generates an error or not according to the processing result of the CCM message and the updating result of the MEP or judging whether the MEP recovers from the error or not;

the first processing module is used for enabling the chip to respond to the MEP to have errors and storing the errors into an MEP table; or in response to the MEP recovering from the error, clearing the corresponding error in the MEP table;

a second judging module for making the chip judge whether to report the error based on the detection report enabling table

The second processing module is used for enabling the chip to respond to the reported error, and enabling bit positions of the OAM detection table for marking errors generated by the corresponding MEPs to be a preset value or enabling bit positions of the corresponding MEPs recovered from the errors to be a preset value;

the reporting module is used for enabling the chip to scan each table item in the OAM detection table and reporting an index corresponding to the table item with a preset value to the CPU;

and the third processing module is used for enabling the CPU to read the corresponding table entry according to the index, judging whether an error is generated or recovered from the error, and performing service protection switching.

Compared with the prior art, the invention can lead the CPU to perform protection switching based on whether errors are generated or not, avoid reading and analyzing error information, further reduce the processing process and effectively improve the protection switching efficiency.

Drawings

FIG. 1 is a schematic illustration of an application scenario of the invention;

FIG. 2 is a flow chart of a method for implementing fast service switching by cooperation of a chip and a CPU according to an embodiment of the invention;

FIG. 3 is a flow chart of chip reporting according to an embodiment of the present invention;

fig. 4 is a block diagram of an apparatus for implementing fast service switching by cooperation of a chip and a CPU according to an embodiment of the present invention.

Detailed Description

The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.

Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.

In the prior art, the CPU needs to read the error information of the MEP and further analyze the error cause based on the error information, and if protection switching is needed, the CPU performs corresponding operations. In the whole process, the CPU needs to do excessive IO operations, and the CPU performance is reduced when the CPU reads and analyzes error information, so that the protection switching efficiency is low. The method for realizing the service fast switching by the cooperation of the chip and the CPU ensures that the CPU performs the protection switching based on whether errors are generated or not, avoids the reading and analysis of error information, further reduces the processing process of the error information, and can effectively improve the protection switching efficiency.

Referring to fig. 1 to 3, a method for implementing service fast switching by cooperation of a chip and a CPU according to an embodiment of the present invention is applied to a scenario shown in fig. 1. In this application scenario, there is a working link and a protection link between device a and device B. When the working link fails, a link switch is needed, i.e. from service a to service B, so that the service can run forward. Meanwhile, when the working link is restored to be normal, the working link needs to be switched to, namely, the service B is switched to the service A. The method of the invention can realize the rapid switching of the service and improve the protection switching efficiency through the cooperative work of the chip and the CPU. Specifically, the method for realizing the service fast switching by the cooperation of the chip and the CPU comprises the following steps:

s1, the chip judges whether the MEP generates an error or not according to a processing result of the CCM message and an updating result of the MEP, or judges whether the MEP recovers from the error or not;

specifically, the connectivity detection function is configured to detect a connection state between maintenance endpoints, and the maintenance endpoints MEP periodically send CCM (Continuity CheckMessage, continuity detection message) messages, and other maintenance endpoints of the same maintenance alliance receive the messages. And the chip processes the CCM message after receiving the CCM message, and judges whether an error is generated according to a processing result so as to determine whether the link has a problem. In addition, the MEP also performs update processing periodically, so the chip also determines whether the MEP generates an error according to the update result to determine whether the link has a problem.

Since the error may be cleared after a certain time, the chip also needs to determine whether the MEP has recovered from the error.

In this embodiment, the errors include, but are not limited to, loss of connectivity (dLoc), detection cycle mismatch (dUnexpPeriod), far-end MAC address mismatch (rMEPMacMismatch), far-end port state mismatch (rMEPPortStatusChange), far-end interface state mismatch (rMEPIntfStatusChange), far-end generated RDI error (rMEPLastrdi), detection endpoint mismatch (dUnexpMe), detection domain information mismatch (dMismerge), detection class mismatch (dMegLvl). The MEP periodic updates may be triggered by a timer, i.e., the MEP update is triggered when the timer expires.

S2, the chip responds to the MEP that the error exists, and the error is stored in an MEP table; or in response to the MEP recovering from the error, clearing the corresponding error in the MEP table;

specifically, after the chip determines that the MEP generates an error according to the processing result of the CCM message and the update result of the MEP, the chip further stores the error information into the MEP table. The MEP table is used to store information related to the OAM state machine, including error information, that is, the MEP table may be used to store the error information. In practice, the MEP table is configured with a field for indicating the type of error, such as a field for indicating loss of connection. When the error information is stored in the MEP table, the corresponding field is set to a first preset value, for example, when the memory loses connection, the field corresponding to the error is set to the first preset value, for example, all the fields are set to 1, etc.

And after the chip judges that the MEP recovers from the error, the corresponding error in the MEP table is cleared. In implementation, the field corresponding to the error may be set to a second preset value to clear the corresponding error in the MEP table. If the error of losing connection is cleared, the value of the corresponding field in the MEP table is set to a second preset value, such as all set to 0, etc.

S3, the chip judges whether to report errors or not based on the detection report enabling table;

specifically, when the corresponding error is stored in the MEP table, or after the corresponding error is cleared from the MEP table, it is further determined whether the error needs to be reported based on a detection report enable table (deffectreport). The detection report enable table is used to indicate which errors need to be reported. The detection report enabling table is configured with a plurality of bits, each bit corresponding to one error type, and if the detection report enabling table is configured with 9 bits, each bit corresponding to one error type, as described above for the 9 errors. In practice, the chip determines whether an error is reported by querying a bit in the detection report enable table. When the bit is set to the first preset value, it indicates that the error needs to be reported. When the bit is set to the second preset value, it indicates that the error does not need to be reported. If the error of losing connection is aimed at, when the corresponding bit position is 1, the error is required to be reported; when its corresponding bit position is 0, this error is indicated as not having to be reported. By adopting the detection report enabling table, which error types need to be reported can be enabled according to the needs, and the flexibility of error reporting is increased.

In this embodiment, the detection report enabling table enables reporting of corresponding errors by configuring corresponding bits, and of course, in other embodiments, the detection report enabling table may also enable reporting of corresponding errors by configuring corresponding fields, and may be selected according to actual requirements.

S4, responding to the reported error, the chip sets the bit position used for marking the error generated by the corresponding MEP in the OAM detection table as a preset value or sets the bit position used for marking the recovery of the corresponding MEP from the error as a preset value;

specifically, when it is determined that an error needs to be reported based on the detection report enabling table, a bit position in the OAM detection table (DsOamDefectStatus) for indicating that the corresponding MEP generates an error is a preset value, or a bit position for indicating that the corresponding MEP recovers from the error is a preset value. The OAM detection table here is used to record whether each MEP is generating an error or recovering from an error. The OAM detection table comprises a plurality of table entries, each table entry comprises a plurality of bits, each MEP occupies 2 bits, one bit is used for identifying whether the MEP generates an error, and the other bit is used for identifying whether the MEP recovers from the error. For example, each entry in the OAM detection table occupies 32 bits, and when stored in 1024 MEPs, a total of 64 entries are required.

Further, when the corresponding bit position is set to a preset value, it indicates that an error is generated or recovered from the error. Indicating that the MEP is generating an error, such as when a bit for identifying whether the MEP is generating an error is set to 1; when the bit used to identify whether the MEP recovered from the error is set to 1, it indicates that the MEP recovered from the error.

S5, the chip scans each table item in the OAM detection table and reports an index corresponding to the table item with a preset value to the CPU;

specifically, after the information that an error is generated or recovered from the error is stored in the OAM detection table, the chip scans each entry in the OAM detection table, and reports an index corresponding to the entry having the preset value to the CPU. As in a certain table entry, the bit for identifying whether the MEP generated an error is set to 1. When the chip scans the table entry, the bit position for identifying whether the MEP generates errors is set to be 1, and then the index corresponding to the table entry is reported to the CPU.

In this embodiment, each entry in the OAM detection table is scanned at chip timing as the best. The chip timing scan may be triggered by a timer.

S6, the CPU reads the corresponding table item according to the index, judges whether an error is generated or recovered from the error, and performs corresponding service protection switching.

Specifically, after receiving the index, the CPU reads information stored in the corresponding entry through the index, and determines whether to generate an error or recover from the error based on the information. In practice, the CPU may determine whether an error is generated according to whether a bit in the table entry for identifying whether the MEP generates an error is a preset value, and determine whether to recover from the error according to whether a bit in the table entry for identifying whether the MEP recovers from the error is a preset value. That is, it is determined which bit is set to a preset value for identifying whether the MEP has generated an error, and for identifying whether the MEP has recovered from the error. Determining that an error is generated when a bit for identifying whether the MEP generates the error is set to a preset value; when a bit for identifying whether the MEP recovers from the error is set to a preset value, it is determined to recover from the error.

When determining that an error is generated or recovering from the error, the CPU performs switching of corresponding services, such as switching the services into a protection link when determining that the error is generated; when it is determined to recover from the error, the CPU switches the traffic into the original link.

The method for realizing the service fast switching by the cooperation of the chip and the CPU ensures that the CPU performs the service switching based on whether an error is generated or not, does not need to analyze the type of the error, reduces the processing process and can improve the service switching efficiency.

As shown in fig. 4, the invention also discloses a device for realizing the service fast switching by the cooperation of the chip and the CPU, which comprises a first judging module, a first processing module, a second judging module, a second processing module, a reporting module and a third processing module. The first judging module is used for enabling the chip to judge whether the MEP generates an error or not according to the processing result of the CCM message and the updating result of the MEP or judging whether the MEP recovers from the error or not; the first processing module is used for enabling the chip to respond to the MEP to have errors, and storing the errors into an MEP table; or in response to the MEP recovering from the error, clearing the corresponding error in the MEP table; the second judging module is used for enabling the chip to judge whether to report errors or not based on the detection report enabling table; the second processing module is used for enabling the chip to respond to the reporting error, and enabling bit positions of the OAM detection table for marking errors generated by the corresponding MEPs to be a preset value or enabling bit positions of the corresponding MEPs recovered from the errors to be a preset value; the reporting module is used for enabling the chip to scan each table item in the OAM detection table and reporting an index corresponding to the table item with a preset value to the CPU; and the third processing module is used for enabling the CPU to read the corresponding table entry according to the index, judging whether an error is generated or recovered from the error, and performing service protection switching.

When the method is implemented, the chip processes the CCM message after receiving the CCM message, and judges whether an error occurs or not through the first judging module according to the processing result so as to determine whether the link has a problem or not. In addition, the MEP also performs update processing periodically, so that the chip also judges whether the MEP generates errors or not through the first judging module according to the update result so as to determine whether the link has problems or not.

After judging that the MEP generates errors according to the processing result of the CCM message and the updating result of the MEP, the chip further stores the error information into an MEP table through the first processing module. After the chip judges that the MEP recovers from the error, the first processing module further clears the corresponding error in the MEP table. The details are described above, and will not be described in detail here.

When the chip stores the corresponding error in the MEP table or clears the corresponding error from the MEP table, the chip further judges whether the error needs to be reported or not through a second judging module based on a detection report enabling table (Defect report En). The details are described above, and will not be described in detail here.

When the chip judges that the error needs to be reported based on the detection report enabling table, a bit position used for marking that the corresponding MEP generates the error in the OAM detection table (DsOamDefectStatus) is set as a preset value, or a bit position used for marking that the corresponding MEP recovers from the error is set as a preset value through the second processing module. The details are described above, and will not be described in detail here.

After the information of generating the error or recovering from the error is stored in the OAM detection table, the chip scans each table item in the OAM detection table through the reporting module and reports the index corresponding to the table item with the preset value to the CPU.

After the CPU receives the index, the information stored in the corresponding table entry is read by the third processing module by using the index, and whether an error is generated or recovered from the error is judged based on the information. When it is determined that an error is generated or recovered from the error, the CPU performs switching of the corresponding service.

The device can realize the chip and the CPU to cooperatively realize the service quick switching method, so that the CPU performs service switching based on whether errors are generated or not, analysis on error types is not needed, the processing process is reduced, and the service switching efficiency can be improved.

It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.

Claims

1. A method for realizing service fast switching by cooperation of a chip and a CPU is characterized by comprising the following steps:

the chip judges whether the maintenance end point MEP generates an error or not according to the processing result of the continuity detection CCM message and the updating result of the maintenance end point MEP or judges whether the maintenance end point MEP recovers from the error or not;

the chip responds to the error of the maintenance end point MEP, and stores the error into a maintenance end point MEP table; or in response to the maintenance end point MEP recovering from the error, clearing the corresponding error in the maintenance end point MEP table;

responding to the reporting error, the chip takes the bit position used for marking the error generated by the corresponding maintenance end point MEP in the OAM detection table as a preset value or takes the bit position recovered from the error by the corresponding maintenance end point MEP as a preset value;

2. The method of claim 1, wherein the storing, by the chip, the error into the maintenance endpoint MEP table in response to the maintenance endpoint MEP having the error comprises:

setting a field configured in the maintenance end point MEP table for identifying the error to a first preset value to store the error in the maintenance end point MEP table.

3. The method of claim 1, wherein the chip, in response to the maintenance end point MEP recovering from the error, clearing the corresponding error in the maintenance end point MEP table comprises:

setting a field configured in the maintenance end point MEP table for identifying the error to a second preset value to clear the error from the maintenance end point MEP table.

4. The method of claim 1, wherein the chip determining whether to report an error based on a detection report enabling table comprises:

5. The method of claim 1, wherein the OAM detection table includes a plurality of entries, each entry corresponding to at least one maintenance end point MEP, each maintenance end point MEP corresponding to a bit in the entry for indicating that the maintenance end point MEP generated an error and indicating that the maintenance end point MEP recovered from the error.

6. The method of claim 5, wherein the chip scans each entry in the OAM detection table at a timing.

7. The method of claim 1, wherein the CPU determining whether to generate or recover from an error comprises:

the CPU judges the bit used for marking the maintenance end point MEP to produce the error and the bit used for marking the maintenance end point MEP to recover from the error, which bit is the preset value;

the CPU responds to the bit for marking the error generated by the maintenance end point MEP as a preset value, and determines the error; in response to the bit indicating recovery of maintenance end point MEP from the error being a preset value, recovery from the error is determined.

8. The method of claim 1, wherein the error comprises a loss of connection, a detection cycle mismatch, a far-end MAC address mismatch, a far-end port state mismatch, a far-end interface state mismatch, a far-end generation RDI error, a detection endpoint mismatch, a detection domain information mismatch, a detection level mismatch.

9. The method of claim 1, wherein the maintenance end point MEP is updated periodically by a timer.

10. An apparatus for implementing the method of any one of claims 1 to 9, wherein the apparatus comprises:

the first judging module is used for enabling the chip to judge whether the maintenance end point MEP generates an error or not according to the processing result of the continuity detection CCM message and the updating result of the maintenance end point MEP or judging whether the maintenance end point MEP recovers from the error or not;

the first processing module is used for enabling the chip to respond to the error of the maintenance end point MEP and store the error into the maintenance end point MEP table; or in response to the maintenance end point MEP recovering from the error, clearing the corresponding error in the maintenance end point MEP table;

the second judging module is used for enabling the chip to judge whether to report errors or not based on the detection report enabling table;

the second processing module is used for enabling the chip to respond to the reporting error, and enabling bit positions in the OAM detection table for marking errors generated by the corresponding maintenance end points MEPs to be preset values or enabling bit positions recovered from the errors by the corresponding maintenance end points MEPs to be preset values;