CN114937468A - Reading circuit, non-volatile memory chip and electronic device - Google Patents

Reading circuit, non-volatile memory chip and electronic device Download PDF

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Publication number
CN114937468A
CN114937468A CN202210617471.1A CN202210617471A CN114937468A CN 114937468 A CN114937468 A CN 114937468A CN 202210617471 A CN202210617471 A CN 202210617471A CN 114937468 A CN114937468 A CN 114937468A
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China
Prior art keywords
circuit
output
nmos tube
tube
storage
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CN202210617471.1A
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马继荣
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Beijing Unigroup Tsingteng Microsystems Co Ltd
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Beijing Unigroup Tsingteng Microsystems Co Ltd
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Priority to CN202210617471.1A priority Critical patent/CN114937468A/en
Publication of CN114937468A publication Critical patent/CN114937468A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)

Abstract

The application relates to the technical field of reading circuits, and discloses a reading circuit which comprises a pre-charging circuit, a storage circuit and a control circuit, wherein the pre-charging circuit is used for receiving control signals and adjusting the voltages of the storage circuit to be equal under different control signals; the output circuit is connected with the pre-charging circuit; the output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current, and outputting data to be output according to the comparison result. Thus, the voltages of the regulating storage circuits under different control signals are equal. The voltage of the storage array is equal to the voltage of the storage array when the storage array is logic 0 when the storage array is logic 1, the reading window is not reduced, the reading circuit can correctly output the data to be output, and the accuracy of the reading circuit outputting the data to be output is improved. The application also discloses a non-volatile memory chip and an electronic device.

Description

Reading circuit, non-volatile memory chip and electronic device
Technical Field
The present application relates to the field of read circuit technology, and for example, to a read circuit, a non-volatile memory chip, and an electronic device.
Background
At present, a reading circuit is usually used to read the data stored in the FLASH nonvolatile memory chip. Each reading circuit can read 1-bit data, so that when the output bit width of FLASH is 8 bits, 8 reading circuits are required. FIG. 1 is a schematic diagram of the overall structure of a non-volatile memory chip. As shown in fig. 1, one end of the read circuit 101 receives the SAENb control signal and the PRECH control signal, and the other end of the read circuit 101 is connected to one end of the column gate 102. The other end of the column gate 102 is connected to one end of the memory array 103. The other end of the memory array 103 is connected to a row decoder 104. Wherein, the SAENb control signal and the PRECH control signal are provided by a delay time sequence generating circuit. The bit lines of the memory array are BL and the word lines of the memory array are WL. In the case where the SAENb control signal is low, the read circuit is enabled. In the case where the SAENb control signal is high, the read circuit is turned off. In the case where the PRECH control signal is high, the read circuit charges the memory array. In the case where the PRECH control signal is low, the read circuit stops charging the memory array.
Fig. 2 is a schematic structural diagram of a conventional read circuit. As shown in fig. 2, the readout circuit is composed of a third PMOS (positive channel Metal Oxide Semiconductor field effect) transistor 201, a fifth NMOS (N-Metal-Oxide-Semiconductor field effect) transistor 202, a sixth NMOS transistor 203, a second current source 204, and a third inverter 205. The seventh NMOS transistor 206 and the second capacitor 207 form a memory array. The memory circuit is formed by a memory array and a column gate 208. The source of the third PMOS transistor 201 is configured to receive a voltage signal, the gate of the third PMOS transistor 201 is configured to receive a SAENb control signal, and the drain of the third PMOS transistor 201 is connected to the drain of the fifth NMOS transistor 202 and the anode of the second current source 204. The gate of the fifth NMOS transistor 202 is configured to receive the PRECH control signal, and the source of the fifth NMOS transistor 202 is connected to the cathode of the second current source 204, the input of the third inverter 205, and the drain of the sixth NMOS transistor 203. The gate of the sixth NMOS transistor 203 receives the clamp control voltage signal Vlim. The source of the sixth NMOS transistor 203 is connected to one end of the column gate 208. The other end of the column gate 208 is connected to the drain of the seventh NMOS transistor 206. The gate of the seventh NMOS transistor 206 is connected to the word line WL, and the source of the seventh NMOS transistor 206 is grounded. One end of the second capacitor 207 is connected to the source of the seventh NMOS transistor 206, and the other end of the second capacitor 207 is connected to the drain of the seventh NMOS transistor 206. The voltage value of the BL is the voltage of the storage array, and the voltage value of the BL is equal to the voltage value of the second capacitor. When the reading circuit works, the voltage of the seventh NMOS tube needs to be biased to a stable potential, then the current value flowing through the storage array is compared with the current value of the second current source through the third inverter, whether the data of the storage array is logic 0 or logic 1 is judged according to the comparison result, and the data to be output is output through the output end of the third inverter. Data to be output, for example: the memory array is a logic 0 or a logic 1. The value of the current flowing through the memory array is equal to the sum of the current flowing through the seventh NMOS tube and the current flowing through the second capacitor. When the data of the memory array is logic 1, the current in the memory array is large, and the conduction capability is large. When the data of the memory array is logic 0, the current in the memory array is small, and the conduction capability is small. In general, in designing FLASH, when the memory array is desired to be logic 1, the current flowing through the memory array is larger. When the memory array is logic 0, the current flowing through the memory array is smaller. The difference in the current through the memory array between when the memory array is logic 1 and when the memory array is logic 0 is referred to as the read window, i.e., during the design of FLASH, it is generally desirable to have a larger value for the read window. Since the PRECH control signal is fixed, when the memory array is completely charged by the read circuit, the voltage of the memory array when the memory array is logic 1 is lower than the voltage of the memory array when the memory array is logic 0. This is because when the memory array is charged to the predetermined time point, ideally, the voltage of the memory array when the memory array is logic 1 and the voltage of the memory array when the memory array is logic 0 are both charged to the inversion threshold, and the inversion threshold is equal to the clamp control voltage signal minus the threshold voltage of the second NMOS transistor. But the memory array is formed by connecting the seventh NMOS tube and the second capacitor in parallel. Therefore, after the read circuit finishes charging the memory array, due to the characteristics of the memory array, the voltage of the memory array is greater when the memory array is logic 1 than when the memory array is logic 0. The current values of the memory array logic 0 and the memory array logic 1 can be obtained by calculating I ═ K × S (Vw1-Vt) × Vb. Wherein I is the current value of the memory array; k is a constant; s is the width-length ratio of the seventh NMOS tube; vw1 is the voltage of WL; vt is the threshold voltage of the seventh NMOS tube; vb is the voltage of BL; "" is multiplication. Therefore, the voltage of the memory array is larger when the memory array is logic 1 than when the memory array is logic 0, so that the reading window is reduced, and the reading circuit outputs errors.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended to be a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a reading circuit, a non-volatile memory chip and an electronic device, so as to improve the accuracy of the reading circuit for outputting data to be output.
In some embodiments, the read circuit comprises: the pre-charging circuit is used for receiving the control signals and adjusting the voltages of the storage circuit to be equal under different control signals; the output circuit is connected with the pre-charging circuit; the output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current, and outputting data to be output according to the comparison result.
In some embodiments, the precharge circuit comprises: the NMOS transistor comprises a first PMOS transistor, a first NMOS transistor, a second NMOS transistor and a first phase inverter; the source electrode of the first PMOS tube is used for receiving a voltage signal, the grid electrode of the first PMOS tube is used for receiving a control signal, and the drain electrode of the first PMOS tube is connected with the output circuit and the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the output circuit; the source electrode of the second NMOS tube is connected with the input end of the first phase inverter, the source electrode of the second NMOS tube is used for adjusting charging and discharging of the storage circuit, and the grid electrode of the second NMOS tube receives a clamping control voltage signal.
In some embodiments, the first inverter comprises: a second PMOS tube and a third NMOS tube; the source electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the third NMOS tube to serve as the input end of the first phase inverter, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube to serve as the output end of the first phase inverter; and the source electrode of the third NMOS tube is grounded.
In some embodiments, the width-to-length ratio of the third NMOS transistor is greater than a preset multiple of the width-to-length ratio of the second PMOS transistor.
In some embodiments, the output circuit comprises: a first current source and a second inverter; the positive pole of the first current source is connected with the pre-charging circuit, and the negative pole of the first current source is connected with the input end of the second inverter and the pre-charging circuit.
In some embodiments, the read circuit further comprises: the storage circuit is connected with the pre-charging circuit; the storage circuit is used for storing data to be output and carrying out charging and discharging according to the pre-charging circuit.
In some embodiments, the memory circuit comprises: a memory array and a column gate; one end of the column gate is connected with the pre-charging circuit, and the other end of the column gate is connected with the storage array.
In some embodiments, the storage array comprises: a fourth NMOS transistor and a first capacitor; the drain electrode of the fourth NMOS tube is connected with the column gate selector, the grid electrode of the fourth NMOS tube is connected with a word line, and the source electrode of the fourth NMOS tube is grounded; one end of the first capacitor is connected with the source electrode of the fourth NMOS tube, and the other end of the first capacitor is connected with the drain electrode of the fourth NMOS tube.
In some embodiments, the nonvolatile memory chip comprises the above-mentioned read circuit.
In some embodiments, the electronic device includes the above-mentioned non-volatile memory chip.
The reading circuit, the nonvolatile memory chip and the electronic device provided by the embodiment of the disclosure can realize the following technical effects: the pre-charging circuit is used for receiving the control signals and adjusting the voltages of the storage circuits to be equal under different control signals. The output circuit is connected with the pre-charging circuit. The output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current, and outputting data to be output according to the comparison result. Thus, the voltages of the regulating storage circuits under different control signals are equal. The memory circuit comprises a column gate and a memory array, wherein the column gate is composed of a switch with small resistance, so that the voltage of the column gate is ignored. Therefore, the voltage of the memory circuit is approximately equal to the voltage of the memory array, so that the voltage of the memory array when the memory array is logic 1 is equal to the voltage of the memory array when the memory array is logic 0, and the reading window is not reduced. Therefore, the reading circuit can correctly output the data to be output, and the accuracy of the reading circuit for outputting the data to be output is improved.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated in the accompanying drawings, which correspond to the accompanying drawings and not in a limiting sense, in which elements having the same reference numeral designations represent like elements, and in which:
FIG. 1 is a schematic diagram of an overall structure of a non-volatile memory chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a conventional read circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a first read circuit according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a second read circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a third exemplary embodiment of a reading circuit;
fig. 6 is a schematic structural diagram of a fourth read circuit provided in the embodiment of the present disclosure.
Reference numerals:
101: a read circuit; 102: a column gate selector; 103: a storage array; 104: a row decoder; 201: a third PMOS tube; 202: a fifth NMOS transistor; 203: a sixth NMOS transistor; 204: a second current source; 205: a third inverter; 206: a seventh NMOS transistor; 207: a second capacitor; 208: a column gate selector; 301: a precharge circuit; 302: an output circuit; 401: a first PMOS tube; 402: a first NMOS transistor; 403: a second NMOS transistor; 404: a first inverter; 405: a first current source; 406: a second inverter; 407: a first capacitor; 408: a column gate selector; 409: a fourth NMOS transistor; 503: a storage circuit; 601: a second PMOS tube; 602: and a third NMOS transistor.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "rear", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the disclosed embodiments and their examples and are not intended to limit the indicated devices, elements or components to a particular orientation or to be constructed and operated in a particular orientation. Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meanings of these terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art as appropriate.
In addition, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, elements or components. Specific meanings of the above terms in the embodiments of the present disclosure can be understood by those of ordinary skill in the art according to specific situations.
The term "plurality" means two or more, unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.
As shown in fig. 3, an embodiment of the present disclosure provides a reading circuit including a precharge circuit 301 and an output circuit 302. The pre-charging circuit 301 is used for receiving the control signal and adjusting the voltages of the storage circuit under different control signals to be equal. The output circuit 302 is connected to the precharge circuit. The output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current, and outputting data to be output according to the comparison result.
By adopting the reading circuit provided by the embodiment of the disclosure, the pre-charging circuit is used for receiving the control signal and adjusting the voltage of the storage circuit to be equal under different control signals. The output circuit is connected with the pre-charging circuit. The output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current, and outputting data to be output according to the comparison result. Thus, the voltages of the regulating storage circuits under different control signals are equal. The memory circuit comprises a column gate and a memory array, wherein the column gate is composed of a switch with small resistance, so that the voltage of the column gate is ignored. Therefore, the voltage of the memory circuit is approximately equal to the voltage of the memory array, so that the voltage of the memory array when the memory array is logic 1 is equal to the voltage of the memory array when the memory array is logic 0, and the reading window is not reduced. Therefore, the reading circuit can correctly output the data to be output, and the accuracy of the reading circuit for outputting the data to be output is improved.
As shown in connection with fig. 4, optionally, the precharge circuit includes: a first PMOS transistor 401, a first NMOS transistor 402, a second NMOS transistor 403, and a first inverter 404. The source electrode of the first PMOS tube 401 is connected with a voltage generating circuit, the source electrode of the first PMOS tube 401 is used for receiving a voltage signal, the grid electrode of the first PMOS tube 401 is connected with a time delay sequence generating circuit, the grid electrode of the first PMOS tube 401 is used for receiving a control signal, and the drain electrode of the first PMOS tube 401 is connected with an output circuit and the drain electrode of the first NMOS tube 402. The gate of the first NMOS transistor 402 is connected to the output terminal of the first inverter 404, and the source of the first NMOS transistor 402 is connected to the drain of the second NMOS transistor 403 and the output circuit. The source of the second NMOS transistor 403 is connected to the input terminal of the first inverter 404, the source of the second NMOS transistor 403 is connected to the storage circuit, the source of the second NMOS transistor 403 is used to regulate charging and discharging of the storage circuit, the gate of the second NMOS transistor 403 is connected to the voltage regulation circuit, and the gate of the second NMOS transistor 403 is used to receive the clamp control voltage signal Vlim. The control signal is a SAENb control signal, and the SAENb control signal is a pulse signal with high and low levels. Wherein, the voltage generating circuit can be a power supply directly, for example: a battery. The working principle of the time delay and sequence generation circuit is that for the rising edge delay of a digital signal, the digital logic control signal with specific pulse width can be generated by the AND operation of the delayed signal and the original digital signal. The working principle of the voltage regulating circuit is that a band gap reference voltage value is used as a reference, a source follower or a loop voltage stabilizer and the like are used for generating required clamping control voltage, and the clamping control voltage is a clamping control voltage signal.
Optionally, the output circuit comprises: a first current source and a second inverter. The positive pole of the first current source is connected with the pre-charging circuit, and the negative pole of the first current source is connected with the input end of the second inverter and the pre-charging circuit. As shown in fig. 4, the positive pole of the first current source 405 is connected to the drain of the first PMOS transistor 401, and the negative pole of the first current source 405 is connected to the input terminal of the second inverter 406, the source of the first NMOS transistor 402, and the drain of the second NMOS transistor 403.
Optionally, the read circuit further comprises: a memory circuit. And the storage circuit is connected with the pre-charging circuit. The storage circuit is used for storing data to be output and carrying out charging and discharging according to the pre-charging circuit. As shown in fig. 4, the memory circuit is connected to the source of the second NMOS transistor 403. The storage circuit is used for storing data to be output and performing charging and discharging according to the second NMOS transistor 403. Thus, the first inverter is used to detect the voltage value of the BL, and the flipping threshold of the first inverter is approximately equal to the voltage value of the clamp control voltage signal minus the voltage value of the threshold voltage of the second NMOS transistor. When the voltage value of the BL is less than or equal to the inversion threshold, the output of the first inverter becomes high. So that the second NMOS transistor is turned on to precharge the memory circuit. When the voltage value of the BL is greater than the inversion threshold, the output of the first inverter changes to a low level. So that the second NMOS transistor is closed and the pre-charging of the memory circuit is finished. Therefore, the voltages of the storage circuit under different control signals can be adjusted to be equal in a self-adaptive mode.
Optionally, the memory circuit comprises: a memory array and a column gate. One end of the column gating device is connected with the pre-charging circuit, and the other end of the column gating device is connected with the storage array. As shown in fig. 4, one end of the column gate 408 is connected to the source of the second NMOS transistor 403, and the other end of the column gate 408 is connected to the memory array.
As shown in connection with fig. 4, optionally, the memory array includes: a fourth NMOS transistor 409 and a first capacitor 407. The drain of the fourth NMOS transistor 409 is connected to the column gate 408, the gate of the fourth NMOS transistor 409 is connected to the word line WL, and the source of the fourth NMOS transistor 409 is grounded. One end of the first capacitor 407 is connected to the source of the fourth NMOS transistor 409, and the other end of the first capacitor 407 is connected to the drain of the fourth NMOS transistor 409. Wherein the word lines are generated by a row decoder. In some embodiments, the gate of the fourth NMOS transistor 409 is connected to the row decoder. Thus, the first inverter is used to detect the voltage value of the BL, and the flip threshold of the first inverter is approximately equal to the voltage value of the clamp control voltage signal minus the voltage value of the threshold voltage of the second NMOS transistor. When the voltage value of the BL is less than or equal to the inversion threshold, the output of the first inverter becomes high. So that the second NMOS transistor is turned on to precharge the memory array. When the voltage value of the BL is greater than the inversion threshold, the output of the first inverter changes to a low level. So that the second NMOS transistor is turned off and the precharging of the memory array is completed. That is, the time for precharging the memory array varies with the voltage value of the BL so that the voltage values of the BL are the same, and the charging is stopped. Therefore, when the storage array is logic 1, the voltage of the storage array is equal to the voltage of the storage array when the storage array is logic 0, the reading window cannot be reduced, the reading circuit can correctly output the data to be output, and the accuracy of the reading circuit outputting the data to be output is improved.
In some embodiments, as shown in fig. 5, another reading circuit provided in the embodiments of the present disclosure includes: a precharge circuit 301, an output circuit 302, and a storage circuit 503. The pre-charging circuit 301 is used for receiving the control signal and adjusting the voltages of the storage circuit under different control signals to be equal. The memory circuit 503 is connected to the precharge circuit 301. The memory circuit 503 is used for storing data to be output and performs charging and discharging according to the precharge circuit 301. The output circuit 302 is connected to the precharge circuit 301. The output circuit 302 is used for generating a reference current, comparing the current of the storage circuit 503 with the reference current, and outputting data to be output according to the comparison result.
By adopting the reading circuit provided by the embodiment of the disclosure, the pre-charging circuit is used for receiving the control signal and adjusting the voltage of the storage circuit to be equal under different control signals. The output circuit is connected with the pre-charging circuit. The output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current and outputting data to be output according to the comparison result. Thus, the voltages of the regulating storage circuits under different control signals are equal. The memory circuit includes a column gate and a memory array, the column gate is formed by a switch with a small resistance, so that the voltage of the column gate is ignored. Therefore, the voltage of the memory circuit is approximately equal to the voltage of the memory array, so that the voltage of the memory array when the memory array is logic 1 is equal to the voltage of the memory array when the memory array is logic 0, and the reading window is not reduced. Therefore, the reading circuit can correctly output the data to be output, and the accuracy of the reading circuit for outputting the data to be output is improved.
As shown in connection with fig. 6, optionally, the first inverter includes: a second PMOS transistor 601 and a third NMOS transistor 602. The source electrode of the second PMOS transistor 601 is connected to the drain electrode of the first NMOS transistor 402, the gate electrode of the second PMOS transistor 601 is connected to the gate electrode of the third NMOS transistor 602 as the input terminal of the first inverter, and the drain electrode of the second PMOS transistor 601 is connected to the drain electrode of the third NMOS transistor 602 as the output terminal of the first inverter. The source of the third NMOS transistor 602 is grounded. The source of the first PMOS transistor 401 is connected to a voltage generating circuit, the source of the first PMOS transistor 401 is used for receiving a voltage signal, the gate of the first PMOS transistor 401 is connected to a delay timing generating circuit, the gate of the first PMOS transistor 401 is used for receiving a control signal, and the drain of the first PMOS transistor 401 is connected to the anode of the first current source 405 and the drain of the first NMOS transistor 402. The gate of the first NMOS transistor 402 is connected to the drain of the second PMOS transistor 601 and the drain of the third NMOS transistor 602, and the source of the first NMOS transistor 402 is connected to the drain of the second NMOS transistor 403, the negative pole of the first current source 405, and the input of the second inverter 406. The source of the second NMOS transistor 403 is connected to the gate of the second PMOS transistor 601, the gate of the third NMOS transistor 602, and one end of the column gate 408, the source of the second NMOS transistor 403 is used to regulate charging and discharging of the memory circuit, the gate of the second NMOS transistor 403 is connected to the voltage regulating circuit, and the gate of the second NMOS transistor 403 is used to receive the clamp control voltage signal Vlim. The other end of the column gate 408 is connected to the drain of a fourth NMOS transistor 409, the gate of the fourth NMOS transistor 409 is connected to the word line WL, and the source of the fourth NMOS transistor 409 is grounded. One end of the first capacitor 407 is connected to the source of the fourth NMOS transistor 409, and the other end of the first capacitor 407 is connected to the drain of the fourth NMOS transistor 409.
Optionally, the width-to-length ratio of the third NMOS transistor is greater than the width-to-length ratio of the second PMOS transistor by a preset multiple. In some embodiments, the width-to-length ratio of the third NMOS transistor is equal to 10 times the width-to-length ratio of the second PMOS transistor. Thus, the switching threshold is made closer to the clamp control voltage signal minus the threshold voltage of the second NMOS transistor. When the voltage value of the BL is less than or equal to the inversion threshold, the output of the first inverter becomes high. So that the second NMOS transistor is turned on to precharge the memory array. When the voltage value of the BL is greater than the inversion threshold, the output of the first inverter goes low. So that the second NMOS transistor is turned off and the precharging of the memory array is completed. Therefore, at the end of the pre-charging, when the storage array is logic 1, the voltage of the storage array is equal to the voltage of the storage array when the storage array is logic 0, so that the reading circuit can correctly output the data to be output, and the accuracy of outputting the data to be output by the reading circuit is improved.
The embodiment of the disclosure provides a nonvolatile memory chip, which includes the above-mentioned read circuit.
The non-volatile memory chip provided by the embodiment of the disclosure is used for receiving the control signal and adjusting the voltage of the memory circuit to be equal under different control signals through the pre-charging circuit. The output circuit is connected with the pre-charging circuit. The output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current and outputting data to be output according to the comparison result. Thus, the voltages of the regulating storage circuits under different control signals are equal. The memory circuit includes a column gate and a memory array, the column gate is formed by a switch with a small resistance, so that the voltage of the column gate is ignored. Therefore, the voltage of the memory circuit is approximately equal to the voltage of the memory array, so that the voltage of the memory array when the memory array is logic 1 is equal to the voltage of the memory array when the memory array is logic 0, and the reading window cannot be reduced. Therefore, the reading circuit can correctly output the data to be output, and the accuracy of the reading circuit for outputting the data to be output is improved.
The embodiment of the disclosure provides an electronic device, which includes the nonvolatile memory chip.
By adopting the electronic equipment provided by the embodiment of the disclosure, the pre-charging circuit is used for receiving the control signal and adjusting the voltage of the storage circuit to be equal under different control signals. The output circuit is connected with the pre-charging circuit. The output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current, and outputting data to be output according to the comparison result. Thus, the voltages of the regulating storage circuits under different control signals are equal. The memory circuit comprises a column gate and a memory array, wherein the column gate is composed of a switch with small resistance, so that the voltage of the column gate is ignored. Therefore, the voltage of the memory circuit is approximately equal to the voltage of the memory array, so that the voltage of the memory array when the memory array is logic 1 is equal to the voltage of the memory array when the memory array is logic 0, and the reading window is not reduced. Therefore, the reading circuit can correctly output the data to be output, and the accuracy of the reading circuit outputting the data to be output is improved.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (10)

1. A read circuit, comprising:
the pre-charging circuit is used for receiving the control signals and adjusting the voltages of the storage circuit to be equal under different control signals;
the output circuit is connected with the pre-charging circuit; the output circuit is used for generating reference current, comparing the current of the storage circuit with the reference current, and outputting data to be output according to the comparison result.
2. The read circuit of claim 1, wherein the precharge circuit comprises: the device comprises a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube and a first phase inverter; the source electrode of the first PMOS tube is used for receiving a voltage signal, the grid electrode of the first PMOS tube is used for receiving a control signal, and the drain electrode of the first PMOS tube is connected with the output circuit and the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the output end of the first phase inverter, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and the output circuit; the source electrode of the second NMOS tube is connected with the input end of the first phase inverter, the source electrode of the second NMOS tube is used for adjusting charging and discharging of the storage circuit, and the grid electrode of the second NMOS tube receives a clamping control voltage signal.
3. The read circuit of claim 2, wherein the first inverter comprises: a second PMOS tube and a third NMOS tube; the source electrode of the second PMOS tube is connected with the drain electrode of the first NMOS tube, the grid electrode of the second PMOS tube is connected with the grid electrode of the third NMOS tube to serve as the input end of the first phase inverter, and the drain electrode of the second PMOS tube is connected with the drain electrode of the third NMOS tube to serve as the output end of the first phase inverter; and the source electrode of the third NMOS tube is grounded.
4. The reading circuit as claimed in claim 3, wherein the width-to-length ratio of the third NMOS transistor is greater than the width-to-length ratio of the second PMOS transistor by a predetermined multiple.
5. The read circuit of claim 1, wherein the output circuit comprises: a first current source and a second inverter; the positive pole of the first current source is connected with the pre-charging circuit, and the negative pole of the first current source is connected with the input end of the second phase inverter and the pre-charging circuit.
6. The read circuit of claim 1, further comprising:
the storage circuit is connected with the pre-charging circuit; the storage circuit is used for storing data to be output and carrying out charging and discharging according to the pre-charging circuit.
7. The read circuit of claim 6, wherein the storage circuit comprises: a memory array and a column gate; one end of the column gate is connected with the pre-charging circuit, and the other end of the column gate is connected with the storage array.
8. The read circuit of claim 7, wherein the memory array comprises: a fourth NMOS transistor and a first capacitor; the drain electrode of the fourth NMOS tube is connected with the column gate selector, the grid electrode of the fourth NMOS tube is connected with a word line, and the source electrode of the fourth NMOS tube is grounded; one end of the first capacitor is connected with the source electrode of the fourth NMOS tube, and the other end of the first capacitor is connected with the drain electrode of the fourth NMOS tube.
9. A non-volatile memory chip comprising the read circuit of any one of claims 1 to 8.
10. An electronic device comprising the nonvolatile memory chip according to claim 9.
CN202210617471.1A 2022-06-01 2022-06-01 Reading circuit, non-volatile memory chip and electronic device Pending CN114937468A (en)

Priority Applications (1)

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CN202210617471.1A CN114937468A (en) 2022-06-01 2022-06-01 Reading circuit, non-volatile memory chip and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210617471.1A CN114937468A (en) 2022-06-01 2022-06-01 Reading circuit, non-volatile memory chip and electronic device

Publications (1)

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CN114937468A true CN114937468A (en) 2022-08-23

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