CN114928035A - Multi-limiter-based short-circuit current suppression strategy generation method and system - Google Patents

Multi-limiter-based short-circuit current suppression strategy generation method and system Download PDF

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CN114928035A
CN114928035A CN202210819538.XA CN202210819538A CN114928035A CN 114928035 A CN114928035 A CN 114928035A CN 202210819538 A CN202210819538 A CN 202210819538A CN 114928035 A CN114928035 A CN 114928035A
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admittance
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CN114928035B (en
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宋墩文
杨学涛
马世英
刘开欣
李希洋
丁攀
陈勇
许鹏飞
杜三恩
刘道伟
杨红英
冯静
谢家正
赵高尚
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China Electric Power Research Institute Co Ltd CEPRI
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current

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Abstract

The invention discloses a multi-limiter-based generation method and a multi-limiter-based generation system for a short-circuit current suppression strategy. The method comprises the following steps: when the III-type measures exist, calculating a III-type branch array admittance array according to the branch position added with the limiting impedance; constructing a control participation matrix of the class III limiter according to the class III branch array admittance array; implementing matrix Hamamada products on the control participation matrix and the III-class branch line array admittance matrix to generate a III-class admittance additional matrix after the impedor is transformed into a network structure; when I-type or II-type measures do not exist, generating a calculation matrix cluster containing all measures of a limiter according to row elements in the III-type admittance additional matrix; when the II type measures and the III type measures exist at the same time, forming a composite control admittance calculation matrix cluster considering the II type measures and the III type measures; and injecting the measures into basic operation mode data, and performing static safety N-1/N-2 check and transient stability N-1/N-2 check of the power grid.

Description

Multi-limiter-based short-circuit current suppression strategy generation method and system
Technical Field
The invention relates to the technical field of power grid simulation, in particular to a multi-limiter-based short-circuit current suppression strategy generation method and system.
Background
The over-standard short-circuit current is the key point of safety concern of the power grid. The short-circuit current suppression method can be divided into the network structure adjustment, the power supply access optimization, the impedance equipment addition and the like. The network structure adjusting method is a lot, considering the factors of operation convenience, adjusting flexibility and investment, and adopting measures such as reasonable partition, bus segmentation, line series or reassignment, electromagnetic ring-breaking and the like to restrain the short-circuit current of the power grid in the power grid operation stage, the branch circuit breaking is the common characteristic of the measures, the methods can reduce the electrical connection of the power grid to a certain extent and influence the power supply reliability, therefore, the methods of installing an electric reactor on an outlet wire, splitting a low-voltage winding of a transformer, changing a three-winding into self-coupling and installing an electric reactor on a bus segment loop are adopted to restrain the short-circuit current in part of the power grid, and the common point of the methods is that the impedance on the branch circuit of the power grid is changed by reforming or additionally arranging an impedance device on a primary side device to restrain the short-circuit current, and can be called as an impedance limiter short-circuit restraining method, because the power grid device is reformed, the method has long period and large investment, and is commonly used for scheme type selection in the power grid development planning stage.
In the process of realizing a machine decision short circuit control scheme based on an artificial intelligence technology, a machine is required to autonomously carry out network structure adjustment, and the adjustment needs to be carried out not only for the measure condition taking disconnection as a common point, but also for the condition of adding an impedance limiter. Because the two action principles are different, the means for transforming the power grid are also different, and although the machine autonomous generation strategy utilizes similar mathematical principles, the structural element meaning and the process are obviously different.
Disclosure of Invention
According to the invention, a multi-limiter-based short-circuit current suppression strategy generation method and a multi-limiter-based short-circuit current suppression strategy generation system are provided, so that the technical problems that the large-scale development and complexity of a power grid are aggravated, the problem that local short-circuit current is close to or exceeds a limit value is more and more frequent in power grid safety and stability calculation, and the problem that a multipoint short circuit exceeds the standard, and the searching of an effective short-circuit control measure becomes high-mental and high-labor consumption work, and is a difficult point in power grid safety and stability calculation are solved.
According to a first aspect of the present invention, there is provided a method for generating a multi-limiter based short-circuit current suppression strategy, including:
based on admittance matrix
Figure 31103DEST_PATH_IMAGE001
Calculating short-circuit current, determining the type of short-circuit control according to network characteristics or states when short-circuit superscript points exist in the short-circuit current, and selecting a proper structure adjustment measure type;
calculating an admittance augmentation matrix when a class I measure is present
Figure 466501DEST_PATH_IMAGE002
When there is a type II measure, a type II cut-off suppression short circuit is generated, and an admittance substitution matrix is calculated
Figure 485273DEST_PATH_IMAGE003
；
When the class III measures exist, the class III branch array admittance array is calculated according to the branch position added with the limiting impedance
Figure 632221DEST_PATH_IMAGE004
；
According to the class III branch line array admittance array
Figure 129061DEST_PATH_IMAGE004
Control participation matrix for constructing class III limiters
Figure 169698DEST_PATH_IMAGE005
；
Participating in the matrix for the control
Figure 624950DEST_PATH_IMAGE005
And class III branch array admittance array
Figure 259194DEST_PATH_IMAGE006
Implementing matrix Hamamada product to generate class III admittance additional matrix after impedance device is transformed into network structure
Figure 559725DEST_PATH_IMAGE007
；
When there are no class I and class II measures, appending a matrix according to the class III admittance
Figure 330235DEST_PATH_IMAGE007
Sequentially extracting admittance values of the elements in the row and superposing the admittance values on corresponding branches of the basic calculation matrix to generate a calculation matrix cluster containing limiter measures;
when the type II measures and the type III measures exist simultaneously, establishing an outer loop, and adding a matrix to the type III admittance
Figure 566176DEST_PATH_IMAGE007
The upper admittance of the middle row element is superposed on the corresponding branch of the basic calculation matrix to open up the inner partCirculating, traversing the class II cut-off and short circuit inhibition admittance replacing matrix according to rows, and backfilling admittance values on each row into the calculation matrix updated by the limiter measures one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types;
and injecting the measures into the basic operation mode data, and performing static safety N-1/N-2 checking and transient stability N-1/N-2 checking of the power grid.
Optionally based on admittance matrices
Figure 687715DEST_PATH_IMAGE008
Calculating short-circuit current, determining the short-circuit control category according to the network characteristics or state when the short-circuit current has short-circuit superscript points, and selecting a proper structure adjustment measure type, wherein the method comprises the following steps:
determining an admittance matrix according to the following formula
Figure 526358DEST_PATH_IMAGE008
：
Figure 416954DEST_PATH_IMAGE009
(1-1)
Wherein Y is ii Is a self-admittance value Y ij Is a transadmittance value;
based on the admittance matrix
Figure 73063DEST_PATH_IMAGE010
Calculating short-circuit current;
judging whether a short-circuit exceeding standard point exists in the short-circuit current according to bus interruption current threshold values of different voltage grades;
and when the short-circuit current has a short-circuit over-standard point, determining the short-circuit control type according to the network characteristics or state.
Optionally, when there is a type I measure, an augmented admittance matrix is generated
Figure 416320DEST_PATH_IMAGE011
When there is a type II measure, a type II cut-off suppression short circuit is generated, and an admittance replacement matrix is calculated
Figure 324233DEST_PATH_IMAGE012
Which comprises the following steps of;
when I-type measures exist, the standard exceeding bus is split to form a bus-coupled breaking branch, and the admittance matrix is expanded to
Figure 69335DEST_PATH_IMAGE013
：
Figure 37291DEST_PATH_IMAGE014
(2-1)
Therein is provided with
Figure 979096DEST_PATH_IMAGE015
When the strip bus is segmented, the matrix is driven
Figure 425121DEST_PATH_IMAGE016
Is raised to
Figure 290308DEST_PATH_IMAGE017
Enhanced admittance matrix
Figure 163586DEST_PATH_IMAGE018
And with
Figure 606069DEST_PATH_IMAGE019
Arrays having similar properties, for the case of measures of the type I, in subsequent steps
Figure 855785DEST_PATH_IMAGE019
Array use
Figure 575479DEST_PATH_IMAGE020
Replacing;
when there are I and II measures, generating II cut-off inhibiting short circuit, calculating admittance substitution matrix
Figure 619659DEST_PATH_IMAGE021
：
By determining the master when there is a type II actionConstruction of class II column admittance matrix by open-close branches
Figure 424804DEST_PATH_IMAGE022
Creating a branch on-off participation control matrix
Figure 87997DEST_PATH_IMAGE023
And 2, implementing the Hamamada product on the type-2 matrix to generate a type-II short circuit suppression admittance substitution matrix after the branch is disconnected
Figure 662198DEST_PATH_IMAGE024
Matrix is
Figure 877279DEST_PATH_IMAGE025
Step (2);
will be provided with
Figure 169720DEST_PATH_IMAGE026
Matrix row-by-row branch-off corresponding position substitution
Figure 761238DEST_PATH_IMAGE027
Array, forming
Figure 314579DEST_PATH_IMAGE028
-1 grid short circuit calculation matrix cluster applying on-off control
Figure 700561DEST_PATH_IMAGE029
Each computation matrix in the cluster
Figure 480298DEST_PATH_IMAGE030
A class II measure corresponding to a group of branch on-off combinations;
when adopting
Figure 875508DEST_PATH_IMAGE031
In the case of a matrix, the matrix,
Figure 158721DEST_PATH_IMAGE032
the method comprises the steps of containing I, II types of all measure sets;
Figure 355085DEST_PATH_IMAGE033
(2-2)
Figure 356539DEST_PATH_IMAGE034
(2-3)
wherein the content of the first and second substances,
Figure 24281DEST_PATH_IMAGE035
the number of open branches.
Optionally, when there is a class III measure, calculating a class III branch column admittance array according to the branch position to which the limiting impedance is added
Figure 693160DEST_PATH_IMAGE036
：
When the III-type measures exist, calculating the III-type branch column admittance array according to the branch position added with the limiting impedance by the following formula
Figure 686524DEST_PATH_IMAGE037
：
Figure 34328DEST_PATH_IMAGE038
(3-1)
Wherein the content of the first and second substances,
Figure 771340DEST_PATH_IMAGE039
numbering limiter branch positions, elements, for participation in control
Figure 29146DEST_PATH_IMAGE040
Is a branch
Figure 193411DEST_PATH_IMAGE041
The admittance value of the added limiter is added,
Figure 169457DEST_PATH_IMAGE042
all the column matrixes participating in impedance control are numbered in sequence and are provided with
Figure 319947DEST_PATH_IMAGE043
The strip branch may participate in short circuit overproof control;
recording
Figure 432260DEST_PATH_IMAGE044
Matrix elements and
Figure 767426DEST_PATH_IMAGE045
and the position mapping relation of the matrix elements.
Optionally, the class III branch array admittance array
Figure 230769DEST_PATH_IMAGE046
Control participation matrix for constructing class III limiters
Figure 309583DEST_PATH_IMAGE047
The method comprises the following steps:
let the initial participation matrix be
Figure 666615DEST_PATH_IMAGE048
The number of rows is
Figure 907103DEST_PATH_IMAGE049
The numbers 1, 0 identify the limiter branch to participate or not participate in the short circuit suppression, respectively;
associating the initial participation matrix
Figure 123321DEST_PATH_IMAGE050
The value of the element in the 1 st column is converted from 1 to 0, and a group of row matrixes with the same number of columns is obtained
Figure 740247DEST_PATH_IMAGE051
The operation is marked in the local row matrix
Figure 827152DEST_PATH_IMAGE052
The branch circuit does not participate in the short-circuit current suppression, and the two are combined to form the structure
Figure 603654DEST_PATH_IMAGE053
Matrix of
Figure 776009DEST_PATH_IMAGE053
The value of the 2 nd element in the middle column is changed from 1 to 0 to obtain one
Figure 196626DEST_PATH_IMAGE054
Of (2) matrix
Figure 138038DEST_PATH_IMAGE055
By analogy, the method is obtained by adding loop iteration operation through displacement
Figure 110542DEST_PATH_IMAGE056
Order limiter participation control matrix
Figure 35772DEST_PATH_IMAGE057
；
Figure 994501DEST_PATH_IMAGE058
(4-1)
Figure 55998DEST_PATH_IMAGE059
(4-2)
Figure 74770DEST_PATH_IMAGE060
(4-3)
Figure 831504DEST_PATH_IMAGE061
(4-4)
Figure 859503DEST_PATH_IMAGE062
(4-5)
Wherein the matrix comprises all combinations of measures for limiter control, wherein the 1 st row shows that no limiter branch participates in the short circuit control, and comprises 2 of K limiter branches k -1 all cases participating in short circuit control.
Optionally for the aboveControlling participation matrices
Figure 775506DEST_PATH_IMAGE063
And class III branch array admittance array
Figure 965179DEST_PATH_IMAGE064
Implementing matrix Hamamada product to generate class III admittance additional matrix after impedance device is transformed into network structure
Figure 599423DEST_PATH_IMAGE065
The method comprises the following steps:
for the control participation matrix according to the following formula
Figure 24588DEST_PATH_IMAGE066
And class III branch array admittance array
Figure 795098DEST_PATH_IMAGE067
Implementing matrix Hamamada product to generate class III admittance additional matrix after impedance device is transformed into network structure
Figure 421251DEST_PATH_IMAGE068
：
Figure 277212DEST_PATH_IMAGE069
（5-1）
Wherein the order is
Figure 381434DEST_PATH_IMAGE070
。
Figure 645931DEST_PATH_IMAGE071
Any row in the list represents a measure of the combination of the limiters, and each element value in the row represents an action
Figure 177407DEST_PATH_IMAGE072
The arrays correspond to the admittance variation of the branches.
Optionally, when there are no class I or class II measures, appending a matrix according to the class III admittance
Figure 786243DEST_PATH_IMAGE073
Sequentially extracting admittance values of elements in the row and superposing the admittance values on corresponding branches of the basic calculation matrix to generate a calculation matrix cluster containing all measures of the limiter, wherein the method comprises the following steps:
appending a matrix based on the class III admittance when there is no class I or II control measure
Figure 428576DEST_PATH_IMAGE073
Middle 1 to
Figure 173679DEST_PATH_IMAGE074
-1 row of cyclic values, each row of admittance values being superimposed on the corresponding element of the G matrix, such as a limiter branch
Figure 689DEST_PATH_IMAGE075
Corresponding to the G matrix as
Figure 96821DEST_PATH_IMAGE076
Line for mobile communication terminal
Figure 542846DEST_PATH_IMAGE077
Column, the class III admittance supplemental matrix
Figure 408034DEST_PATH_IMAGE078
On the middle line
Figure 281312DEST_PATH_IMAGE079
After the column element value is acted on the G matrix, the value is revised as
Figure 208948DEST_PATH_IMAGE080
In the formula
Figure 458663DEST_PATH_IMAGE081
Is zero, indicating a branch
Figure 178358DEST_PATH_IMAGE082
Does not participate in;
one or more limiters are formed to participate after the circulation is finishedAdmittance calculation matrix cluster for short circuit control
Figure 488116DEST_PATH_IMAGE083
Each computation matrix in the cluster
Figure 27682DEST_PATH_IMAGE084
Corresponding to a combination of the measures of the limiter,
Figure 940143DEST_PATH_IMAGE084
the order of the matrix is the same as that of the G matrix except that the admittance value of the branch where the limiter is located is different, and the element positions are not changed;
Figure 514344DEST_PATH_IMAGE085
（6-1）
when there is no class II control measure, from
Figure 995004DEST_PATH_IMAGE086
And sequentially taking the matrixes in the cluster in order to carry out short circuit calculation, checking the state of the short circuit exceeding the standard by using a threshold value, and observing the effectiveness and the inhibition effect of the limiter after the function is exerted.
Optionally, when there is a case of both type II and type III measures, an outer loop is established, and the class III admittance adding matrix is added
Figure 287445DEST_PATH_IMAGE087
The admittance values on the row elements in the array are superposed on the corresponding branches of the basic calculation matrix, an internal circulation is opened, the class II cut-off and short circuit inhibition admittance replacing matrix is traversed according to the rows, and the admittance values on each row are backfilled into the calculation matrix updated by the limiter measures one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types, comprising the following steps:
generation of admittance substitute computation matrix clusters according to equation 2-2
Figure 613384DEST_PATH_IMAGE088
The admittance adding matrix generated by equation 5-1
Figure 684502DEST_PATH_IMAGE089
From 1 to
Figure 70484DEST_PATH_IMAGE090
Traversing and establishing external circulation, and taking
Figure 584642DEST_PATH_IMAGE091
Elements on matrix rows are superposed to the corresponding position of the G matrix;
open up a 2 to
Figure 979851DEST_PATH_IMAGE092
Internal circulation of (2), taking
Figure 528644DEST_PATH_IMAGE093
With elements on rows of the matrix backfilled to the outer loop after modification
Figure 210161DEST_PATH_IMAGE094
The corresponding position of the matrix, the revision positions of the outer loop and the inner loop and the pointed branch are
Figure 211615DEST_PATH_IMAGE094
The positions in the middle are consistent, the internal and external circulation sequence is designed according to the mode that the cut-off is higher than the modification mode of the limiter, and the internal and external circulation sequence cannot be reversed;
after the double circulation and two admittance value revising operations, a larger-scale admittance calculation matrix cluster containing I, II and III control at the same time is constructed
Figure 144936DEST_PATH_IMAGE095
The number of the matrices is
Figure 813815DEST_PATH_IMAGE096
；
Computing matrix clusters from admittances
Figure 541599DEST_PATH_IMAGE097
And sequentially taking the matrixes in sequence to carry out short circuit calculation, and checking the state of the short circuit exceeding the standard by using a threshold value to obtain the effectiveness and the inhibition effect of the limiter after the function is exerted.
According to another aspect of the present invention, there is also provided a generating system for a multi-limiter based short-circuit current suppression strategy, including:
determining a short circuit control category module for use in a short circuit control system based on an admittance matrix
Figure 905716DEST_PATH_IMAGE098
Calculating short-circuit current, determining the short-circuit control category according to the network characteristics or state when the short-circuit current has a short-circuit over-standard point, and selecting a proper structure adjustment measure type;
a module for calculating admittance substitution matrix, which is used for generating II type cut-off and short circuit inhibition when I type and II type measures exist, and calculating admittance substitution matrix
Figure 642728DEST_PATH_IMAGE099
；
A module for calculating branch array admittance array, which is used for calculating the class III branch array admittance array according to the branch position added with the limiting impedance when the class III measures exist
Figure 166113DEST_PATH_IMAGE100
；
A control participation matrix module is constructed and used for constructing the admittance array according to the III-class branch line
Figure 64799DEST_PATH_IMAGE100
Constructing control participation matrices for class III limiters
Figure 40845DEST_PATH_IMAGE101
；
A generate admittance-append matrix module to participate in the matrix for the control
Figure 440602DEST_PATH_IMAGE101
And class III branch array admittance array
Figure 552915DEST_PATH_IMAGE102
Implementing matrix Hamamada product to generate class III admittance adding matrix after impedor is transformed into network structure
Figure 153660DEST_PATH_IMAGE103
；
A module for generating all measure matrix cluster, which is used for adding matrix according to the III type admittance when there is no I type or II type measure
Figure 351424DEST_PATH_IMAGE103
Sequentially extracting admittance values of the elements in the row, superposing the admittance values on corresponding branches of the basic calculation matrix, and generating a calculation matrix cluster containing a limiter measure;
a module for generating a class II and class III composite matrix cluster, which is used for establishing an outer loop and adding the class III admittance additional matrix when the class II and class III measures exist simultaneously
Figure 538560DEST_PATH_IMAGE104
The admittance values on the row elements in the array are superposed on the corresponding branches of the basic calculation matrix, an internal circulation is opened, the class II cut-off and short circuit inhibition admittance replacing matrix is traversed according to the rows, and the admittance values on each row are backfilled into the calculation matrix updated by the limiter measures one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types;
and the checking module is used for injecting measures into the basic operation mode data and carrying out static safety N-1/N-2 checking and transient stability N-1/N-2 checking of the power grid.
According to another aspect of the present invention, there is also provided a computer-readable storage medium storing a computer program for executing the method of any one of the above.
Therefore, a power grid short-circuit current calculation basic admittance matrix is established based on a physical network, short-circuit calculation is carried out, and when the short-circuit current exceeds the standard, selection is carried out
Figure 505379DEST_PATH_IMAGE105
The impedance branches are added to form a control admittance column matrix, the structural elements are all 1, and the number of columns is
Figure 11447DEST_PATH_IMAGE105
Of the row matrix
Figure 962085DEST_PATH_IMAGE106
From 1 to the row matrix
Figure 579011DEST_PATH_IMAGE107
Taking 1 column from the column and setting 0 column to form a new row matrix, stacking the new matrix into the formed row matrix and alternately performing 0 setting operation to finally form a limiter to participate in controlling the matrix
Figure 790550DEST_PATH_IMAGE108
. Structure of the device
Figure 467519DEST_PATH_IMAGE109
And
Figure 639874DEST_PATH_IMAGE110
and (3) the Hadamard product of the matrix, wherein the single row elements of the product matrix are superposed to the corresponding position of the short circuit calculation basic admittance array to form a measure for the short circuit suppression of the impeder combination, and the control strategy complete set containing the impeder short circuit suppression is automatically generated by traversing the rows of the product matrix.
The strategy has clear physical concept, comprehensive and understandable measure content, strong theoretical guidance, easy realization of a machine and direct application in the production and operation of the power grid. The problems that the traditional manual method is limited in sample analysis, large in human resource consumption, low in automatic processing degree and incapable of obtaining all feasible solutions or optimal solutions are solved.
Drawings
Exemplary embodiments of the invention may be more completely understood in consideration of the following drawings:
fig. 1 is a schematic flowchart of a method for generating a multi-limiter based short-circuit current suppression strategy according to this embodiment;
FIG. 2 is a schematic diagram illustrating a classification of measures for adjusting and suppressing short-circuit in a power grid structure;
fig. 3 is a schematic diagram of an intelligent generation process of a multi-limiter short-circuit suppression strategy according to this embodiment;
fig. 4 is a schematic diagram of a generating system for suppressing a short-circuit current based on multiple limiters according to this embodiment.
Detailed Description
The exemplary embodiments of the present invention will now be described with reference to the accompanying drawings, however, the present invention may be embodied in many different forms and is not limited to the embodiments described herein, which are provided for complete and complete disclosure of the present invention and to fully convey the scope of the present invention to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the accompanying drawings is not intended to be limiting of the invention. In the drawings, the same unit/element is denoted by the same reference numeral.
Unless otherwise defined, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Further, it will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.
According to a first aspect of the present invention, there is provided a method 100 for generating a multi-limiter based short-circuit current suppression strategy, referring to fig. 1, the method 100 comprising:
s101, based on admittance matrix
Figure 326071DEST_PATH_IMAGE111
Calculating short-circuit current, determining the type of short-circuit control according to network characteristics or states when short-circuit superscript points exist in the short-circuit current, and selecting a proper structure adjustment measure type;
s102, when the I type measures exist, generating an augmentation admittance matrix
Figure 267482DEST_PATH_IMAGE112
When there is a type II measure, a type II cut-and-break short circuit is generated, and an admittance substitution matrix is calculated
Figure 990718DEST_PATH_IMAGE113
；
S103, when the III type measures exist, calculating the III type branch line array admittance array according to the branch line position added with the limiting impedance
Figure 650370DEST_PATH_IMAGE114
；
S104, according to the class III branch line array admittance array
Figure 609098DEST_PATH_IMAGE114
Constructing control participation matrices for class III limiters
Figure 936175DEST_PATH_IMAGE115
；
S105, participating in the matrix for the control
Figure 689367DEST_PATH_IMAGE115
And class III branch array admittance array
Figure 960948DEST_PATH_IMAGE116
Implementing matrix Hamamada product to generate class III admittance adding matrix after impedor is transformed into network structure
Figure 723368DEST_PATH_IMAGE117
；
S106, when there is no I type or II type measure, adding matrix according to the III type admittance
Figure 639371DEST_PATH_IMAGE117
Sequentially extracting admittance values of the elements in the row, superposing the admittance values on corresponding branches of the basic calculation matrix, and generating a calculation matrix cluster containing a limiter measure;
s107, when the II type measures and the III type measures exist simultaneously, establishing an outer loop, and adding a matrix to the III type admittance
Figure 94623DEST_PATH_IMAGE117
In the method, the upper admittance of the row element is superposed on the corresponding branch of the basic calculation matrix, an inner loop is opened, the class II cut-off inhibiting short circuit admittance replacing matrix is traversed according to the row, and each row is connected with the upper admittance of the row elementBackfilling the admittance values into a calculation matrix updated by the measure of the limiter one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types;
and S108, injecting the measures into the basic operation mode data, and performing static safety N-1/N-2 checking and transient stability N-1/N-2 checking of the power grid.
Specifically, referring to fig. 2, there are 3 types of measures for suppressing short circuit in the present embodiment.
Referring to fig. 3, the intelligent generation method is divided into 8 key steps as shown in the attached drawings, wherein the steps S-1 and S-2 are a brief introduction description of the branch disconnection generation principle, and specifically include:
and (5) forming an admittance matrix of the short-circuit current calculation node and judging whether the short circuit exceeds the standard. Data node admittance matrix adopting basic operation mode
Figure 463288DEST_PATH_IMAGE118
Indicating the network connection status as in equation 1-1. According to setting calculation conditions of the national standard 'three-phase alternating current system short-circuit current calculation', load flow calculation data is selected, transient stability model data is used for calculating system short-circuit current, the condition that the short-circuit current exceeds the standard is judged according to bus interruption current threshold values of different voltage levels, and a proper structure adjustment measure type is selected by combining exceeding standard distribution.
Figure 140650DEST_PATH_IMAGE119
(1-1)
S-2, when bus segmentation measures (I-type measures) exist, the standard exceeding bus is split to form a bus-tie breaking branch, and the admittance matrix is expanded to
Figure 176739DEST_PATH_IMAGE120
See formula 2-1, there are
Figure 537314DEST_PATH_IMAGE121
When the strip bus is segmented, the matrix is driven
Figure 393274DEST_PATH_IMAGE122
Is raised to
Figure 763076DEST_PATH_IMAGE123
Enhanced admittance matrix
Figure 778305DEST_PATH_IMAGE124
And
Figure 309780DEST_PATH_IMAGE125
arrays having similar properties, for the case of measures of the type I, in subsequent steps
Figure 918616DEST_PATH_IMAGE126
Array use
Figure 560950DEST_PATH_IMAGE127
Instead of this.
Figure 306052DEST_PATH_IMAGE128
(2-1)
When the equipment is disconnected (standby) or the measure (II measure) is allocated, the dominant disconnected branch is determined (the set number is
Figure 883795DEST_PATH_IMAGE129
) Constructing class II column admittance matrices
Figure 714348DEST_PATH_IMAGE130
Further creating a branch on-off participation control matrix
Figure 160373DEST_PATH_IMAGE131
And 2, implementing the Hamamada product on the type-2 matrix to generate a type-II short circuit suppression admittance substitution matrix after the branch is disconnected
Figure 25561DEST_PATH_IMAGE132
Matrix is
Figure 898839DEST_PATH_IMAGE133
And (4) carrying out step. Will be provided with
Figure 341322DEST_PATH_IMAGE134
Substituting matrix row according to corresponding position of cut-off branch
Figure 591037DEST_PATH_IMAGE135
Array, forming
Figure 45152DEST_PATH_IMAGE136
-1 grid short circuit calculation matrix cluster applying on-off control
Figure 354911DEST_PATH_IMAGE137
Each calculation matrix in a cluster
Figure 160056DEST_PATH_IMAGE138
And (3) a II type measure corresponding to a group of branch on-off combinations. When adopting
Figure 321785DEST_PATH_IMAGE139
In the case of a matrix, the matrix,
Figure 895986DEST_PATH_IMAGE140
the I, II-class complete measure set is included.
Figure 376645DEST_PATH_IMAGE141
(2-2)
Figure 669087DEST_PATH_IMAGE142
(2-3)
S-3, when the limiter is used for restraining short circuit, the basic idea is to revise the branch impedance of the power grid part, so that the distribution of short circuit current is changed, and the short circuit standard exceeding control is further realized. According to the branch position added with the limiting impedance, calculating branch admittance to form a III-class revised array of admittance
Figure 995026DEST_PATH_IMAGE143
(formula 3-1) in the formula,
Figure 548367DEST_PATH_IMAGE144
is composed of
Figure 199928DEST_PATH_IMAGE145
Position number, element of the limiter branch participating in the control
Figure 714086DEST_PATH_IMAGE146
Is a branch
Figure 843716DEST_PATH_IMAGE147
The admittance value of the added limiter is added,
Figure 267875DEST_PATH_IMAGE148
all the column matrixes participating in impedance control are sequentially numbered
Figure 824758DEST_PATH_IMAGE149
The strip branch may participate in short-circuit over-regulation control. Recording
Figure 91792DEST_PATH_IMAGE150
Matrix elements and
Figure 25113DEST_PATH_IMAGE151
the position of the matrix elements is mapped so that the slicer participates in the controlled admittance value modification.
Figure 428412DEST_PATH_IMAGE152
(3-1)
And S-4, constructing a limiter control participation matrix according to the row number of the III-type column admittance matrix. Let the initial participation matrix be
Figure 280831DEST_PATH_IMAGE153
The number of rows is
Figure 35160DEST_PATH_IMAGE154
The numbers 1, 0 identify the participation or non-participation of the limiter branch in the short circuit suppression, respectively. Will be provided with
Figure 506593DEST_PATH_IMAGE155
Middle 1 st column elementThe value is changed from 1 to 0, and a group of row matrixes with the same column number are obtained
Figure 764399DEST_PATH_IMAGE156
The operation is marked in the local row matrix
Figure 928664DEST_PATH_IMAGE157
The branch circuit does not participate in the short-circuit current suppression, and the two are combined to form the structure
Figure 281541DEST_PATH_IMAGE158
Matrix of
Figure 291085DEST_PATH_IMAGE158
The value of the 2 nd element in the middle column is changed from 1 to 0 to obtain one
Figure 934556DEST_PATH_IMAGE159
Of (2) matrix
Figure 4143DEST_PATH_IMAGE160
. By analogy, the operation is obtained by adding loop iteration through position change
Figure 467486DEST_PATH_IMAGE161
Order limiter participation control matrix
Figure 405355DEST_PATH_IMAGE162
(equations 4-5), the matrix contains all the combinations of measures for the participation of the limiter in the control, the second one
Figure 903332DEST_PATH_IMAGE163
Line representation
Figure 409400DEST_PATH_IMAGE164
No limiter branch participates in the short circuit control.
Figure 94459DEST_PATH_IMAGE165
Is covered with
Figure 711385DEST_PATH_IMAGE166
On the strip-mounted limiter branch
Figure 63869DEST_PATH_IMAGE167
-1 participates in all cases of short circuit control.
Figure 616204DEST_PATH_IMAGE168
(4-1)
Figure 788560DEST_PATH_IMAGE169
(4-2)
Figure 943598DEST_PATH_IMAGE170
(4-3)
Figure 416167DEST_PATH_IMAGE171
(4-4)
Figure 123092DEST_PATH_IMAGE172
(4-5)
S-5 pair control participation matrix
Figure 48323DEST_PATH_IMAGE173
And class III column admittance matrix
Figure 7051DEST_PATH_IMAGE174
Implementing matrix Hamamada product to generate III-class short circuit check admittance additional matrix after impedance device is transformed into network structure
Figure 802969DEST_PATH_IMAGE175
Order of is
Figure 821741DEST_PATH_IMAGE176
。
Figure 234268DEST_PATH_IMAGE177
Any row in the figure represents a combination of the limitersEach element value in a row represents an effect
Figure 370589DEST_PATH_IMAGE178
And the admittance variable quantity of the corresponding branch of the array.
Figure 286592DEST_PATH_IMAGE179
（5-1）
S-6 is based on, in the absence of control measures of class I or II
Figure 210686DEST_PATH_IMAGE180
1 to
Figure 110509DEST_PATH_IMAGE181
-1 row cycle value, each row admittance value is superposed on the corresponding element of the G matrix as a limiter branch
Figure 411040DEST_PATH_IMAGE182
Corresponding to the G matrix of
Figure 571763DEST_PATH_IMAGE183
Line for mobile communication terminal
Figure 666758DEST_PATH_IMAGE184
Column, then
Figure 788297DEST_PATH_IMAGE185
On the middle row
Figure 892520DEST_PATH_IMAGE186
After the column element value is acted on the G matrix, the value is revised as
Figure 392902DEST_PATH_IMAGE187
In the formula
Figure 189957DEST_PATH_IMAGE188
Is zero, indicating a branch
Figure 533214DEST_PATH_IMAGE189
Do not participate in controlAnd (5) preparing. Forming one or more limiters to participate in the admittance calculation matrix cluster of the short-circuit control after the circulation is finished
Figure 441127DEST_PATH_IMAGE190
Each calculation matrix in a cluster
Figure 186229DEST_PATH_IMAGE191
Corresponding to a combination of the measures of the limiter,
Figure 13240DEST_PATH_IMAGE192
the order of the matrix is the same as that of the G matrix except that the admittance values of the branch where the limiter is located are different, and the element positions are not changed.
Figure 109371DEST_PATH_IMAGE193
（6-1）
When there is no type II control measure, from
Figure 555396DEST_PATH_IMAGE194
And sequentially taking the matrixes in the cluster in order to carry out short circuit calculation, checking the state of the short circuit exceeding the standard by using a threshold value, and observing the effectiveness and the inhibition effect of the limiter after the function is exerted.
S-7, because the type I measures depend on the type II measure inspection, only considering the situation that the type II measures and the type III measures exist simultaneously, more composite control measures are generated, and the combination form of the measures is shown in figure 3. Generation of admittance substitution computation matrix cluster according to formula 2-2
Figure 155005DEST_PATH_IMAGE195
The admittance adding matrix generated by equation 5-1
Figure 28283DEST_PATH_IMAGE196
From 1 to
Figure 611711DEST_PATH_IMAGE197
Traversing to establish external circulation, taking
Figure 984397DEST_PATH_IMAGE198
Elements on matrix rows are superposed to the corresponding position of the G matrix; open up a 2 to
Figure 704092DEST_PATH_IMAGE199
Internal circulation of (2), taking
Figure 748271DEST_PATH_IMAGE200
With elements on rows of the matrix backfilled to the outer loop after modification
Figure 553416DEST_PATH_IMAGE201
The corresponding position of the matrix, the revision positions of the outer loop and the inner loop and the pointed branch are
Figure 465877DEST_PATH_IMAGE201
Are consistent. The internal and external circulation sequence is designed according to the mode that the cut-off is higher than the modification mode of the limiter, and can not be reversed, and after the operation is finished, a certain number of identical matrixes exist, so that the effectiveness and the completeness of measures are not influenced. After double circulation and two admittance value revision operations, at most, a larger-scale admittance calculation matrix cluster containing I, II and III control simultaneously can be constructed
Figure 305657DEST_PATH_IMAGE202
The number of the matrices is
Figure 520738DEST_PATH_IMAGE203
. Slave cluster
Figure 547600DEST_PATH_IMAGE204
And sequentially taking the matrixes in sequence to carry out short circuit calculation, checking the short circuit exceeding state by using a threshold value, and observing the effectiveness and the inhibition effect of the limiter after the function is exerted.
S-8, aiming at effective control measures after the limiter plays a role, the measures are injected into basic operation mode data to carry out static safety N-1/N-2 checking and transient stability N-1/N-2 checking of the power grid, and compared with the basic operation mode data, if the static safety checking result of the power grid has no newly increased overload branch and voltage out-of-limit node and the transient stability checking has no newly increased instability fault, the measures are selected as recommended feasible short-circuit current control measures.
Therefore, aiming at the situation that the multiple limiters inhibit the short circuit from exceeding the standard, an intelligent generation method for realizing the strategy of inhibiting the short circuit current by the multiple limiters based on the Hamamada product operation is provided, and is combined with other methods for adjusting and inhibiting the short circuit from exceeding the standard, so that a more complete solution is provided for the intelligent selection of a scheme for inhibiting the short circuit from exceeding the standard. The method has clear strategy generation physical concept, strong theoretical guidance and interpretable and understandable measure contents, and can be directly applied to the power grid production operation.
Optionally based on admittance matrices
Figure 139118DEST_PATH_IMAGE008
Calculating short-circuit current, determining the short-circuit control category according to the network characteristics or state when the short-circuit current has a short-circuit superscript point, and selecting a proper structure adjustment measure type, wherein the method comprises the following steps:
determining an admittance matrix according to the following formula
Figure 443192DEST_PATH_IMAGE008
：
Figure 94753DEST_PATH_IMAGE009
(1-1)
Wherein, Y ii Is the value of self-admittance Y ij Is a transadmittance value;
based on the admittance matrix
Figure 874490DEST_PATH_IMAGE010
Calculating short-circuit current;
judging whether short-circuit exceeding standard points exist in the short-circuit current according to bus interruption current threshold values of different voltage grades;
and when the short-circuit current has a short-circuit over-standard point, determining the short-circuit control category according to the network characteristics or states.
Optionally, when there is a type I measure, an augmented admittance matrix is generated
Figure 4120DEST_PATH_IMAGE011
When there is a type II measure, a type II cut-off suppression short circuit is generated, and an admittance replacement matrix is calculated
Figure 287334DEST_PATH_IMAGE012
Comprises the following steps of;
when I-type measures exist, the standard exceeding bus is split to form a bus-tie breaking branch, and the admittance matrix is expanded to
Figure 234430DEST_PATH_IMAGE013
：
Figure 501463DEST_PATH_IMAGE014
(2-1)
Therein, there are
Figure 434784DEST_PATH_IMAGE015
When the strip bus is segmented, the matrix is driven
Figure 572505DEST_PATH_IMAGE016
Is raised to
Figure 565868DEST_PATH_IMAGE017
Of an augmented admittance matrix
Figure 428520DEST_PATH_IMAGE018
And
Figure 899953DEST_PATH_IMAGE019
arrays having similar properties, in the case of measures of the type I, in subsequent steps
Figure 423338DEST_PATH_IMAGE019
Array use
Figure 587603DEST_PATH_IMAGE020
Replacing;
when there are I and II measures, generating II cut-off inhibiting short circuit, calculating admittance substitute matrix
Figure 298070DEST_PATH_IMAGE021
：
When there is a type II measure, a type II column admittance matrix is constructed by determining the dominant open branch
Figure 697827DEST_PATH_IMAGE022
Creating a branch on-off participation control matrix
Figure 75719DEST_PATH_IMAGE023
And 2, implementing the Hamamada product on the type-2 matrix to generate a type-II short circuit suppression admittance substitution matrix after the branch is disconnected
Figure 145306DEST_PATH_IMAGE024
In a matrix of
Figure 874228DEST_PATH_IMAGE025
Step (2);
will be provided with
Figure 687463DEST_PATH_IMAGE026
Matrix row-by-row branch-off corresponding position substitution
Figure 795227DEST_PATH_IMAGE027
Array, forming
Figure 35716DEST_PATH_IMAGE028
-1 grid short circuit calculation matrix cluster applying on-off control
Figure 251934DEST_PATH_IMAGE029
Each computation matrix in the cluster
Figure 868860DEST_PATH_IMAGE030
A II type measure corresponding to a group of branch on-off combination;
when adopting
Figure 955764DEST_PATH_IMAGE031
When the matrix is used, the matrix is divided into a plurality of matrixes,
Figure 757367DEST_PATH_IMAGE032
the method comprises the steps of containing I, II types of all measure sets;
Figure 929723DEST_PATH_IMAGE033
(2-2)
Figure 350340DEST_PATH_IMAGE034
(2-3)
wherein the content of the first and second substances,
Figure 557330DEST_PATH_IMAGE035
the number of open branches.
Optionally, when the class III measure exists, calculating the class III branch array admittance array according to the branch position added with the limiting impedance
Figure 139621DEST_PATH_IMAGE036
：
When the class III measures exist, according to the branch position added with the limiting impedance, the class III branch array admittance array is calculated by the following formula
Figure 176104DEST_PATH_IMAGE037
：
Figure 134832DEST_PATH_IMAGE038
(3-1)
Wherein the content of the first and second substances,
Figure 196329DEST_PATH_IMAGE039
numbering limiter arms positions, elements, for taking part in control
Figure 480680DEST_PATH_IMAGE040
Is a branch
Figure 627628DEST_PATH_IMAGE041
The admittance value of the added limiter is added,
Figure 249102DEST_PATH_IMAGE042
all the column matrixes participating in impedance control are numbered in sequence and are provided with
Figure 165105DEST_PATH_IMAGE043
The strip branch may participate in short circuit over-standard control;
recording
Figure 620357DEST_PATH_IMAGE044
Matrix elements and
Figure 254601DEST_PATH_IMAGE045
and the position mapping relation of the matrix elements.
Optionally, the class III branch array admittance array
Figure 555132DEST_PATH_IMAGE046
Control participation matrix for constructing class III limiters
Figure 201008DEST_PATH_IMAGE205
The method comprises the following steps:
let the initial participation matrix be
Figure 561583DEST_PATH_IMAGE048
The number of rows is
Figure 683122DEST_PATH_IMAGE049
The numbers 1, 0 identify the limiter branch to participate or not participate in the short circuit suppression, respectively;
associating the initial participation matrix
Figure 787345DEST_PATH_IMAGE050
The value of the element in the 1 st column is changed from 1 to 0, and a group of row matrixes with the same column number are obtained
Figure 677940DEST_PATH_IMAGE051
The operation is marked in the local row matrix
Figure 334050DEST_PATH_IMAGE052
Branch circuit does not participate in short-circuit current suppression, twoPost-merger structure
Figure 677306DEST_PATH_IMAGE053
Matrix of
Figure 585219DEST_PATH_IMAGE053
The value of the 2 nd element in the middle column is changed from 1 to 0 to obtain one
Figure 595901DEST_PATH_IMAGE054
Of (2) matrix
Figure 298277DEST_PATH_IMAGE055
By analogy, the method is obtained by adding loop iteration operation through displacement
Figure 502732DEST_PATH_IMAGE056
Order limiter participation control matrix
Figure 683177DEST_PATH_IMAGE057
；
Figure 548365DEST_PATH_IMAGE058
(4-1)
Figure 421643DEST_PATH_IMAGE059
(4-2)
Figure 864126DEST_PATH_IMAGE060
(4-3)
Figure 113842DEST_PATH_IMAGE061
(4-4)
Figure 567957DEST_PATH_IMAGE062
(4-5)
Wherein, the matrix includes various measures combination of all limiters participating in control, wherein the 1 st row shows that no limitation is availableThe branch circuit participates in the short circuit control and covers 2 of K mounting limiter branches k -1 participates in all cases of short circuit control.
Optionally, participating in the matrix for the control
Figure 877715DEST_PATH_IMAGE206
And class III branch array admittance array
Figure 682860DEST_PATH_IMAGE064
Implementing matrix Hamamada product to generate class III admittance adding matrix after impedor is transformed into network structure
Figure 346054DEST_PATH_IMAGE065
The method comprises the following steps:
for the control participation matrix according to the following formula
Figure 920255DEST_PATH_IMAGE066
And class III branch array admittance array
Figure 932073DEST_PATH_IMAGE067
Implementing matrix Hamamada product to generate class III admittance adding matrix after impedor is transformed into network structure
Figure 335766DEST_PATH_IMAGE068
：
Figure 927284DEST_PATH_IMAGE069
（5-1）
Wherein the order is
Figure 355992DEST_PATH_IMAGE070
。
Figure 7553DEST_PATH_IMAGE071
Any row in the table represents a measure of the combination of the limiters, and each element value in the row represents an action
Figure 787290DEST_PATH_IMAGE072
The arrays correspond to the admittance variation of the branches.
Optionally, when there is no type I or type II measure, appending a matrix according to the type III admittance
Figure 41554DEST_PATH_IMAGE073
Sequentially extracting admittance values of elements in the row and superposing the admittance values on corresponding branches of the basic calculation matrix to generate a calculation matrix cluster containing all measures of the limiter, wherein the method comprises the following steps:
appending a matrix based on the class III admittance when there is no class I or II control measure
Figure 324768DEST_PATH_IMAGE073
Figure 324768DEST_PATH_IMAGE073
1 to
Figure 147230DEST_PATH_IMAGE074
-1 row of cyclic values, each row of admittance values being superimposed on the corresponding element of the G matrix, such as a limiter branch
Figure 414263DEST_PATH_IMAGE075
Corresponding to the G matrix of
Figure 82005DEST_PATH_IMAGE076
Line of
Figure 360671DEST_PATH_IMAGE077
Column, the class III admittance supplemental matrix
Figure 354035DEST_PATH_IMAGE078
On the middle line
Figure 842785DEST_PATH_IMAGE079
After the column element value is acted on the G matrix, the value is revised as
Figure 579797DEST_PATH_IMAGE080
In the formula
Figure 837603DEST_PATH_IMAGE081
Is zero, indicating a branch
Figure 860922DEST_PATH_IMAGE082
Does not participate in;
forming one or more limiters to participate in the admittance calculation matrix cluster of the short-circuit control after the circulation is finished
Figure 836968DEST_PATH_IMAGE083
Each calculation matrix in a cluster
Figure 112092DEST_PATH_IMAGE084
Corresponding to a combination of the measures of the limiter,
Figure 224405DEST_PATH_IMAGE084
except that the admittance values of the branch where the limiter is located are different from those of the G matrix, the order number of the matrix is the same, and the element positions are not changed;
Figure 933472DEST_PATH_IMAGE085
（6-1）
when there is no class II control measure, from
Figure 396815DEST_PATH_IMAGE086
And sequentially taking the matrixes in the cluster in sequence to carry out short circuit calculation, checking the state of the short circuit exceeding the standard by using a threshold value, and observing the effectiveness and the inhibition effect of the limiter after the function is exerted.
Optionally, when there is a case of both type II and type III measures, an outer loop is established, and the class III admittance adding matrix is added
Figure 475629DEST_PATH_IMAGE087
The admittance values on the row elements in the array are superposed on the corresponding branches of the basic calculation matrix, an internal circulation is opened, the class II cut-off and short circuit inhibition admittance replacing matrix is traversed according to the rows, and the admittance values on each row are backfilled into the calculation matrix updated by the limiter measures one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types, comprising the following steps:
generation of admittance substitution computation matrix clusters according to equation 2-2
Figure 708027DEST_PATH_IMAGE088
The admittance adding matrix generated by equation 5-1
Figure 948516DEST_PATH_IMAGE089
From 1 to
Figure 23788DEST_PATH_IMAGE090
Traversing and establishing external circulation, and taking
Figure 640714DEST_PATH_IMAGE091
Elements on matrix rows are superposed to the corresponding position of the G matrix;
opening one 2 to
Figure 727619DEST_PATH_IMAGE092
Internal circulation of (2), taking
Figure 404588DEST_PATH_IMAGE093
With elements on rows of the matrix backfilled to the outer loop after modification
Figure 186730DEST_PATH_IMAGE094
The corresponding position of the matrix, the revision positions of the outer loop and the inner loop and the pointed branch are
Figure 607347DEST_PATH_IMAGE094
The positions in the middle are consistent, the internal and external circulation sequence is designed according to the mode that the cut-off is higher than the modification mode of the limiter, and the internal and external circulation sequence cannot be reversed;
after the double circulation and two admittance value revising operations, a larger-scale admittance calculation matrix cluster containing I, II and III control at the same time is constructed
Figure 814338DEST_PATH_IMAGE095
The number of the matrices is
Figure 662208DEST_PATH_IMAGE096
；
Computing matrix clusters from admittance
Figure 321859DEST_PATH_IMAGE097
And sequentially taking the matrixes in sequence to carry out short circuit calculation, and checking the short circuit exceeding state by using a threshold value to obtain the effectiveness and the inhibition effect of the limiter after the function is exerted.
Therefore, a power grid short-circuit current calculation basic admittance matrix is established based on a physical network, short-circuit calculation is carried out, when short-circuit current exceeds the standard, a control admittance column matrix is formed by selecting and adding impedance branches, a row matrix with all 1 elements and columns is constructed, 1 column is taken from 1 to the columns of the row matrix, the row matrix is placed in 0 to form a new row matrix, the new matrix is stacked into the formed row matrix and is alternately operated with the placing in 0, and finally a limiter participating in the control matrix is formed. Constructing a Hadamard product of the product matrix and the matrix, superposing single row elements of the product matrix to corresponding positions of the short circuit calculation basic admittance array to form a measure for the short circuit inhibition of the impedor combination, and traversing the rows of the product matrix to automatically generate a control strategy complete set containing the impedor to inhibit the short circuit.
The strategy has clear physical concept, comprehensive and understandable measure content, strong theoretical guidance, easy realization of a machine and direct application in the production and operation of the power grid. The problems that the traditional manual method is limited in sample analysis, large in human resource consumption, low in automatic processing degree and incapable of obtaining all feasible solutions or optimal solutions are solved.
According to another aspect of the present invention, there is also provided a generating system 400 for a multi-limiter based short-circuit current suppression strategy, as shown with reference to fig. 4, the system 400 including:
determine short circuit control category module 410 for admittance matrix based
Figure 405222DEST_PATH_IMAGE098
Calculating short-circuit current, determining the type of short-circuit control according to network characteristics or states when short-circuit superscript points exist in the short-circuit current, and selecting a proper structure adjustment measure type;
a calculate admittance replace matrix module 420 for generating a class II cut-off inhibit short circuit when there are class I and class II measures, calculating an admittance replace matrix
Figure 732298DEST_PATH_IMAGE099
；
A branch array admittance calculating module 430, configured to calculate a class III branch array admittance array according to the branch position to which the limiting impedance is added when the class III measure exists
Figure 751070DEST_PATH_IMAGE100
；
A control participation matrix constructing module 440 for constructing a class III branch array admittance array according to the class III branches
Figure 632438DEST_PATH_IMAGE100
Constructing control participation matrices for class III limiters
Figure 394858DEST_PATH_IMAGE101
；
Generate admittance add matrix module 450 to participate in the matrix for the control
Figure 687692DEST_PATH_IMAGE101
And class III branch array admittance array
Figure 877365DEST_PATH_IMAGE102
Implementing matrix Hamamada product to generate class III admittance additional matrix after impedance device is transformed into network structure
Figure 511609DEST_PATH_IMAGE103
；
A generate all measures matrix cluster module 460 for appending a matrix according to the class III admittance when there are no class I or class II measures
Figure 77719DEST_PATH_IMAGE103
Sequentially extracting admittance values of the elements in the row and superposing the admittance values on corresponding branches of the basic calculation matrix to generate a calculation matrix cluster containing limiter measures;
a generate class II and class III composite matrix cluster module 470 for establishing an extrinsic cycle when there is a simultaneous occurrence of class II and class III measures, appending the class III admittance to the matrix
Figure 848229DEST_PATH_IMAGE104
The admittance values on the row elements in the array are superposed on the corresponding branches of the basic calculation matrix, an internal circulation is opened, the class II cut-off and short circuit inhibition admittance replacing matrix is traversed according to the rows, and the admittance values on each row are backfilled into the calculation matrix updated by the limiter measures one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types;
and the checking module 480 is used for injecting measures into the basic operation mode data to carry out static safety N-1/N-2 checking and transient stability N-1/N-2 checking of the power grid.
The generating system 400 for suppressing the short-circuit current based on multiple limiters according to the embodiment of the present invention corresponds to the generating method 100 for suppressing the short-circuit current based on multiple limiters according to another embodiment of the present invention, and is not described herein again.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The scheme in the embodiment of the application can be implemented by adopting various computer languages, such as object-oriented programming language Java and transliterated scripting language JavaScript.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (10)

1. A method for generating a multi-limiter-based short-circuit current suppression strategy is characterized by comprising the following steps:
based on admittance matrix
Figure 438607DEST_PATH_IMAGE001
Calculating short-circuit current, determining the type of short-circuit control according to network characteristics or states when short-circuit superscript points exist in the short-circuit current, and selecting a proper structure adjustment measure type;
generating an augmented admittance matrix when a class I measure is present
Figure 716005DEST_PATH_IMAGE002
When there is a type II measure, a type II cut-off suppression short circuit is generated, and an admittance replacement matrix is calculated
Figure 742867DEST_PATH_IMAGE003
；
When the class III measures exist, the class III branch array admittance array is calculated according to the branch position added with the limiting impedance
Figure 272068DEST_PATH_IMAGE004
；
Array admittance according to the class III branch
Figure 700775DEST_PATH_IMAGE005
Control participation matrix for constructing class III limiters
Figure 352337DEST_PATH_IMAGE006
；
For the control participation matrix
Figure 194391DEST_PATH_IMAGE007
And class III branch array admittance array
Figure 324021DEST_PATH_IMAGE008
Implementing matrix Hamamada product to generate class III admittance adding matrix after impedor is transformed into network structure
Figure 544918DEST_PATH_IMAGE009
；
When there are no class I and class II measures, the rootAccording to the class III admittance additional matrix
Figure 632959DEST_PATH_IMAGE009
Sequentially extracting admittance values of the elements in the row and superposing the admittance values on corresponding branches of the basic calculation matrix to generate a calculation matrix cluster containing limiter measures;
when the type II measures and the type III measures exist simultaneously, establishing an outer loop, and adding a matrix to the type III admittance
Figure 634413DEST_PATH_IMAGE010
The admittance values on the row elements in the array are superposed on the corresponding branches of the basic calculation matrix, an internal circulation is opened, the class II cut-off and short circuit inhibition admittance replacing matrix is traversed according to the rows, and the admittance values on each row are backfilled into the calculation matrix updated by the limiter measures one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types;
and injecting the measures into basic operation mode data, and performing static safety N-1/N-2 check and transient stability N-1/N-2 check of the power grid.
2. The method of claim 1, wherein the admittance matrix is based
Figure 630051DEST_PATH_IMAGE011
Calculating short-circuit current, determining the short-circuit control category according to the network characteristics or state when the short-circuit current has a short-circuit superscript point, and selecting a proper structure adjustment measure type, wherein the method comprises the following steps:
determining an admittance matrix according to the following formula
Figure 767771DEST_PATH_IMAGE011
：
Figure 698818DEST_PATH_IMAGE012
(1-1)
Wherein, Y ii Is the value of self-admittance Y ij Is a transadmittance value;
based on the admittance matrix
Figure 187568DEST_PATH_IMAGE013
Calculating short-circuit current;
judging whether short-circuit exceeding standard points exist in the short-circuit current according to bus interruption current threshold values of different voltage grades;
and when the short-circuit current has a short-circuit over-standard point, determining the short-circuit control type according to the network characteristics or state.
3. The method of claim 1, wherein the augmented admittance matrix is generated when the class I measure is present
Figure 721318DEST_PATH_IMAGE014
When there is a type II measure, a type II cut-off suppression short circuit is generated, and an admittance replacement matrix is calculated
Figure 979124DEST_PATH_IMAGE015
The method comprises the following steps:
when I-type measures exist, the standard exceeding bus is split to form a bus-tie breaking branch, and the admittance matrix is expanded to
Figure 579607DEST_PATH_IMAGE016
：
Figure 290074DEST_PATH_IMAGE017
(2-1)
Therein is provided with
Figure 627515DEST_PATH_IMAGE018
When the strip bus is segmented, the matrix is lifted
Figure 270986DEST_PATH_IMAGE019
Step to
Figure 340573DEST_PATH_IMAGE020
Of an augmented admittance matrix
Figure 741598DEST_PATH_IMAGE021
And
Figure 554834DEST_PATH_IMAGE022
arrays having similar properties, for the case of measures of the type I, in subsequent steps
Figure 52811DEST_PATH_IMAGE023
Array use
Figure 355616DEST_PATH_IMAGE024
Replacing;
when the measures of I type and II type exist, the disconnection of II type is generated to inhibit short circuit, and the admittance substitution matrix is calculated
Figure 306255DEST_PATH_IMAGE025
：
When there are type II measures, constructing a type II column admittance matrix by determining the dominant open branch
Figure DEST_PATH_IMAGE026
Creating a branch on-off participation control matrix
Figure 595285DEST_PATH_IMAGE027
And the 2-type matrix implements the Hamamad product to generate the II-type short circuit suppression admittance substitution matrix after the branch is cut off
Figure 744507DEST_PATH_IMAGE028
In a matrix of
Figure 421476DEST_PATH_IMAGE029
Step (2);
will be provided with
Figure 531514DEST_PATH_IMAGE030
Matrix row-by-row branch-off corresponding position substitution
Figure 952131DEST_PATH_IMAGE031
Array, forming
Figure 159121DEST_PATH_IMAGE032
-1 grid short circuit calculation matrix cluster applying on-off control
Figure 803729DEST_PATH_IMAGE033
Each calculation matrix in a cluster
Figure 463381DEST_PATH_IMAGE034
A class II measure corresponding to a group of branch on-off combinations;
when adopting
Figure 687689DEST_PATH_IMAGE035
When the matrix is used, the matrix is divided into a plurality of matrixes,
Figure 922754DEST_PATH_IMAGE036
the method comprises the steps of containing I, II types of all measure sets;
Figure 3843DEST_PATH_IMAGE037
(2-2)
Figure 416370DEST_PATH_IMAGE038
(2-3)
wherein the content of the first and second substances,
Figure 913210DEST_PATH_IMAGE039
the number of open branches.
4. The method of claim 1, wherein when a class III measure is present, the class III branch column admittance array is calculated based on the branch position to which the limiting impedance is added
Figure 766897DEST_PATH_IMAGE040
：
When the class III measures exist, according to the branch position added with the limiting impedance, the class III branch array admittance array is calculated by the following formula
Figure 956570DEST_PATH_IMAGE040
：
Figure 653130DEST_PATH_IMAGE041
(3-1)
Wherein the content of the first and second substances,
Figure 219241DEST_PATH_IMAGE042
numbering limiter arms positions, elements, for taking part in control
Figure 989751DEST_PATH_IMAGE043
For the admittance values of the limiters added on the branches,
Figure 288008DEST_PATH_IMAGE044
all the column matrixes participating in impedance control are sequentially numbered
Figure 409548DEST_PATH_IMAGE045
The strip branch may participate in short circuit over-standard control;
recording
Figure 310508DEST_PATH_IMAGE046
Matrix elements and
Figure 466682DEST_PATH_IMAGE047
and the position mapping relation of the matrix elements.
5. The method of claim 1, wherein the class III branch array admittance array is based on the class III branch array
Figure 998158DEST_PATH_IMAGE048
Control participation matrix for constructing class III limiters
Figure 279098DEST_PATH_IMAGE049
The method comprises the following steps:
let the initial participation matrix be
Figure 187011DEST_PATH_IMAGE050
The number of rows is
Figure 994430DEST_PATH_IMAGE051
The numbers 1, 0 identify the limiter branch to participate or not participate in the short circuit suppression, respectively;
associating the initial participation matrix
Figure 696807DEST_PATH_IMAGE052
The value of the element in the 1 st column is converted from 1 to 0, and a group of row matrixes with the same number of columns is obtained
Figure 792939DEST_PATH_IMAGE053
The operation is marked in the local row matrix
Figure 409602DEST_PATH_IMAGE054
The branch circuit does not participate in the short-circuit current suppression, and the two are combined to form the structure
Figure 274790DEST_PATH_IMAGE055
Matrix of
Figure 210385DEST_PATH_IMAGE055
The value of the 2 nd element in the middle column is changed from 1 to 0 to obtain one
Figure 528234DEST_PATH_IMAGE056
Of (2) matrix
Figure 450054DEST_PATH_IMAGE057
By analogy, the method is obtained by adding loop iteration operation through displacement
Figure 435327DEST_PATH_IMAGE058
Order limiter participation control matrix
Figure 276244DEST_PATH_IMAGE059
；
Figure 346968DEST_PATH_IMAGE060
(4-1)
Figure 134796DEST_PATH_IMAGE061
(4-2)
Figure 646680DEST_PATH_IMAGE062
(4-3)
Figure 861760DEST_PATH_IMAGE063
(4-4)
Figure 154202DEST_PATH_IMAGE064
(4-5)
Wherein, the matrix includes various measures combination of all limiters participating in control, wherein, the 1 st row
Figure 808037DEST_PATH_IMAGE065
Meaning that no limiter leg is involved in the short circuit control,
Figure 236744DEST_PATH_IMAGE066
covering K branch of installation limiter
Figure 560409DEST_PATH_IMAGE067
All cases participating in short circuit control.
6. The method of claim 1, wherein the control participation matrix is configured
Figure 340146DEST_PATH_IMAGE068
And class III branch array admittance array
Figure 532093DEST_PATH_IMAGE069
Implementing matrix Hamamada product to generate class III admittance adding matrix after impedor is transformed into network structure
Figure 815307DEST_PATH_IMAGE070
The method comprises the following steps:
participating in the matrix for the control according to the following formula
Figure 76918DEST_PATH_IMAGE071
And class III branch array admittance array
Figure 343951DEST_PATH_IMAGE072
Implementing matrix Hamamada product to generate class III admittance additional matrix after impedance device is transformed into network structure
Figure 11693DEST_PATH_IMAGE073
：
Figure 477309DEST_PATH_IMAGE074
（5-1）
Wherein the order is
Figure 470673DEST_PATH_IMAGE075
，
Figure 631527DEST_PATH_IMAGE076
Any row in the figure represents a combination of limiters,each element value in a row represents an action
Figure 368539DEST_PATH_IMAGE077
The arrays correspond to the admittance variation of the branches.
7. The method of claim 1, wherein when there are no class I or class II measures, appending a matrix according to the class III admittance
Figure 891924DEST_PATH_IMAGE078
Sequentially extracting admittance values of elements in the row and superposing the admittance values on corresponding branches of the basic calculation matrix to generate a calculation matrix cluster containing limiter measures, wherein the method comprises the following steps:
appending a matrix based on the class III admittance when there is no class I or II control measure
Figure 852927DEST_PATH_IMAGE079
1 to
Figure 828973DEST_PATH_IMAGE080
-1 row cycle value, each row admittance value is superposed on the corresponding element of the G matrix as a limiter branch
Figure 41780DEST_PATH_IMAGE081
Corresponding to the G matrix of
Figure 419671DEST_PATH_IMAGE082
Line of
Figure 551575DEST_PATH_IMAGE083
Column, the class III admittance supplemental matrix
Figure 749338DEST_PATH_IMAGE084
On the middle line
Figure 765836DEST_PATH_IMAGE085
Column element value ofAfter being applied to the G matrix, the value is revised as
Figure 263813DEST_PATH_IMAGE086
In the formula
Figure 504302DEST_PATH_IMAGE087
Is zero, indicating a branch
Figure 517257DEST_PATH_IMAGE088
Does not participate in;
forming one or more limiters to participate in the admittance calculation matrix cluster of the short-circuit control after the circulation is finished
Figure 134183DEST_PATH_IMAGE089
Each calculation matrix in a cluster
Figure 657306DEST_PATH_IMAGE090
Corresponding to a combination of the measures of the limiter,
Figure 334275DEST_PATH_IMAGE091
the order of the matrix is the same as that of the G matrix except that the admittance value of the branch where the limiter is located is different, and the element positions are not changed;
Figure 506631DEST_PATH_IMAGE092
（6-1）
when there is no class II control measure, from
Figure 989565DEST_PATH_IMAGE093
And sequentially taking the matrixes in the cluster in sequence to carry out short circuit calculation, checking the state of the short circuit exceeding the standard by using a threshold value, and observing the effectiveness and the inhibition effect of the limiter after the function is exerted.
8. Method according to claim 1, characterized in that, when both class II and class III measures are present, an outer loop is established, the class III being treatedClass admittance adding matrix
Figure DEST_PATH_IMAGE094
The admittance on the row element in the system is superposed on a corresponding branch of the basic calculation matrix, an internal circulation is opened, a class II cut-off is traversed according to the row to inhibit the short circuit admittance replacement matrix, and admittance values on each row are backfilled into the calculation matrix updated by the limiter measure one by one; completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types, comprising the following steps:
generation of admittance substitution computation matrix clusters according to equation 2-2
Figure 930976DEST_PATH_IMAGE095
The admittance adding matrix generated by equation 5-1
Figure 716529DEST_PATH_IMAGE096
From 1 to
Figure 376181DEST_PATH_IMAGE097
Traversing and establishing external circulation, and taking
Figure 397226DEST_PATH_IMAGE098
Elements on matrix rows are superposed to the corresponding position of the G matrix;
open up a 2 to
Figure 458723DEST_PATH_IMAGE099
Internal circulation of (2), taking
Figure 415178DEST_PATH_IMAGE100
With elements on rows of the matrix backfilled to the outer loop after modification
Figure 296546DEST_PATH_IMAGE101
The corresponding position of the matrix, the revision positions of the outer loop and the inner loop and the pointed branch are
Figure 121283DEST_PATH_IMAGE102
The positions in the middle part are consistent, the internal and external circulation sequences are designed according to the mode that the cut-off is higher than the limiter modification mode, and the internal and external circulation sequences cannot be reversed;
after the double circulation and two admittance value revising operations, a larger-scale admittance calculation matrix cluster containing I, II and III control at the same time is constructed
Figure 302865DEST_PATH_IMAGE103
The number of the matrices is
Figure 492538DEST_PATH_IMAGE104
；
Computing matrix clusters from admittance
Figure 64465DEST_PATH_IMAGE105
And sequentially taking the matrixes in sequence to carry out short circuit calculation, and checking the state of the short circuit exceeding the standard by using a threshold value to obtain the effectiveness and the inhibition effect of the limiter after the function is exerted.
9. A system for generating a multi-limiter based short circuit current suppression strategy, comprising:
the short circuit control type determining module is used for calculating short circuit current based on the admittance matrix, determining the short circuit control type according to the network characteristics or state when the short circuit current has a short circuit over-standard point, and selecting a proper structure adjustment measure type;
a module for calculating admittance substitution matrix, which is used for generating II type cut-off inhibition short circuit and calculating admittance substitution matrix when I type and II type measures exist
Figure 364996DEST_PATH_IMAGE106
；
A module for calculating branch array admittance array, which is used for calculating the class III branch array admittance array according to the branch position added with the limiting impedance when the class III measures exist
Figure 197823DEST_PATH_IMAGE107
；
Construction controlA participating matrix module for array admittance according to the class III branch line
Figure 823977DEST_PATH_IMAGE107
Control participation matrix for constructing class III limiters
Figure 679937DEST_PATH_IMAGE108
；
A module for generating an admittance supplement matrix for the control participation matrix
Figure 223307DEST_PATH_IMAGE108
And class III branch array admittance array
Figure 113903DEST_PATH_IMAGE109
Implementing matrix Hamamada product to generate class III admittance additional matrix after impedance device is transformed into network structure
Figure DEST_PATH_IMAGE110
；
A module for generating a whole measure matrix cluster for adding a matrix according to the class III admittance when there is no class I or class II measure
Figure 442116DEST_PATH_IMAGE110
Sequentially extracting admittance values of the elements in the row, superposing the admittance values on corresponding branches of the basic calculation matrix, and generating a calculation matrix cluster containing a limiter measure;
a module for generating a class II and class III composite matrix cluster, which is used for establishing an outer loop and adding the class III admittance superaddition matrix when the class II and class III measures exist simultaneously
Figure 723056DEST_PATH_IMAGE111
The admittance values on the row elements in the array are superposed on the corresponding branches of the basic calculation matrix, an internal circulation is opened, the class II cut-off and short circuit inhibition admittance replacing matrix is traversed according to the rows, and the admittance values on each row are backfilled into the calculation matrix updated by the limiter measures one by one;completing internal and external circulation to form a composite control admittance calculation matrix cluster considering II and III types;
and the checking module is used for injecting measures into the basic operation mode data and carrying out static safety N-1/N-2 checking and transient stability N-1/N-2 checking of the power grid.
10. A computer-readable storage medium, characterized in that the storage medium stores a computer program for performing the method of any of the preceding claims 1-8.
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