CN114924547A

CN114924547A - Signal electrical fault injection device

Info

Publication number: CN114924547A
Application number: CN202210483258.6A
Authority: CN
Inventors: 叶兵清; 邹涛; 范天福; 于兵; 张天宏
Original assignee: Nanjing University of Aeronautics and Astronautics
Current assignee: Nanjing University of Aeronautics and Astronautics
Priority date: 2022-05-05
Filing date: 2022-05-05
Publication date: 2022-08-19

Abstract

The invention discloses a signal electrical fault injection device, which can realize the injection of 4 common electrical faults such as short circuit between signal lines, open circuit of the signal lines, series resistance on the signal lines, lap resistance between the signal lines and the like through manual fault injection or automatic fault injection. The device consists of a control main board, a relay sub-board, a power supply configuration and an external interface. The control mainboard receives a channel electrical fault information control instruction sent by the upper computer software and converts the instruction into a relay switch instruction of a corresponding channel; the relay daughter board adopts a relay array design, and three relay modules are adopted corresponding to each channel, so that the normal, open circuit and short circuit control of channel signal electricity is realized; the power supply is configured to control the main board and the relay daughter board to supply power; the external interface is connected with other equipment such as a signal simulation case and the like. The device can realize multiple electrical fault injection, and has advantages such as modularization, extensible, easily upgrading and easily integrated.

Description

Signal electrical fault injection device

Technical Field

The invention relates to the technical field of fault simulation and test, in particular to a signal electrical fault injection device.

Background

The full-authority digital electronic control system of the aircraft engine is one of the most complex key components with the highest equipment concentration on the aircraft, and the reliability of the system is directly related to the flight safety of the whole aircraft. The electronic control unit is the core of the control system, and is essentially a high-reliability digital fault-tolerant control computer which comprises a large number of input and output signal interfaces and high-performance computing components. Wherein, the sensor of the electronic control unit and the signal cable interface of the actuating mechanism are easy to generate 4 common electrical faults such as short circuit between signal lines, open circuit of the signal lines, series resistance on the signal lines, lap resistance between the signal lines and the like. To ensure safe operation of the engine, the electronic control unit must have real-time detection and isolation capabilities for these faults. In order to ensure that the electronic control unit meets various technical indexes, the development process of the electronic control unit generally needs to be repeatedly verified in multiple links such as overall design, full-digital simulation, hardware-in-loop simulation, semi-physical simulation, bench test run, high-altitude bench test run, flight verification and the like. One test content of the hardware-in-loop simulation is to check the fault tolerance capability of the electronic control unit to the electrical faults of the signal interfaces, and a fault simulation device capable of effectively simulating the electrical faults of the 4 signal interfaces is needed.

The utility model discloses a utility model patent with publication number CN209313856U "an ARINC429 bus communication fault injection device" adopts DSP + FPGA framework to realize the electrical characteristics fault injection in four aspects of bus signal level amplitude, bus signal level duty cycle, bus signal level rising and falling slope, bus signal frequency. The invention patent with publication number CN105353755B "a multifunctional fault injection device based on PXI bus" adopts PXI bus to inject fault into the device under test. In the paper "avionics relay system multi-communication ARINC429 bus fault injection method" of "computer measurement and control" volume 29, No. 8, by Yan Hooyong et al, a data interaction mode of the avionics relay system is analyzed, a fault injection architecture based on the avionics relay system is designed, and a multichannel parallel fault injection method based on a reflective memory communication network is researched.

In the prior art, the function of manual fault injection can be realized, the function is single, and the fault detection efficiency is low. Thus, the invention provides a more comprehensive solution.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides a signal electrical fault injection device, which can realize the injection of 4 common electrical faults such as short circuit between signal lines, open circuit of the signal lines, series resistance on the signal lines, overlap resistance between the signal lines and the like through manual fault injection or automatic fault injection, wherein the fault type is defined as shown in figure 2.

In order to achieve the purpose, the invention designs a signal electrical fault injection device which comprises a control main board, a relay sub-board, a power supply configuration and an external interface. And the control mainboard receives a channel electrical fault information control instruction sent by the upper computer software and converts the instruction into a relay switch instruction of a corresponding channel. The relay daughter board is designed by adopting a relay array, and three relay modules are adopted corresponding to each channel, so that the normal, open and short circuit control of channel signal electricity is realized. The power supply is configured to control the main board and the relay daughter board to supply power. The external interface adopts two aviation plugs, one end of each aviation plug is a signal input port and is connected to the sensor signal simulation case, and the other end of each aviation plug is a signal output port and is connected to the health management unit.

The signal electrical fault injection device can realize two functions of manual fault injection and automatic fault injection. The manual fault injection utilizes the wiring panel and the wiring terminals, and realizes electrical faults such as short circuit between signal lines, signal line open circuit, overlap resistance between the series resistance on the signal lines and the signal lines, and the like through the plugging and unplugging of the wiring terminals. The working principle of the automatic fault injection is shown in fig. 1, and the automatic fault injection has three parts: the relay matrix structure diagram is shown in figure 3, and the upper computer software is signal electrical fault injection and configuration management software.

Furthermore, the upper computer software establishes communication with the main control board through a TCP protocol, sends channel state information (normal, open, front end and back short circuit) to the main control board, receives the relay state information returned by the main control board in real time, processes the information and displays the processed information in an upper computer interface. The main control board is designed based on an ARM chip, receives TCP protocol data sent by an upper computer, converts the TCP protocol data into an SPI bus and sends the SPI bus to the relay daughter board, the main control board realizes board selection of the relay daughter board through a bus controller, and on-off of each relay in a relay matrix is realized through relay control logic. The relay sub-board converts an SPI signal into a high-low level through a 74HC595 shift register chip to control a relay switch, as shown in FIG. 3, when S1 and S2 are closed and S3 is opened, the electrical state of the signal is normal, when S1 and S2 are opened and S3 is opened, a signal channel is opened, when S1, S2 and S3 are closed, the front of the signal channel is short-circuited, and when S1 and S2 are opened and S3 is closed, the rear of the signal channel is short-circuited.

The signal electrical fault injection device provided by the invention can realize the injection of 4 common electrical faults such as short circuit between signal lines, open circuit of the signal lines, series resistance on the signal lines, lap resistance between the signal lines and the like through manual fault injection or automatic fault injection.

Drawings

Fig. 1 is a schematic diagram of the operation of a signal electrical fault injection apparatus.

Fig. 2 is an illustration of four common electrical fault types.

Fig. 3 is a diagram of a relay matrix structure.

FIG. 4 is an engine fault simulation platform hardware implementation.

Fig. 5 is a circuit diagram of the control motherboard according to the embodiment.

Fig. 6 is a physical diagram of a relay daughter board circuit of a specific embodiment.

Fig. 7 is a pictorial diagram of a signal electrical fault injection apparatus and external interface of an embodiment.

FIG. 8 is a JTAG interface circuit diagram of a particular embodiment.

Fig. 9 is a circuit diagram of an ethernet interface of a particular embodiment.

Fig. 10 is a power supply circuit diagram of a specific embodiment.

FIG. 11 is a diagram of a chip reset circuit of a specific embodiment.

FIG. 12 is a circuit diagram of a control motherboard board select signal of a specific embodiment.

Fig. 13 is a relay daughter board SPI signal resolution circuit of an embodiment.

Fig. 14 is a circuit diagram of a relay daughter board relay matrix of a particular embodiment.

Fig. 15 is a relay daughter board relay function self-test circuit of a specific embodiment.

Detailed Description

Reference will now be made in detail to specific embodiments of the invention. While the invention will be described in conjunction with the specific embodiments, it will be understood that they are not intended to limit the invention to the embodiments described. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims. It should be noted that the method steps described herein may be implemented by any functional block or functional arrangement, and that any functional block or functional arrangement may be implemented as a physical entity or a logical entity, or a combination of both.

In order that those skilled in the art will better understand the present invention, the following detailed description of the invention is provided in conjunction with the accompanying drawings and the detailed description of the invention.

Note that: the example to be described next is only a specific example, and does not limit the embodiments of the present invention necessarily to the following specific steps, values, conditions, data, orders, and the like. Those skilled in the art can, upon reading this specification, utilize the concepts of the present invention to construct more embodiments than those specifically described herein.

The signal electrical fault injection device provided by the invention can be used for an engine fault simulation platform as shown in fig. 4, wherein the engine fault simulation platform comprises a fault simulation platform, an engine health management unit and a plurality of monitoring or management computers (including a database). The fault simulation platform comprises 3 parts, namely a real-time computing unit (a high-performance ATOM + FPGA platform, analog quantity interfaces and digital quantity interfaces), a sensor signal simulation case and a signal electrical fault injection case. According to the characteristics and the requirements of the engine health management unit, the engine fault simulation platform can realize direct fault simulation, engine characteristic slow-change fault simulation based on an engine model and fault simulation based on data playback

A signal electrical fault injection device comprises a control main board, a relay sub-board, a power supply configuration and an external interface, wherein a real object circuit of the control main board is shown in figure 5, a real object circuit of the relay sub-board is shown in figure 6, and a signal electrical fault injection device and the external interface are shown in figure 7.

The signal electrical injection unit control main board ARM adopts a TM4C1294 chip of a core of a cotex M4 of TI company, the chip integrates an Ethernet hardware interface and has excellent connectivity, the main control board comprises a power supply circuit, a JTAG circuit, a chip reset circuit, a board chip selection circuit and an Ethernet interface circuit, the JTAG interface circuit diagram is shown in figure 8, and the Ethernet interface circuit diagram is shown in figure 9.

The power supply of the main control board is divided into 5V and 3.3V, 5V power supply is realized by adopting a linear power supply module converting 220V into 5V, 5V is converted into 3.3V by adopting an AMS1117 linear voltage stabilizer chip, and the maximum working current of the linear voltage stabilizer can reach 1A. The reset circuit utilizes the reset pin of TM4C1294 chip

The pin is active at a low level, and when the ripple switch is pressed down, the pin is pulled down to 0V and then restored to 3.3V, so that the chip reset is realized, a power supply circuit diagram is shown in fig. 10, and a chip reset circuit diagram is shown in fig. 11. The board selection signal adopts a 74HC245 eight-way signal transceiver to drive the relay daughter board, and the specific circuit is shown in FIG. 12.

The signal electrical fault injection chassis relay daughter board comprises an SPI signal analysis circuit, a relay matrix circuit and a relay function self-checking circuit, wherein the SPI signal analysis circuit adopts an 8-bit serial input 74HC595 shift register, when single-row data are input into a chip, the front 8-bit data are output to high and low levels through Q0-Q7, other data are output to a next shift register through Q7', the rear end of the 74HC595 chip adopts a Darlington tube to drive a relay, and ULN2803 chips are output through 8 collectors, the circuit diagram is shown in fig. 13, and the signal electrical fault injection chassis relay daughter board relay matrix circuit diagram is shown in fig. 14. The relay function self-checking circuit for the relay daughter board of the signal electrical fault injection chassis adopts a TIC10024 chip which is a multi-switch detection interface device, can monitor 24-way switch input, can bear-24V-40V switch voltage, and is directly connected with the outside through a Serial Peripheral Interface (SPI) protocol, and a circuit diagram is shown in fig. 15.

Claims

1. The utility model provides a signal electrical fault injection apparatus, includes control mainboard, relay daughter board, power configuration and external interface, its characterized in that:

the control main board receives a channel electrical fault information control instruction sent by upper computer software and converts the instruction into a relay switch instruction of a corresponding channel;

the relay daughter board is designed by adopting a relay array, and three relay modules are adopted corresponding to each channel, so that the normal, open circuit and short circuit control of channel signal electricity is realized;

the power supply is configured to control the main board and the relay sub-board to supply power;

the external interface adopts two aviation plugs, one end of the external interface is a signal input port and is connected to the sensor signal simulation case, and the other end of the external interface is a signal output port and is connected to the health management unit.

2. The electrical signal fault injection apparatus according to claim 1, wherein 4 common electrical faults such as short circuit between signal lines, open circuit between signal lines, series resistance on signal lines and overlap resistance between signal lines can be injected by manual fault injection or automatic fault injection.

3. The manual fault injection function as claimed in claim 2, wherein 4 kinds of common electrical faults, such as short circuit between signal lines, open circuit of signal lines, series resistance on signal lines and overlap resistance between signal lines, are injected by plugging in and out the connection terminals by using the wiring panel and the connection terminals.

4. The automatic fault injection function as claimed in claim 2 comprises three parts of upper computer software, a main control board and a relay daughter board, wherein the upper computer software establishes communication with the main control board through a TCP protocol, channel state information is sent to the main control board, relay state information returned by the main control board is received in real time, the information is processed and displayed in an interface of the upper computer, the main control board is designed based on an ARM chip, TCP protocol data sent by the upper computer is received and converted into an SPI bus to be sent to the relay daughter board, the main control board realizes board selection of the relay daughter board through a bus controller, on-off of each relay in a relay matrix is realized through relay control logic, and the relay daughter board converts SPI signals into high and low levels through a shift register chip to control a relay switch.