CN114916011A

CN114916011A - Control method of UWB baseband chip, UWB main control chip and storage medium

Info

Publication number: CN114916011A
Application number: CN202210530920.9A
Authority: CN
Inventors: 张华龙; 李华伟
Original assignee: Chipsbank Technologies Shenzhen Co ltd
Current assignee: Chipsbank Technologies Shenzhen Co ltd
Priority date: 2022-05-16
Filing date: 2022-05-16
Publication date: 2022-08-16

Abstract

The embodiment of the application discloses a control method of a UWB baseband chip, a UWB main control chip and a storage medium, which are used in the technical field of wireless communication. The method of the embodiment of the application comprises the following steps: establishing a data communication channel with the UWB baseband chip based on an SPI interface; obtaining a first command frame for transmitting a command to the UWB baseband chip, the first command frame comprising a configurable identification bit and a data byte; configuring the identification bit of the first command frame to obtain a second command frame; and sending the second command frame to the UWB baseband chip through the data communication channel so as to control the UWB baseband chip to carry out data interaction based on the identification bit and the data byte in the second command frame. In the embodiment of the application, the second command frame is obtained by configuring the identification bit of the first command frame, and the second command frame is sent to the UWB baseband chip, so that the control on the UWB baseband chip can be efficiently and flexibly realized.

Description

Control method of UWB baseband chip, UWB main control chip and storage medium

Technical Field

The embodiment of the application relates to the technical field of wireless communication, in particular to a control method of a UWB baseband chip, a UWB main control chip and a storage medium.

Background

In modern communication, an Ultra Wide Band (UWB) technology is a new communication technology, is established on the basis of low-energy radio signals, can realize short-distance high-speed data transmission, has the characteristics of high transmission rate, multipath interference resistance, simple structure and the like, is widely used in the aspects of precise positioning, radar, wireless communication and the like, and is a hotspot technology in the field of current short-distance communication.

The existing control process of the UWB baseband chip is generally that the UWB main control chip sends a control command to the UWB baseband chip, and the UWB baseband chip performs corresponding data interaction with the UWB main control chip in response to the control command. Based on the consideration of cost and power consumption, the interface connection between the UWB baseband chip and the UWB main control chip needs to be reduced as much as possible.

The conventional UWB baseband chip generally uses an SPI (serial Peripheral interface) interface to define a specific SPI data frame for receiving a control command from the UWB main control chip. However, the frame structure of a specific SPI data frame is generally fixed, and it is difficult to provide an extensible address space and access to an arbitrary address space requires a large number of clocks, which complicates the control of the UWB host chip on the UWB baseband chip and reduces the transmission efficiency between the UWB host chip and the UWB baseband chip.

Disclosure of Invention

The embodiment of the application provides a control method of a UWB baseband chip, a UWB main control chip and a storage medium, which can efficiently and flexibly realize the control of the UWB baseband chip.

The embodiment of the application provides a control method of a UWB baseband chip, which comprises the following steps:

establishing a data communication channel with the UWB baseband chip based on an SPI interface;

acquiring a first command frame for transmitting a command to the UWB baseband chip, wherein the first command frame comprises a configurable identification bit and a data byte;

configuring the identification bit of the first command frame to obtain a second command frame;

and sending the second command frame to the UWB baseband chip through the data communication channel so as to control the UWB baseband chip to carry out data interaction based on the identification bit and the data byte in the second command frame.

Further, the identification bits of the first command frame include: a byte flag bit, a read-write flag bit and a write mode bit;

the configuring the identification bit of the first command frame to obtain a second command frame includes:

and configuring the byte zone bit, the read-write zone bit and the write mode bit in the first command frame respectively to obtain the second command frame.

Further, the separately configuring the byte flag bit, the read-write flag bit, and the write mode bit in the first command frame includes:

configuring the byte flag bits in the first command frame as double bytes;

forming a double-byte register read-write command based on the double-byte flag bit and the register address of the identification bit;

configuring the read-write flag bit in the first command frame as a read operation; or, configuring the read-write flag bit in the first command frame as a write operation, and configuring the write mode bit as one of a normal write, an and operation, an or operation, and an xor operation.

Further, the separately configuring the byte flag bit, the read-write flag bit, and the write mode bit in the first command frame to obtain the second command frame includes:

configuring the byte flag bits in the first command frame into single bytes to form a single-byte command;

configuring the read-write flag bit and the write mode bit as read operation when the single-byte command forms a single-byte register read-write command based on the register address offset of the identification bit; or, when the single byte command is a single byte register read-write command, configuring the read-write flag bit as write operation, and configuring the write mode bit as one of ordinary write, and operation, or operation and exclusive or operation;

and when the single-byte command forms a single-byte system command based on the system control command configured in advance in the identification bit, configuring the read-write zone bit and the write mode bit as control operation.

Further, the method further comprises:

and expanding the data bytes in the first command frame into corresponding system command bits when the single-byte command is a single-byte system command and the single-byte command is more than a preset number.

Further, the establishing a data communication channel with the UWB baseband chip based on the SPI interface includes:

and respectively establishing a data input channel, a data output channel, a clock signal channel and a chip selection signal channel with the UWB baseband chip based on the SPI interface.

Further, said sending said second command frame to said UWB baseband chip through said data communication channel comprises:

determining a target UWB baseband chip from a plurality of UWB baseband chips based on a chip selection signal in the chip selection signal channel;

and sending the second command frame to the target UWB baseband chip through the data input channel.

The embodiment of the application also provides a UWB main control chip, which comprises;

the establishing unit is used for establishing a data communication channel with the UWB baseband chip based on the SPI interface;

the acquisition unit is used for acquiring a first command frame for transmitting a command to the UWB baseband chip, wherein the first command frame comprises a configurable identification bit and a data byte;

the configuration unit is used for configuring the identification bit of the first command frame to obtain a second command frame;

and the control unit is used for sending the second command frame to the UWB baseband chip through the data communication channel so as to control the UWB baseband chip to carry out data interaction based on the identification bit and the data byte in the second command frame.

The embodiment of the present application further provides a UWB main control chip, including:

the system comprises a central processing unit, a memory, an input/output interface, a wired or wireless network interface and a power supply;

the memory is a transient memory or a persistent memory;

the central processor is configured to communicate with the memory, and execute the instruction operations in the memory on the control plane functional entity to execute the control method.

The embodiment of the application also provides a computer-readable storage medium, which comprises instructions, and when the instructions are run on a computer, the instructions cause the computer to execute the control method.

According to the technical scheme, the embodiment of the application has the following advantages:

in the embodiment of the application, a second command frame is obtained by obtaining a first command frame used for transmitting a command to the UWB baseband chip and configuring an identification bit of the first command frame; and sending the second command frame to the UWB baseband chip so as to control the UWB baseband chip to carry out data interaction based on the identification bit and the data byte in the second command frame, thereby efficiently and flexibly realizing the control of the UWB baseband chip.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

Fig. 1 is a diagram of a communication architecture disclosed in an embodiment of the present application;

FIG. 2 is a control flow diagram of a UWB baseband chip according to the embodiment of the present application;

FIG. 3 is a signal diagram of an SPI interface according to an embodiment of the present disclosure;

FIG. 4 is a diagram illustrating a structure of a command frame according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a two-byte command frame disclosed in an embodiment of the present application;

FIG. 6 is a diagram illustrating a single byte register read/write command according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a single byte system command disclosed in an embodiment of the present application;

fig. 8 is a schematic diagram of a UWB main control chip disclosed in the embodiments of the present application;

fig. 9 is a schematic diagram of another UWB main control chip disclosed in the embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the embodiments of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the embodiments of the present application and simplifying the description, but do not indicate or imply that the referred devices or elements must have specific orientations, be configured in specific orientations, and operate, and thus, should not be construed as limiting the embodiments of the present application.

In the description of the embodiments of the present application, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless explicitly stated or limited otherwise; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. Specific meanings of the above terms in the embodiments of the present application can be understood in specific cases by those of ordinary skill in the art.

As shown in fig. 1, the existing UWB baseband chip 102 generally performs a control procedure in which the UWB main control chip 101 sends a control command to the UWB baseband chip 102, and the UWB baseband chip 102 performs corresponding data interaction with the UWB main control chip 101 in response to the control command. The conventional UWB baseband chip 102 generally employs an SPI interface, and defines a specific SPI data frame for receiving a control command from the UWB main control chip 101. It is understood that one UWB main control chip 101 may be connected to a plurality of UWB baseband chips 102, and the plurality of UWB baseband chips 102 serve as slave devices of the UWB main control chip 101 to receive control commands from the UWB main control chip 101. However, the frame structure of a specific SPI data frame is generally fixed, and it is difficult to provide an extensible address space and access to an arbitrary address space requires a large number of clocks, which complicates the control of the UWB host chip on the UWB baseband chip and reduces the transmission efficiency between the UWB host chip and the UWB baseband chip. Therefore, an embodiment of the present application provides a method for controlling a UWB baseband chip, which can efficiently and flexibly implement control of the UWB baseband chip, and as shown in fig. 2, the method includes the following specific steps:

201. and establishing a data communication channel with the UWB baseband chip based on the SPI interface.

In the embodiment of the application, a host control interface adopted by the UWB main control chip is mainly a 4-wire SPI interface, the SPI interface is generally used for communication between a master device and a slave device, wherein the UWB main control chip is the master device, and the UWB baseband chip is the slave device. And the UWB main control chip establishes a data communication channel with the UWB baseband chip based on the SPI interface. It can be understood that the SPI interface is used to allow the UWB host chip to send command frames to the UWB baseband chip, and the UWB baseband chip has a function of executing the relevant command frames, thereby implementing a function of controlling the UWB baseband chip or reading and writing an internal register of the UWB baseband chip.

The SPI generally occupies four pins of the UWB baseband chip, which are respectively a data input (SDI), a data output (SDO), a clock Signal (SCLK), and a chip select signal (CS); therefore, the UWB main control chip establishes a data input channel, a data output channel, a clock signal channel and a chip selection signal channel with the UWB baseband chip based on the SPI interface. As shown in fig. 3, SPI signals based on the SPI interface generally follow the corresponding communication protocol: the spi _ cs signal is set to 0, indicating the start of a command frame; the spi _ cs signal is set to 1, indicating the end of a command frame. A command frame always starts with one or more bytes of command, followed by one or more bytes of data. The slave device (UWB baseband chip) always receives the command and then, according to the command, returns the corresponding data. All byte transfers begin with the most significant bit and end with the least significant bit. When multi-byte transmission is performed, the low byte is transmitted first, and the high byte is transmitted last. The host (UWB master chip) can terminate the transmission at any time by setting spi _ cs to 1. Bytes that have been transferred are valid bytes and bytes that have not been completed are invalid data. When the register is read and written, the register address is contained in the command (command frame), and when one byte is read and written, the address is automatically added by 1 to obtain the address of the next byte. The host can continuously read and write a plurality of registers of the slave device by keeping spi _ cs 0. The host can directly carry out operations of setting 1 and 0 or turning over and the like on a certain position of a certain register of the slave equipment by defining the command frame, and the operations of reading the register and writing back are not needed, so that the access time of the host to the slave equipment is effectively saved.

202. A first command frame for transmitting commands to the UWB baseband chip is acquired.

In this embodiment of the present application, before the UWB main control chip sends a command to the UWB baseband chip, a first command frame for transmitting the command to the UWB baseband chip needs to be obtained first, where the first command frame includes a configurable identification bit and a data byte. Specifically, the UWB main control chip may store the first command frame in advance or may acquire the first command frame according to an actual situation through network communication, which is not limited herein. The identification bits in the first command frame are configurable, the identification bits are different, and the control functions realized by the first command frame are different; and the data byte typically carries the data that needs to be transmitted.

It should be noted that the precedence relationship between step 201 and step 202 is not limited.

203. And configuring the identification bit of the first command frame to obtain a second command frame.

The UWB main control chip can configure the identification bit of the first command frame to obtain a second command frame; specifically, the UWB main control chip controls the UWB baseband chip according to actual needs, or when a register of the UWB baseband chip is read and written, the identifier of the first command frame may be configured as needed to obtain the second command frame. It is understood that the first command frame is an initial baseband control command and data, and the second command frame is a command frame to be transmitted configured based on the initial control command.

It is to be understood that the identification bits of the first command frame generally include: a byte flag bit, a read-write flag bit and a write mode bit; specifically, configuring the identification bit of the first command frame to obtain a second command frame includes: and respectively configuring the byte zone bit, the read-write zone bit and the write mode bit in the first command frame to obtain a second command frame. The byte flag bit generally realizes that the command frame is a single byte or double bytes, the read-write flag generally realizes that the command frame is a read register or a write register, and the write mode bit generally realizes different write functions when the command frame is a write register. It can be understood that the identification bits include not only byte flag bits, read-write flag bits, and write mode bits, but also register addresses, register address offsets, and the like, and in a specific configuration process of the first command frame, a plurality of second command frames can be obtained according to the configuration of the byte flag bits, the read-write flag bits, and the write mode bits, the register addresses, the register address offsets, and the like.

Further, the UWB main control chip may configure the byte flag bit in the first command frame into a double byte, and form a double byte register read-write command based on the double byte flag bit and the register address in the identification bit; configuring a reading and writing flag bit in a first command frame into reading operation; or, configuring the read-write flag bit in the first command frame as a write operation, and configuring the write mode bit as one of a normal write, an and operation, an or operation, and an xor operation. In one implementation, as shown in fig. 4 and 5, the byte flag bit is an AD bit, where an AD bit of 0 indicates that the frame is a single-byte command and an AD bit of 1 indicates that the frame is a double-byte command. It is understood that the AD bit being 1 may also indicate that the frame is a single-byte command, and the AD bit being 0 may also indicate that the frame is a double-byte command, which is not limited herein. The double byte command frame is a register address read/write command, and RW is a read/write flag bit. RW-0 indicates that the command is a read operation, and RW-1 indicates that the command is a write operation. M1 and M0 are write mode bits, 00 is normal write, and the write bytes are directly written into the registers of corresponding addresses; 01 is AND operation, AND operation is performed on the register value of the address directly corresponding to the byte, and the bit of 0 in the byte is cleared by 0 for the corresponding register bit; 10 is an OR operation, or the byte is directly OR' ed with the register value of the corresponding address, that is, a bit of 1 in the byte will set the corresponding register bit to 1; and 11 is an exclusive-or operation, the exclusive-or byte is directly exclusive-ored with the register of the corresponding address, and the bit of 1 in the exclusive-or byte is used for inverting the corresponding register bit. It is understood that, in the embodiment of the present application, the specific identifier in the byte flag bit, the read-write flag bit, and the write mode bit may be defined by itself, for example, RW ═ 0 may indicate that the command is a read operation or a write operation, and details are not described again. The number of bytes read and written in the read and write register frame is controlled by the signal spi _ cs. While spi _ cs remains 0, the host will continuously read and write the registers. And when one byte is read and written, the read-write address is automatically added with 1 until spi _ cs is 1, and the read-write operation is terminated.

Further, the UWB main control chip may configure the byte flag bit in the first command frame as a single byte to form a single byte command; and single-byte commands are generally divided into system commands and register read-write commands. When a single-byte command forms a single-byte register read-write command based on the register address offset in the identification bit, the UWB main control chip configures a read-write flag bit and a write mode bit into read operation; or, when the single-byte command is a single-byte register read-write command, configuring the read-write flag bit as a write operation, and configuring the write mode bit as one of a normal write, an and operation, an or operation, and an xor operation. In one implementation, as shown in FIG. 6, a single byte register read/write command is used to quickly read and write some registers, with 1 for RW, 0 for RW, and 0 for M1 for read. In the write operation, M1 and M0 indicate the write mode, similar to the above-mentioned double-byte command, and detailed description thereof is omitted here. The single byte register read/write command contains the offset of the address, and the actual register address is calculated by adding the offset to the last register address accessed. The master device (UWB master chip) accesses the registers of the different UWB baseband chips based on the register address. For example, when reading and writing the register a of the UWB baseband chip, the slave (UWB baseband chip) interface records the address of the register a. When accessing the register B of the slave device next time, if a single byte read-write command is used, the read-write address is calculated by adding an offset to the address of the register A. The offset is a signed number, and the offset is typically only 4 bits (including a sign bit), and thus can be located in a range of 8 words (i.e., 32 bytes) before and after the last read-write address. Therefore, if the addresses of the register accessed this time and the register accessed last time do not exceed 8 words, a single-byte read-write command can be used, and the time of 8 clock cycles is reduced.

Further, when the single-byte command forms a single-byte system command based on the system control command preconfigured in the identification bits, the UWB main control chip may configure the read-write flag bit and the write mode bit as control operations. The system control command may be a predefined system control code. In one implementation, as shown in fig. 7, RW is 0 and M1 is 1 representing a single-byte system command that is used to control the UWB baseband chip. The single byte system command has 4 bits, and can support 16 system commands. When the single-byte command is a single-byte system command and the single-byte command is greater than a predetermined number, the data bytes in the first command frame may be expanded into corresponding system command bits. The preset number is specific, and when the number of system commands is greater than 16, the system commands can be expanded by using a parameter 0, that is, the parameter 0 can also be a command. For example, the system command is 4 bits, which may define that when the command is 1111, this byte indicates that the command is to be extended, i.e. the next 1 byte or more may also indicate the command. The format of the specific following byte of the extended command may be user-defined. The single byte system command generally includes: pll: starting and stopping a system PLL; base address: the base address of the register to be read and written is defined, i.e. the subsequent parameter is the base address of the register. Since the baseband chip may have many modules, different modules may have different base addresses. When double bytes are read and written, the base address and the 12-bit address in the command are spliced into a real register address; and (3) testing: chip test commands, and other system commands.

204. And sending the second command frame to the UWB baseband chip through the data communication channel.

The UWB main control chip can send the second command frame to the UWB baseband chip through a data communication channel formed by the SPI interface so as to control the UWB baseband chip to carry out data interaction based on the identification bit and the data byte in the second command frame. It can be understood that the UWB baseband chip may recognize the second command frame, determine that the second command frame is a double-byte register read-write command, a single-byte system command, or a single-byte register read-write command according to the identification bit of the second command frame, and further perform data interaction with the UWB main control chip, so as to implement control of the UWB main control chip on the UWB baseband chip or read-write of the register.

Further, the UWB main control chip may determine a target UWB baseband chip from the plurality of UWB baseband chips based on a chip select signal in the chip select signal channel; when one master slave (one UWB master chip is connected with a plurality of UWB baseband chips), the master device can have a plurality of chip selection signals, and different UWB baseband chips are selected through different chip selection signals. It can be understood that the UWB main control chip can also select a certain UWB baseband chip through the command frame to respond to the subsequent command. When the target UWB baseband chip is determined, the UWB main control chip may send a second command frame to the target UWB baseband chip through the data input channel.

In the embodiment of the application, a second command frame is obtained by obtaining a first command frame used for transmitting a command to the UWB baseband chip and configuring an identification bit of the first command frame; and sending the second command frame to the UWB baseband chip so as to control the UWB baseband chip to carry out data interaction based on the identification bit and the data byte in the second command frame, thereby efficiently and flexibly realizing the control of the UWB baseband chip. Furthermore, the UWB main control chip can conveniently and efficiently configure and transmit data to the UWB baseband chip.

An embodiment of the present application further provides a UWB main control chip, as shown in fig. 8, including;

an establishing unit 801, configured to establish a data communication channel with a UWB baseband chip based on an SPI interface;

an obtaining unit 802, configured to obtain a first command frame for transmitting a command to the UWB baseband chip, where the first command frame includes a configurable identification bit and a data byte;

a configuration unit 803, configured to configure the flag of the first command frame to obtain a second command frame;

the control unit 804 is configured to send the second command frame to the UWB baseband chip through the data communication channel, so as to control the UWB baseband chip to perform data interaction based on the identification bits and the data bytes in the second command frame.

An embodiment of the present application further provides a UWB main control chip, as shown in fig. 9, including:

a central processing unit 901, a memory 902, an input/output interface 903, a wired or wireless network interface 904 and a power supply 905;

the memory 902 is a transient storage memory or a persistent storage memory;

the central processor 901 is configured to communicate with the memory 902, and execute the instruction operations in the memory 902 on the control plane functional entity to execute the control method described above.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application, which are essential or part of the technical solutions contributing to the prior art, or all or part of the technical solutions, may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like.

Claims

1. A control method of a UWB baseband chip is characterized by comprising the following steps:

obtaining a first command frame for transmitting a command to the UWB baseband chip, the first command frame comprising a configurable identification bit and a data byte;

2. The control method of claim 1, wherein the identification bits of the first command frame comprise: a byte flag bit, a read-write flag bit and a write mode bit;

3. The control method according to claim 2, wherein the separately configuring the byte flag bit, the read-write flag bit, and the write mode bit in the first command frame comprises:

configuring the byte flag bits in the first command frame as double bytes;

4. The control method according to claim 2, wherein the configuring the byte flag bit, the read-write flag bit, and the write mode bit in the first command frame respectively to obtain the second command frame comprises:

5. The control method according to claim 4, characterized in that the method further comprises:

6. The method of claim 1, wherein establishing a data communication channel with the UWB baseband chip based on the SPI interface comprises:

7. The control method according to claim 2, wherein the sending the second command frame to the UWB baseband chip through the data communication channel comprises:

8. A UWB master control chip is characterized by comprising;

9. An UWB master control chip, comprising:

the memory is a transient memory or a persistent memory;

the central processor is configured to communicate with the memory, the instructions in the memory operating on the control plane functional entity to perform the method of any of claims 1 to 7.

10. A computer-readable storage medium, comprising instructions which, when executed on a computer, cause the computer to perform the method of claims 1 to 7.