CN114914304A - LDMOS device with high ballast resistance, silicon controlled rectifier device and electronic equipment - Google Patents

LDMOS device with high ballast resistance, silicon controlled rectifier device and electronic equipment Download PDF

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Publication number
CN114914304A
CN114914304A CN202210485382.6A CN202210485382A CN114914304A CN 114914304 A CN114914304 A CN 114914304A CN 202210485382 A CN202210485382 A CN 202210485382A CN 114914304 A CN114914304 A CN 114914304A
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region
type body
source
injection region
contact hole
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陈伟
王强
朱小安
刘锡元
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Chongqing Anpaixin Microelectronics Co Ltd
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Chongqing Anpaixin Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/7404—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device
    • H01L29/742—Thyristor-type devices, e.g. having four-zone regenerative action structurally associated with at least one other device the device being a field effect transistor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses an LDMOS device with a high ballast resistor, a silicon controlled device and electronic equipment, wherein the LDMOS device with the high ballast resistor comprises: a semiconductor substrate; the P-type body region is formed in the semiconductor substrate; the N drift region is positioned inside the P-type body region; the source N injection region and the source P injection region are positioned inside the P type body region; the source N injection region is connected with the source P injection region; the drain N injection region is positioned in the N drift region; a first contact hole is formed in the surface of the adjacent position of the drain N injection region and the N drift region; a second contact hole is formed in one side face, away from the P-type body region, of the position, adjacent to the source N injection region and the source P injection region; the first contact hole and the second contact hole are used for accessing electric energy and form a current channel with the P-type body region and the N drift region. The technical scheme of the invention solves the problem of poor ESD capability of the LDMOS device.

Description

LDMOS device with high ballast resistance, silicon controlled rectifier device and electronic equipment
Technical Field
The invention relates to the field of electronic science and technology, in particular to an LDMOS device with a high ballast resistor, a silicon controlled device and electronic equipment.
Background
LDMOS, i.e., lateral double-diffused metal-oxide-semiconductor device, is widely used in various power conversion applications, such as motor drives, switching power supplies, power conversion, etc. However, the LDMOS has an excessively long drift region, and a large base region widening effect is caused after an ESD pulse enters from the drain of the LDMOS, thereby causing non-uniformity of current distribution. Due to the unreasonable device structure, the ESD capability of the LDMOS device is very poor.
Disclosure of Invention
The invention mainly aims to provide an LDMOS device with a high ballast resistor, a silicon controlled device and electronic equipment, and aims to solve the problem that the ESD capability of the LDMOS device is poor.
In order to achieve the above object, the present invention provides an LDMOS device with high ballast resistance, which includes:
a semiconductor substrate;
the P-type body region is formed in the semiconductor substrate;
the N drift region is positioned inside the P-type body region;
a source N injection region and a source P injection region located inside the P type body region; the source N injection region is connected with the source P injection region;
the drain N injection region is positioned inside the N drift region;
a first contact hole is formed in the surface of the adjacent position of the drain N injection region and the N drift region;
a second contact hole is formed in one side face, away from the P-type body region, of the position, adjacent to the source N injection region and the source P injection region;
the first contact hole and the second contact hole are used for accessing electric energy and form a current channel with the P-type body region and the N drift region.
Optionally, the LDMOS device with high ballast resistance further includes:
a field oxide layer located on the surface of the N drift region and the surface of the P-type body region.
Optionally, the LDMOS device with high ballast resistance further includes:
and the gate oxide layer covers the surface of the channel of the P-type body region.
Optionally, the LDMOS device with high ballast resistance further includes:
and the polysilicon grid is positioned above the gate oxide layer.
Optionally, the LDMOS device with high ballast resistance further includes:
the anode metal covers the first contact hole;
and the cathode metal covers the second contact hole.
Optionally, the LDMOS device with high ballast resistance further includes:
the passivation layer is positioned on the surface of the LDMOS device with the high ballast resistance.
The invention also provides a thyristor device with a high ballast resistor, which comprises:
a semiconductor substrate;
the P-type body region is formed in the semiconductor substrate;
the N drift region is positioned inside the P-type body region;
a source N injection region and a source P injection region located inside the P type body region; the source N injection region is connected with the source P injection region;
the anode N injection region and the anode P injection region are positioned in the N drift region; the anode N injection region is connected with the anode P injection region;
a first contact hole is formed in the surface of the anode N injection region adjacent to the anode P injection region;
a second contact hole is formed in one side face, away from the P-type body region, of the position, adjacent to the source N injection region and the source P injection region;
the first contact hole and the second contact hole are used for accessing electric energy and form a current channel with the P-type body region and the N drift region.
Optionally, the high ballast resistance thyristor device further comprises:
a cross-over N-type implanted region located within the N-drift region and adjacent to the interior of the P-type body region;
a field oxide layer on a surface of the N drift region and a surface of the P-type body region;
the gate oxide layer covers the surface of the channel of the P-type body region;
the polysilicon grid is positioned above the gate oxide layer;
the anode metal covers the first contact hole;
the cathode metal covers the second contact hole;
the passivation layer is positioned on the surface of the LDMOS device with the high ballast resistance.
The invention also provides an electronic device comprising the high-ballast-resistance LDMOS device or the high-ballast-resistance SCR device.
The technical scheme of the invention is that a semiconductor substrate, a P-type body region, an N drift region, a drain N injection region, a source N injection region and a source P injection region are arranged in an LDMOS device; a first contact hole is formed in the surface of the adjacent position of the drain N injection region and the N drift region, and a second contact hole is formed in one side surface, away from the P-type body region, of the adjacent position of the source N injection region and the source P injection region; two current paths are formed when current flows from the first contact hole to the second contact hole through the P-type body region and the N drift region, and a higher ballast resistor can be formed, so that the ESD capacity of the LDMOS device is improved. The invention solves the problem of poor ESD capability of the LDMOS device.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a cross-sectional view of an exemplary embodiment of a high ballast resistance LDMOS device of the present invention;
FIG. 2 is a cross-sectional view of a conventional LDMOS device;
fig. 3 is a cross-sectional view of an embodiment of the thyristor device with high ballast resistance according to the invention.
The reference numbers illustrate:
reference numerals Name (R) Reference numerals Name (R)
a First contact hole 11 N drift region
b Second contact hole 12 P-type body region
01 N-implanted region of drain 21 Field oxide layer
02 Source N implant region 22 Gate oxide layer
03 Source P implanted region 31 Polysilicon grid
04 Anode N implanted region 41 Anodic metal
05 Anode P implanted region 42 Cathode metal
06 Bridging N implant regions 51 Passivation layer
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that, if directional indications (such as up, down, left, right, front, and back … …) are involved in the embodiment of the present invention, the directional indications are only used to explain the relative positional relationship between the components, the movement situation, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indications are changed accordingly.
In addition, if there is a description of "first", "second", etc. in an embodiment of the present invention, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The invention provides an LDMOS device with a high ballast resistor, a silicon controlled device and electronic equipment.
Currently, LDMOS, i.e. lateral double diffused metal-oxide-semiconductor device, is widely used in various power conversion situations, such as motor drive, switching power supply, power conversion, etc. However, because the LDMOS has an excessively long drift region, a large base region extension effect is caused after an ESD pulse enters from the drain of the LDMOS, that is, when a carrier crosses a potential barrier region at a certain concentration and a certain speed, the charge of the carrier affects the electric field distribution in the potential barrier region, and one of important consequences is that when the current is large, the neutral base region becomes wide, and the base region extension effect causes the nonuniformity of the current distribution.
The structure of the conventional LDMOS device is shown in fig. 2, in which a gate is connected to a source and Bulk potential is also equal to the source for convenience of ESD analysis. When their voltage-resistant junctions are broken down, they tend to be very powerful (bipolar devices operate mainly on minority carriers) due to the large bipolar injection effect, i.e. in the small case the minority carriers are very small, but since they can form a large concentration gradient, a large current can be generated. However, in the case of large injections, it is no longer possible to distinguish between minority and majority carriers, which both have the same effect on the conduction. Some phenomena or effects due to the large implant occur, namely the effect of the large implant. The large bipolar injection effect causes a severe base extension effect, which causes current to be severely concentrated in the region shown in fig. 1, resulting in a current crowding effect, which causes local burnout and ultimately failure.
Referring to fig. 1, in an embodiment of the invention, the LDMOS device with high ballast resistance includes:
a semiconductor substrate;
a P-type body region 12 formed within the semiconductor substrate;
an N drift region 11, the N drift region 11 being located inside the P-type body region 12;
a source N implant region 02 and a source P implant region 03 located inside the P-type body region 12; the source N injection region 02 is connected with the source P injection region 03;
a drain N injection region 01, wherein the drain N injection region 01 is positioned inside the N drift region 11;
a first contact hole a is formed in the surface of the adjacent position of the drain N injection region 01 and the N drift region 11;
a second contact hole b is formed in one side surface, away from the P-type body region 12, of the position, adjacent to the source N injection region 02 and the source P injection region 03;
the first contact hole a and the second contact hole b are used for accessing electric energy and form a current channel with the P-type body region 12 and the N drift region 11.
In the embodiment, an LDMOS device is specifically described, an original standard contact hole design is abandoned for an LDMOS device structure composed of a semiconductor substrate, a P-type body region 12, an N drift region 11, a source N injection region 02, a source P injection region 03, and a drain N injection region 01, a first contact hole a is arranged on a side surface of the source N injection region 02 adjacent to the source P injection region 03 and away from the P-type body region 12, and the first contact hole a is in contact with a non-ohmic contact region, so that a higher ballast resistance and a first ESD current path are formed, the non-ohmic contact region is an adjacent surface on the left side of the N drift region 11 and the drain N injection region 01, and current distribution of the device in an ESD state is improved.
It can be understood that when an ESD voltage much higher than the breakdown voltage appears on the drain, the parasitic NPN structure in the LDMOS will be turned on quickly, the source thereof will inject electrons into the drain, and the surface flux will be much smaller than the body flux in the drain N injection region 01 or the source N injection region 02 because the surface ballast resistor is larger than the body ballast resistor, thereby avoiding the current crowding effect and improving the ESD capability. On the other hand, when the large implantation occurs, the N drift region 11 becomes a high concentration neutral region which is not resistant to voltage, and at this time, the first contact hole a portion can form ohmic contact although there is no N implantation, that is, non-rectifying contact can be formed when metal is in contact with semiconductor, and the formed ohmic contact increases the second ESD current path, which is beneficial to improving ESD capability.
Further, the first ESD current path enables current to be output to the drain N injection region 01 through a first contact hole a formed on a surface of the adjacent position of the drain N injection region 01 and the N drift region 11, then output to the P-type body region 12 through the N drift region 11 by the drain N injection region 01, and output through a second contact hole b formed on a side surface of the adjacent position of the source N injection region 02 and the source P injection region 03 away from the P-type body region 12; the second ESD current path enables current to be directly output to the N drift region 11 through a first contact hole a formed in the surface of the adjacent position of the drain N injection region 01 and the N drift region 11, then output to the P-type body region 12 through the N drift region 11, and output through a second contact hole b formed in a side surface, away from the P-type body region 12, of the adjacent position of the source N injection region 02 and the source P injection region 03; the current in the original LDMOS device can only be output to the drain N injection region 01 through the contact hole, then is output to the P-type body region 12 from the drain N injection region 01 through the N drift region 11, and is output through the contact holes above the source N injection region 02 and the source P injection region 03 in the P-type body region 12; in the scheme, the output currents of the two paths are compared with the original path, and the ESD capability can be remarkably improved.
After the contact holes above the source electrode and the drain electrode are specially designed in a non-standard way, the maximization of the ballast resistance of the LDMOS device is realized, the most common method for forming the ballast resistance is to form a layer of non-silicide resistance between the drain region and the grid electrode through a silicide mask layer, silicide is not formed in a part of the region between the drain electrode N injection region 01 and the polysilicon grid electrode 31, and silicide is not formed in a part of the region between the source electrode N injection region 02 and the source electrode P injection region 03 and the polysilicon grid electrode 31, so that the ballast resistance is formed, the design of the first contact hole a and the second contact hole b in the scheme is farther away from the polysilicon grid electrode 31 compared with the contact holes in the existing LDMOS device, so that higher ballast resistance is formed, the ESD performance of the LDMOS device is well improved without adding any additional process flow, and meanwhile, through a conductance modulation principle, the contact resistance of the device under the condition of high-current injection is reduced, and the key effect on improving the ESD (electro-static discharge) capability of the LDMOS is achieved; ESD capability, i.e., electrostatic discharge capability; the principle of conductance modulation, i.e. under large injection conditions, minority carrier concentration increases and, due to the requirement of electrical neutrality, majority carrier concentration increases equally. As the concentration of the majority carriers increases, the base resistivity will be reduced, thereby creating a base conductance modulation effect in which the base conductivity is modulated by the injection current.
The technical scheme of the invention is that a semiconductor substrate, a P type body region 12, an N drift region 11, a drain N injection region 01, a source N injection region 02 and a source P injection region 03 are arranged in an LDMOS device; a first contact hole a is formed in the surface of the adjacent position of the drain N injection region 01 and the N drift region 11, and a second contact hole b is formed in one side surface, away from the P type body region 12, of the adjacent position of the source N injection region 02 and the source P injection region 03; two current paths are formed when current flows from the first contact hole a to the second contact hole b through the P type body region 12 and the N drift region 11, and a higher ballast resistor can be formed through the special position design of the first contact hole a and the second contact hole b, so that the ESD capacity of the LDMOS device is improved. The invention solves the problem of poor ESD capability of the LDMOS device.
Referring to fig. 1, in an embodiment, the LDMOS device with high ballast resistance further includes:
a field oxide layer 21, the field oxide layer 21 being located on a surface of the N drift region 11 and a surface of the P type body region 12.
In this embodiment, the field oxide layer 21 is disposed on the surface of the N drift region 11 and the surface of the P-type body region 12, the field oxide layer 21 is a very thick oxide layer, and is located in a region where a transistor and an electrode are not in contact on a chip, and can play a role of isolating the transistor, the active region and the field region are complementary, the transistor is disposed at the active region, a plurality of metal and polysilicon connecting wires are disposed on the field region, and the field region (i.e., the region outside the transistor) in the LDMOS process needs a thick oxide layer, so as to increase the field turn-on voltage to be higher than the operating voltage, thereby forming a good isolation; while reducing the parasitic capacitance between the metal layer or polysilicon and the silicon substrate. However, the requirement for field turn-on cannot be met only by increasing the thickness of the field oxide (that is, the requirement that the field cannot be turned on when the device normally works) and the field region is implanted to increase the doping concentration of the field region, prevent the generation of a channel and further improve the turn-on voltage. In this embodiment, the field oxide layer 21 is provided, so that generation of a channel can be prevented, and the turn-on voltage can be further increased.
Referring to fig. 1, in an embodiment, the LDMOS device with high ballast resistance further includes:
and the gate oxide layer 22 is covered on the surface of the channel of the P-type body region 12.
In this embodiment, the gate oxide layer 22 may be used to suppress the short channel effect and maintain a good subthreshold slope; to achieve this, the gate oxide layer 22 thickness is reduced in the same proportion as the channel length. For example, for a 0.1 μm scale CMOS device, the gate oxide layer 22 needs to be about 3nm thick. The biggest problem with ultra-thin oxide layers is the occurrence of quantum tunneling punch-through. The tunneling current of the gate oxide layer 22 will increase exponentially with the decrease of the thickness of the oxide layer, and if the thickness of the oxide layer is reduced from 3.6nm to 1.5nm at a gate bias voltage of 1.5V, the gate current density will increase by 10 orders of magnitude more than ever. The present embodiment can suppress the short channel effect by covering the gate oxide layer 22 on the channel surface of the P-type body region 12.
Referring to fig. 1, in an embodiment, the LDMOS device with high ballast resistance further includes:
a polysilicon gate 31, said polysilicon gate 31 being located above said gate oxide layer 22.
In this embodiment, the polysilicon gate 31 is disposed above the gate oxide layer 22, the polysilicon gate is a common sandwich gate structure in the metal oxide semiconductor, a layer of polysilicon is distributed on the surface of the silicon oxide, a layer of non-fusible metal layer is further covered on the surface of the polysilicon, and the polysilicon (polysilicon): with many short range ordered crystals but an overall disordered silicon structure. The polysilicon gate 31 is provided to enable the LDMOS to have a triggered switch, and in this embodiment, if necessary, a resistor may be connected in series between the polysilicon gates 31 to increase the triggering speed. The present embodiment arranges the polysilicon gate 31 above the gate oxide 22 for turning on the LDMOS device when triggered.
Referring to fig. 1, in an embodiment, the LDMOS device with high ballast resistance further includes:
the anode metal 41, wherein the anode metal 41 covers the first contact hole a;
and the cathode metal 42, wherein the cathode metal 42 covers the second contact hole b.
In this embodiment, the anode metal 41 and the cathode metal 42 cover the contact holes, and the anode metal 41 and the cathode metal 42 serve as conductive media to enable current to be output to the drain N injection region 01 in the LDMOS device through the first contact hole a, then output from the drain N injection region 01 to the P-type body region 12 through the N drift region 11, and output through the second contact hole b arranged on a side surface away from the P-type body region 12, where the source N injection region 02 and the source P injection region 03 are adjacent to each other. The present embodiment forms a complete current path by covering the anode metal 41 and the cathode metal 42 on the first contact hole a and the second contact hole b.
Referring to fig. 1, in an embodiment, the LDMOS device with high ballast resistance further includes:
and the passivation layer 51, wherein the passivation layer 51 is positioned on the surface of the LDMOS device with the high ballast resistance.
In this embodiment, the passivation region is a stable region where a protective oxide film is formed on the metal surface, and has the characteristics of compactness and adherence, and the passivation layer 51 disposed on the uppermost layer of the LDMOS device can protect the LDMOS device and prevent the internal structure of the semiconductor from being damaged due to the impurities in the external environment entering the semiconductor. The present embodiment protects the semiconductor by providing a passivation layer 51 on the surface of the LDMOS device.
The invention also provides a silicon controlled rectifier device with high ballast resistance.
Referring to fig. 3, in an embodiment, the high ballast resistance thyristor device includes:
a semiconductor substrate;
a P-type body region 12 formed within the semiconductor substrate;
an N drift region 11, the N drift region 11 being located inside the P-type body region 12;
a source N implant region 02 and a source P implant region 03 located inside the P-type body region 12; the source N injection region 02 is connected with the source P injection region 03;
an anode N injection region 04 and an anode P injection region 05, wherein the anode N injection region 04 and the anode P injection region 05 are located inside the N drift region 11; the anode N injection region 04 is connected with the anode P injection region 05;
a first contact hole a is formed in the surface of the anode N injection region 04 adjacent to the anode P injection region 05;
a second contact hole b is formed in one side surface, away from the P-type body region 12, of the position, adjacent to the source N injection region 02 and the source P injection region 03;
the first contact hole a and the second contact hole b are used for accessing electric energy and form a current channel with the P-type body region 12 and the N drift region 11.
In this embodiment, a thyristor device is specifically described, an anode N injection region 04 and an anode P injection region 05 are arranged in an N drift region 11 of the thyristor device, a first contact hole a is formed in a surface of the anode N injection region 04 adjacent to the anode P injection region 05, and the rest of the structure is consistent with that of the LDMOS device with a high ballast resistance in the above embodiment, so that in this embodiment, current can be output to the anode N injection region 04 and the anode P injection region 05 through the first contact hole a, then output to a P body region 12 through the N drift region 11, and output through a second contact hole b arranged on a side surface away from the P body region 12 adjacent to a source N injection region 02 and a source P injection region 03; therefore, two current paths can be provided, and compared with the original one current path, the ESD (electro-static discharge) capability of the controllable silicon can be remarkably improved.
In the silicon controlled device, the drain N injection region 01 inside the N drift region 11 in the above embodiments is replaced by the anode N injection region 04 and the anode P injection region 05 to form two current paths, so as to improve the ESD capability of the silicon controlled device.
Referring to fig. 3, in an embodiment, the high ballast resistance thyristor device further includes:
a cross-over N-implant region 06 within the N-drift region 11 adjacent to the P-type body region 12;
a field oxide layer 21, the field oxide layer 21 being located on a surface of the N drift region 11 and a surface of the P-type body region 12;
the gate oxide layer 22, the gate oxide layer 22 covers the surface of the channel of the P-type body region 12;
a polysilicon gate 31, said polysilicon gate 31 being located above said gate oxide layer 22;
the anode metal 41, wherein the anode metal 41 covers the first contact hole a;
the cathode metal 42, the said cathode metal 42 covers on the said second contact hole b;
and the passivation layer 51 is positioned on the surface of the thyristor device with the high ballast resistance, and the passivation layer 51 is positioned on the surface of the thyristor device with the high ballast resistance.
In this embodiment, on the basis of the above-mentioned embodiment regarding the thyristor device, a cross-over N injection region 06 is added to the adjacent position inside the N drift region 11 and inside the P-type body region 12 of the thyristor, and the BV, i.e., the breakdown voltage, can be effectively reduced by adding the cross-over N injection region 06, and the other structures, such as the field oxide layer 21, the gate oxide layer 22, the polysilicon gate 31, the anode metal 41, the cathode metal 42, and the passivation layer 51, are the same as those of the LDMOS device with high ballast resistance in the above-mentioned embodiment, so that a low trigger voltage thyristor structure (LVTSCR) with ballast resistance is formed; compared with the original silicon controlled rectifier, the low-trigger-voltage silicon controlled rectifier structure with the ballast resistor has stronger ESD capability and is not easy to burn out under the condition that large current passes through. In the embodiment, a cross-over N injection region 06 is added at the adjacent position between the inside of an N drift region 11 and the inside of a P type body region 12 of the silicon controlled rectifier to form the silicon controlled rectifier with low trigger voltage, so that the silicon controlled rectifier is not easy to burn out.
The invention further provides the electronic equipment.
In an embodiment, the electronic device includes the LDMOS device with a high ballast resistor or the thyristor device with a high ballast resistor as described above, and the specific structure of the LDMOS device with a high ballast resistor or the thyristor device with a high ballast resistor refers to the above embodiments.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents made by the contents of the specification and drawings or directly/indirectly applied to other related technical fields under the technical spirit of the present invention are included in the scope of the present invention.

Claims (9)

1. A high ballast resistance LDMOS device, comprising:
a semiconductor substrate;
the P-type body region is formed in the semiconductor substrate;
the N drift region is positioned inside the P-type body region;
a source N injection region and a source P injection region located inside the P type body region; the source N injection region is connected with the source P injection region;
the drain N injection region is positioned inside the N drift region;
a first contact hole is formed in the surface of the adjacent position of the drain N injection region and the N drift region;
a second contact hole is formed in one side face, away from the P-type body region, of the position, adjacent to the source N injection region and the source P injection region;
the first contact hole and the second contact hole are used for accessing electric energy and form a current channel with the P-type body region and the N drift region.
2. The high ballast resistance LDMOS device set forth in claim 1 further including:
a field oxide layer located on the surface of the N drift region and the surface of the P-type body region.
3. The high ballast resistance LDMOS device set forth in claim 2 further including:
and the gate oxide layer covers the surface of the channel of the P-type body region.
4. The high ballast resistance LDMOS device set forth in claim 3 further including:
and the polysilicon grid is positioned above the gate oxide layer.
5. The high ballast resistance LDMOS device set forth in claim 4 further including:
the anode metal covers the first contact hole;
and the cathode metal covers the second contact hole.
6. The high ballast resistance LDMOS device of any of claims 1-5, further comprising:
the passivation layer is positioned on the surface of the LDMOS device with the high ballast resistance.
7. A thyristor device with high ballast resistance, comprising:
a semiconductor substrate;
the P-type body region is formed in the semiconductor substrate;
the N drift region is positioned inside the P-type body region;
a source N injection region and a source P injection region located inside the P type body region; the source N injection region is connected with the source P injection region;
the anode N injection region and the anode P injection region are positioned in the N drift region; the anode N injection region is connected with the anode P injection region;
a first contact hole is formed in the surface of the anode N injection region, which is adjacent to the anode P injection region;
a second contact hole is formed in one side face, away from the P-type body region, of the position, adjacent to the source N injection region and the source P injection region;
the first contact hole and the second contact hole are used for accessing electric energy and form a current channel with the P-type body region and the N drift region.
8. The high ballast resistance thyristor device of claim 7, further comprising:
a cross-over N-type implanted region located within the N-drift region and adjacent to the interior of the P-type body region;
a field oxide layer on a surface of the N drift region and a surface of the P-type body region;
the gate oxide layer covers the surface of the channel of the P-type body region;
the polysilicon grid is positioned above the gate oxide layer;
the anode metal covers the first contact hole;
the cathode metal covers the second contact hole;
and the passivation layer is positioned on the surface of the silicon controlled device with the high ballast resistance.
9. An electronic device, characterized in that the electronic device comprises the high ballast resistance LDMOS device as claimed in any one of claims 1 to 6 or the high ballast resistance thyristor device as claimed in any one of claims 7 to 8.
CN202210485382.6A 2022-05-06 2022-05-06 LDMOS device with high ballast resistance, silicon controlled rectifier device and electronic equipment Pending CN114914304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210485382.6A CN114914304A (en) 2022-05-06 2022-05-06 LDMOS device with high ballast resistance, silicon controlled rectifier device and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210485382.6A CN114914304A (en) 2022-05-06 2022-05-06 LDMOS device with high ballast resistance, silicon controlled rectifier device and electronic equipment

Publications (1)

Publication Number Publication Date
CN114914304A true CN114914304A (en) 2022-08-16

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