CN114912408B

CN114912408B - Layout modification verification quick iteration method based on local DRC

Info

Publication number: CN114912408B
Application number: CN202210473291.0A
Authority: CN
Inventors: 廖文骏; 李志梁; 刘艳霞
Original assignee: Beijing Empyrean Technology Co Ltd
Current assignee: Beijing Empyrean Technology Co Ltd
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2024-07-26
Anticipated expiration: 2042-04-29
Also published as: CN114912408A

Abstract

A layout modification verification quick iteration method based on local DRC comprises the following steps: screening the local layout information and the corresponding part rules modified each time, and carrying out local DRC; performing layout screening on the local DRC through a layering mode or a regional mode; the result obtained from each partial DRC is fed back to the original DRC result, and the modified result is removed. The layout modification verification rapid iteration method based on the local DRC can greatly reduce the time and the memory expense for DRC iteration and improve the layout modification efficiency.

Description

Layout modification verification quick iteration method based on local DRC

Technical Field

The invention relates to the technical field of semiconductor integrated circuit design automation, in particular to a layout modification verification rapid iteration method based on a local DRC (Partial DRC).

Background

The layout design must conform to the corresponding DRC (Design Rule Check ) rules. After the engineer verifies the layout, the engineer obtains various Results (DRC Results) of the layout violating DRC rules (DRC Rule), and then needs to modify the layout content related to the DRC Results in order to meet the requirement of passing the design Rule check (DRC Pass).

For traditional DRC iteration, after each time or each stage of modification of the layout, the engineer needs to re-perform DRC verification on the whole layout, and manually check whether the previously modified Rule and graph meet the requirements. For complex DRC Rule for large-scale layout and small-scale processes, the number of results of the preliminary DRC verification can be enormous. If the DRC verification is repeated after each stage of modification is completed, a lot of time is consumed and the overhead on system resources such as CPU, memory and the like is huge.

Disclosure of Invention

In order to solve the defects existing in the prior art, the invention aims to provide a layout modification verification rapid iteration method based on local DRC, which can greatly reduce the time and memory expense for DRC iteration and improve the layout modification efficiency.

In order to achieve the above object, the present invention provides a layout modification verification fast iteration method based on local DRC, including the steps of:

Screening the local layout information and the corresponding part rules modified each time, and carrying out local DRC;

performing layout screening on the local DRC through a layering mode or a regional mode;

The result obtained from each partial DRC is fed back to the original DRC result, and the modified result is removed.

Further, the step of filtering the local layout information and the corresponding partial rules for each modification and performing the local DRC, further comprises,

Performing complete DRC on the original layout to obtain an original design rule checking result;

and carrying out layout modification according to the original design rule checking result to obtain a modified layout.

Further, the step of performing layout screening on the local DRC by using a hierarchical mode or a regional mode, further comprises,

Calling a layering mode, and obtaining a difference layer of the original layout and the modified layout through layout comparison;

and extracting the content related to the difference layers in a rule file which is required to meet the condition of the recorded layout as a local rule, and extracting all layers related to the local rule in the modified layout to form the local layout.

Calling a region mode, and selecting a difference region from the modified layout;

processing the difference area to obtain all patterns contacted with the difference area to form a local layout;

DRC rules related to all layers of the local layout are extracted as local rules.

Further, the step of feeding back the result obtained for each partial DRC into the original DRC result, removing the result of modification passing, further comprises,

And carrying out local DRC on the local layout according to the local rule to obtain a local checking result.

Further, the method also comprises the steps of,

And for the layering mode, combining a local inspection result and an original design rule inspection result, and for rule inspection contained in both the local inspection result and the original design rule inspection result, replacing the corresponding result of the original design rule inspection result with the result of the local inspection result, taking the new inspection result as the original design rule inspection result after the replacement is completed, and participating in the next iteration.

Further, the method also comprises the steps of,

Combining a local inspection result and an original design rule inspection result for a region mode, and sequentially traversing all result graphs of the rule, which is positioned in a difference region, in the original design rule inspection result for rule inspection contained in the local inspection result and the original design rule inspection result, and removing the result from the original design rule inspection result when the graph is not contacted with any graph in the rule corresponding to the local inspection result;

And traversing all graphs in the local inspection results in sequence, and if the graphs cannot be completely overlapped with any graph in the original design rule inspection results, adding the graphs into the original design rule inspection results to form new original design rule inspection results, and participating in the next iteration.

Still further, the step of feeding back the result obtained for each partial DRC into the original DRC result, removing the result of modification passing, further comprises,

Defining the modified layout as the original layout of the next iteration;

And performing local DRC iteration until the original design rule check result is null or the specified design requirement is met, and ending the iteration.

In order to achieve the above object, the present invention further provides an electronic device, including a memory and a processor, where the memory stores a program running on the processor, and the processor executes the steps of the local DRC-based layout modification verification fast iteration method described above when running the program.

To achieve the above object, the present invention also provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the local DRC-based layout modification verification fast iteration method described above.

The layout modification verification rapid iteration method based on the local DRC has the following beneficial effects:

1) The complex DRC of large-scale layouts and small-scale processes can be very large in number of results, and DRC run time is long and system occupancy is high.

2) The method carries out targeted quick local DRC on each layout modification, and automatically combines DRC results, thereby avoiding huge time cost and system cost of traditional DRC iteration.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:

FIG. 1 is a flow chart of a local DRC-based layout modification verification fast iteration method of the present invention;

FIG. 2 is a schematic diagram of a Layer Mode iteration process according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a Region Mode iteration process according to an embodiment of the present invention;

FIG. 4 is an Original Layout diagram according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an Origin DB according to an embodiment of the present invention;

FIG. 6 is an iterative diagram using Layer Mode according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of DRC_db automatically updated after one iteration using Layer Mode according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of an iteration using Region Mode according to an embodiment of the present invention;

Fig. 9 is a schematic diagram of drcdb automatically updated after iteration using Region Mode according to an embodiment of the present invention.

Detailed Description

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings, it being understood that the preferred embodiments described herein are for illustration and explanation of the present invention only, and are not intended to limit the present invention.

Example 1

FIG. 1 is a flow chart of a local DRC-based layout modification verification quick iteration method according to the present invention, and the local DRC-based layout modification verification quick iteration method of the present invention will be described in detail with reference to FIG. 1.

In step 101, the local layout information and corresponding part Rule related to each modification are automatically screened, and targeted local DRC is performed. In this step, the local DRC is "partial" in the layer, is "local" in the layout, and is "selective" in the DRC Rule, so that the local DRC is fast and the resource consumption is low.

Preferably, the user performs Full DRC on the Original Layout (Original DRC) to obtain an Original DRC Result (Original DB), and defines Original Layout as layout_before and Original DB as drc_db.

In this embodiment, drc_db is a DRC result file, and specific information of violating DRC Rule in the layout is recorded.

Preferably, the user modifies the Layout according to drc_db to obtain a modified Layout Rev Layout, which is defined as layout_after.

In step 102, the local DRC performs layout screening in a Layer Mode or Region Mode.

Preferably, layer Mode is a fully automatic process, and Layer Mode judges the Layer involved in modification through LVL (Layout vs. Layout contrast) and automatically completes t partial DRC input content (including Layout and Rule) screening.

Preferably, layer Mode is invoked: the Layer Mode obtains the difference Layer (Bias Layer) between the layout_before and layout_after by the auto LVL.

Preferably, content (including definition, connection relation, calculation, rule Check, and the like) related to Bias layers in DRC Rule File (Rule File required to satisfy the condition for recording the Layout) is extracted as a Partial Rule, and all layers related to the Partial Rule in the layout_after are extracted to constitute a Partial Layout.

Preferably, region Mode is a manual Mode, and the user determines the local DRC Input content (including layout and Rule) by manual framing.

Preferably, region Mode is invoked, at which point the user selects a Region (Box or Polygon shape) in the Layout of layout_after, i.e., bias Region.

Preferably, bias regions are processed to obtain all patterns in contact with the Region, and Partial Layout is formed; DRC Rule (including definition, connection relation, calculation, rule Check, etc.) related to all layers of the Partial Layout is extracted as a Partial Rule.

Preferably, one of the Layer Mode or Region Mode modes is selected for layout screening, and only one of the Layer Mode or Region Mode modes can be selected in each iteration process.

In step 103, the result from each partial DRC is automatically fed back into the original DRC result, and the modified Pass result is automatically removed. In the step, whether the layout is compliant (accords with DRC Rule) is judged, and when the DRC result is 0, the full accord with the DRC Rule is indicated, so that complicated manual comparison judgment can be avoided.

Preferably, partial Layout is DRC (Partial DRC) by Partial Rule, and the result obtained is Partial DB (partial_db).

Preferably, for the Layer Mode, partial_db and drc_db are combined, for the Rule Check contained in both dbs: and replacing the corresponding result of the DRC_db with the result of the partial_db, and taking the new db as the DRC_db to participate in the next iteration after the replacement is completed.

Preferably, for the Region Mode, partial_db and drc_db are combined, for Rule Check contained in both dbs: sequentially traversing and checking all result graphs of the Rule positioned in the Bias Region in the DRC_db, and removing the result from the DRC_db when the graph is not contacted with any graph in the Rule corresponding to the partial_db; traversing all graphs in the partial_db in sequence, and adding the graphs into the DRC_db if the graphs cannot completely coincide with any graph in the DRC_db; and finally forming a new DRC_db to participate in the next iteration.

Preferably, layouafter is defined as Layoubefore for the next round of iterations.

Preferably, one of the Layer Mode or Region Mode modes is selected for iteration, and only one of the Layer Mode or Region Mode modes can be selected in each iteration process.

The above-described partial DRC iterations are preferably performed multiple times until all DRC results are removed (drc_db is empty or a specified design requirement is reached), and the iteration ends.

Example 2

Fig. 2 is a schematic view of a Layer Mode iteration process according to an embodiment of the present invention, as shown in fig. 2, the Layer Mode iteration process is as follows:

Step 1: starting. Turning to step 2.

Step 2: and (5) performing Full DRC to obtain DRC_db. Turning to step 3.

Step 3: and the user carries out Layout modification according to the layout_before and the DRC_db to obtain the layout_after. Turning to step 4.

Step 4: LVL is carried out on the Layout_before and Layout_after to obtain Bias Layer. Turning to step 5.

Step 5: extracting the DRC Rule according to the Bias Layer to obtain the Partial Rule. Turning to step 6.

Step 6: and extracting the Layout_after according to the Partial Rule to obtain the Partial Layout. Turning to step 7.

Step 7: and carrying out Partial DRC on the Partial Layout according to the Partial Rule to obtain the partial_db. Turning to step 8.

Step 8: and combining the DRC_db and the partial_db to obtain the NEW DB.

Step 9: the user judges whether the NEW DB results meet the requirements, if so, the step 10 is carried out; if not, then NEW DB replaces DRC_db and Layout_after replaces Layout_before, and step 3 is repeated (step 3 of the Region Mode diagram is also repeated).

Step 10: and (5) ending.

Example 3

Fig. 3 is a schematic diagram of a Region Mode iteration process according to an embodiment of the present invention, as shown in fig. 3, the Region Mode iteration process is as follows:

The Region Mode iteration flow is as follows:

Step 1: starting. Turning to step 2.

Step 2: and (5) performing Full DRC to obtain DRC_db. Turning to step 3.

Step 4: the user performs region selection on the Layout Layout_after, and the Partial Layout is obtained through the processing of the tool (method).

Step 5: extracting DRC Rule according to Partial Layout involving layer to obtain Partial Rule. Turning to step 6.

Step 6: and carrying out Partial DRC on the Partial Layout according to the Partial Rule to obtain the partial_db. Turning to step 7.

Step 7: and combining the DRC_db and the partial_db to obtain the NEW DB.

Step 8: the user judges whether the NEW DB results meet the requirements, if so, the step 9 is carried out; if not, the NEW DB replaces DRC_db, the Layout_after replaces Layout_before, and step 3 is repeated (step 3 of the Layer Mode diagram is also repeated).

Step 9: and (5) ending.

Example 4

Fig. 4 is a schematic diagram of an Original Layout, as shown in fig. 4, named test. FULL DRC was performed with a DRC. Rule containing 3 DRC rules: RULE1 check POLY linewidth is less than 3um, RULE2 check GATE spacing is less than 1.5um, RULE3 check GATE2 spacing is less than 1.5um. DRC results are shown in fig. 5.

After the user makes adjustments to the GATE2 layer, the new layout is rev1.Gds. Layer Mode is selected for iteration as shown in fig. 6.

The Layer Mode firstly obtains that the Layer related to the modification is GATE2 through LVL comparison, and then extracts the content related to the GATE2 from the drc.

Because in the drc. Rule of this example, GATE2 does not establish a connection relationship with the POLY and GATE layers, nor does it perform a correlation calculation with them, the Partial Rule will not include Rule1 and Rule2 which only relate to POLY and GATE. Similarly, partial Layout extracted by rev. Gds does not contain POLY, GATE layers. (it should be noted that for real design Layout and DRC Rule, the Layout reduction and Rule reduction by this process is very considerable.)

Since the error of GATE2 is modified, the DRC result (i.e. RULE3 result) of the Partial Layout according to Partial Rule is 0 at this time. The partial_db result is automatically incorporated into the original drc. Db, at which point the drc. Db is updated, as shown in fig. 7.

Since the Auto Switch option was checked, the previous rev1.Gds will automatically set to layout_before and empty layout_after. At this time, the user continues to modify the Layout, and the modification modifies both the POLY and GATE layers to be compliance, rev2.Gds, and sets to layout_after.

To embody the logic of the Region Mode, the second iteration selects the Region Mode to be performed, and only a local area is selected as the Bias Region, and the area only contains part of modified content, as shown in fig. 8.

And extracting all the graphics contacted with the frame selection position by the Region Mode as Partial Layout, and extracting Partial Rule from the drc. The Partial Rule does not contain GATE2 information or RULE3 information. Partial Layout performs DRC according to Partial Rule.

The result partial_db of the local DRC is automatically incorporated into drc_db. It should be noted that, although the Partial Layout includes 2 POLY patterns (all have contacts) in the Layout, no error occurs in the partial_db, and the Bias Region is not completely framed to the original error coordinates of the bottom POLY pattern, so the original error at the position is not removed (refer to step 103 for specific logic). Drcdb update after this iteration is shown in fig. 9. (the remaining 1 result, i.e., the original result that was not removed, the reverse mark can be seen to have a position that is not compatible with the existing layout.)

And the user flexibly selects the Layer Mode or Region Mode for multiple iterations according to the layout characteristics until the layout is compliant and the iteration is finished. (after which a Full DRC can be run once as a final check.)

The invention provides a DRC rapid iteration method for verifying layout modification, which comprises the following steps: based on the DRC result of the original layout, after the user modifies the layout, the method (tool) can judge and extract the DRC result range affected by the modification, and can pertinently perform quick local DRC (local DRC) and automatically combine the DRC result into the original DRC result. Compared with the traditional layout verification DRC which needs to re-run the complete DRC (Full DRC) each time, and the correction accuracy is manually compared and judged, the method can greatly reduce the time and the memory expense for DRC iteration and improve the layout correction efficiency.

The invention also provides a local DRC-based layout modification verification quick iteration device, which comprises a memory and a processor, wherein the memory is stored with a program running on the processor, and the processor executes the steps of the local DRC-based layout modification verification quick iteration method when running the program.

The present invention also provides a computer readable storage medium, on which computer instructions are stored, the computer instructions executing the steps of the local DRC-based layout modification verification fast iteration method described above, where the local DRC-based layout modification verification fast iteration method is referred to the description of the foregoing sections and will not be repeated.

Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A layout modification verification quick iteration method based on local DRC is characterized by comprising the following steps:

Feeding back the result obtained by each partial DRC to the original DRC result, and removing the result passing modification;

the step of feeding back the result obtained by each partial DRC into the original DRC result, and removing the result of modification passing, further comprises:

Performing local DRC on the local layout according to the local rule to obtain a local checking result;

2. The local DRC-based layout modification verification rapid iteration method according to claim 1, wherein the step of filtering the local layout information and the corresponding partial rules for each modification and performing the local DRC further comprises,

3. The local DRC based layout modification verification rapid iteration method according to claim 1, further comprising the step of performing layout screening on the local DRC by a hierarchical mode or a regional mode,

4. The local DRC based layout modification verification rapid iteration method according to claim 1, further comprising the step of performing layout screening on the local DRC by a hierarchical mode or a regional mode,

5. The local DRC-based layout modification verification quick iteration method as claimed in claim 1, further comprising,

6. The local DRC-based layout modification verification fast iteration method according to claim 1, wherein the step of feeding back the result obtained by each local DRC into the original DRC result, removing the result passed by the modification, further comprises,

Defining the modified layout as the original layout of the next iteration;

7. An electronic device comprising a memory and a processor, the memory having stored thereon a program running on the processor, the processor executing the steps of the local DRC-based layout modification verification fast iteration method of any one of claims 1-6 when the program is run.

8. A computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the local DRC based layout modification verification fast iteration method of any one of claims 1-6.