CN114910774A - Automatic testing method, device, equipment and storage medium for chip pins - Google Patents
Automatic testing method, device, equipment and storage medium for chip pins Download PDFInfo
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- CN114910774A CN114910774A CN202210424839.2A CN202210424839A CN114910774A CN 114910774 A CN114910774 A CN 114910774A CN 202210424839 A CN202210424839 A CN 202210424839A CN 114910774 A CN114910774 A CN 114910774A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention discloses an automatic testing method, device, equipment and storage medium of a chip pin, which are characterized in that a control server side is used for compiling source codes corresponding to an obtained testing serial number into a mirror image file in sequence; after receiving a pin definition coding instruction sent by an external test board, a complex programmable logic device of the test mainboard is controlled to analyze the pin definition coding instruction so as to realize the communication of the chip pins to be tested; and downloading the image file into the chip to be tested, testing the pins of the chip to be tested according to the image file, sending the test result to an external test board, and generating a full pin test result after receiving the test results of all the pins of the chip to be tested. Compared with the prior art, the technical scheme of the application overcomes the defect that the traditional development board test can only cover limited chip pins and functions on the chip pins, realizes automatic test of the chip, reduces dependence on workers in the test process, and improves the test efficiency of the chip pins.
Description
Technical Field
The present invention relates to the field of chip testing technologies, and in particular, to a method, an apparatus, a device, and a storage medium for automatically testing a chip pin.
Background
In the prior art, chip pins are tested, and the test is usually performed based on a development board. One function of the chip usually supports the selection of a plurality of groups of pins, one pin usually has multiplexing of a plurality of functions, the pin selection on the development board is usually realized through a jumper wire, if the development board covers all the function multiplexing of all the pins, the combination quantity among the pins can be very large, and the design difficulty, the workload and the complexity of the development board are greatly increased, so that the traditional development board test can only cover limited chip pins and the functions on the chip pins, and all the pins of the chip and the functions on the chip can not be completely covered due to different requirements of the hardware design of the development board. If the pins which are not led out by the development board on the chip or other functions of the pins need to be tested, flying wires and external small boards are needed, so that the efficiency of a tester is low, the operation is complex, and time and labor are wasted.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the method, the device, the equipment and the storage medium for automatically testing the chip pins are provided, so that the dependence on manpower in the testing process is reduced, and the testing efficiency of the chip pins is improved.
In order to solve the technical problem, the invention provides an automatic testing method of a chip pin, which comprises the following steps:
acquiring and traversing all test serial numbers defined by the test script, controlling the server to sequentially acquire source codes corresponding to the test serial numbers, compiling the source codes into image files and storing the image files into an external test board;
controlling the external test board to send the pin definition coding instruction corresponding to the test serial number to a complex programmable logic device of a test mainboard so that the complex programmable logic device analyzes the pin definition coding instruction and communicates with a corresponding chip pin to be tested;
and controlling the external test board to download the image file into the chip to be tested so that the chip to be tested tests the pins of the chip to be tested according to the image file, and sending a test result to the external test board until the external test board receives the test results of all the pins of the chip to be tested, thereby generating a full pin test result of the chip to be tested.
In a possible implementation manner, before controlling the external test board to send a pin definition coding instruction corresponding to the test serial number to the complex programmable logic device of the test motherboard, the method further includes:
and controlling the external test board to be connected with an expansion chip through an I2C interface, and connecting the external test board with the complex programmable logic device of the test mainboard based on an IO interface of the expansion chip.
In a possible implementation manner, the external test board is controlled to download the image file to a chip to be tested, which specifically includes:
and controlling the external test board to be connected with the chip to be tested through the serial port of the test mainboard so that the external test board controls the chip to be tested to enter a UBOOT command line mode, and downloading the image file corresponding to the current test serial number to the chip to be tested based on a preset command.
The invention also provides an automatic testing device for the chip pins, which comprises: acquiring a module, a server, an external test board, a test mainboard and a chip to be tested;
the acquisition module is used for acquiring a test serial number defined according to the test script;
the server is used for sequentially acquiring source codes corresponding to the test serial numbers, compiling the source codes into image files and storing the image files into an external test board;
the external test board is used for sending the pin definition coding instruction corresponding to the test serial number to a complex programmable logic device of a test mainboard;
the test mainboard is used for receiving the pin definition coding instruction, enabling the complex programmable logic device to analyze the pin definition coding instruction and communicating with the corresponding chip pin to be tested;
the external test board is used for downloading the mirror image file to a chip to be tested;
the chip to be tested is used for testing the pins of the chip to be tested according to the mirror image file and sending a test result to the external test board;
the external test board is used for receiving test results of all the pins of the chip to be tested and generating a full pin test result of the chip to be tested.
In a possible implementation manner, before the external test board is configured to send a pin definition coding instruction corresponding to the test serial number to a complex programmable logic device of a test motherboard, the external test board further includes:
the external test board is used for being connected with an expansion chip through an I2C interface and being connected with the complex programmable logic device of the test mainboard based on an IO interface of the expansion chip.
In a possible implementation manner, the external test board is configured to download the image file to a chip to be tested, and specifically includes:
the external test board is used for connecting the chip to be tested through the serial port of the test mainboard, controlling the chip to be tested to enter a UBOOT command line mode, and downloading the image file corresponding to the current test serial number to the chip to be tested based on a preset command.
The invention also provides a terminal device, which comprises a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to realize the automatic testing method for the chip pins.
The invention also provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program runs, the apparatus where the computer-readable storage medium is located is controlled to execute the method for automatically testing the chip pin according to any one of the above items.
Compared with the prior art, the automatic testing method, the device, the equipment and the storage medium of the chip pin have the following beneficial effects:
the testing source codes are sequentially downloaded through the server according to the testing serial numbers, the source codes are compiled into image files and then are stored in the external testing board, and meanwhile, the external testing board sends corresponding pin definition coding instructions to the complex programmable logic device of the testing mainboard based on the testing serial numbers, so that the complex programmable logic device analyzes the pin definition coding instructions, the communication of the pins of the chip to be tested is realized, the condition that the manual jumper operation is needed for the communication of the pins in the prior art is avoided, and the manual intervention is reduced; and after the chip pins are communicated, downloading the image file to a chip to be tested through an external test board so that the chip to be tested tests the chip pins to be tested according to the image file, and sending a test result to the external test board until the external test board receives the test results of all the chip pins to be tested, thereby generating a full pin test result of the chip to be tested. Compared with the prior art, the technical scheme of the application improves the defects that the traditional development board test can only cover limited chip pins and the function on the chip pins, realizes the automatic test of the chip, reduces the dependence on manpower in the test process, and improves the test efficiency of the chip pins.
Drawings
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a method for automatically testing a chip pin according to the present invention;
FIG. 2 is a schematic structural diagram of an embodiment of an apparatus for automatically testing a chip pin according to the present invention;
fig. 3 is a schematic connection diagram of an embodiment of an apparatus for automatically testing chip pins according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic flowchart of an embodiment of an automated testing method for a chip pin according to the present invention, as shown in fig. 1, the method includes steps 101 to 103, which are specifically as follows:
step 101: and acquiring and traversing all test serial numbers defined by the test script, controlling the server to sequentially acquire source codes corresponding to the test serial numbers, compiling the source codes into image files, and storing the image files into an external test board.
In one embodiment, the test script includes a plurality of test cases, and a test sequence number is defined for each test case, so that the plurality of test cases are sequentially ordered according to the test sequence number. Each test case comprises a command number sent to the complex programmable logic device CPLD of the test mainboard, and the command number is used for enabling the complex programmable logic device CPLD of the test mainboard to connect a set of specified chip pins with a specified test device; each test case also includes test commands for testing a specified set of chip pins.
In an embodiment, the server includes a code server and an editing server, and is configured to obtain source codes of the test cases one by one according to a sequence of the test serial number, and compile the source codes to generate an image file corresponding to the test case. The source codes of each test case comprise UBOOT source codes, LINUX KERNEL source codes, root file system source codes, self-defined application program source codes and equipment tree source codes, and the UBOOT image files for testing, the LINUX KERNEL image files, the root file system image files and the DTB image files generated by compiling the equipment tree source codes are generated by compiling the root file system source codes and the self-defined application program source codes after the source codes are compiled.
In one embodiment, the external test board is used as a test control host, one end of the test control host is connected with the server, and after the server compiles the source code into the image file, the image file is downloaded to the external test board according to the test serial number, wherein the external test board is a raspberry type external test board.
Step 102: and controlling the external test board to send the pin definition coding instruction corresponding to the test serial number to a complex programmable logic device of the test mainboard, so that the complex programmable logic device analyzes the pin definition coding instruction and is communicated with the corresponding chip pin to be tested.
In an embodiment, before controlling the external test board to send the pin definition coding instruction corresponding to the test serial number to the complex programmable logic device of the test motherboard, the external test board is controlled to be connected to the I2C-IO expansion chip through an I2C interface, and is connected to the complex programmable logic device CPLD of the test motherboard based on an IO interface of the expansion chip, as shown in fig. 3.
In an embodiment, the pin definition coding instruction is a command number sent to the complex programmable logic device CPLD of the test motherboard, and is used for enabling the complex programmable logic device CPLD of the test motherboard to connect a specified group of chip pins with a specified test device.
In an embodiment, based on the connection relationship between the external test board and the expansion chip, the external test board is controlled to send the pin definition coding instruction to the complex programmable logic device CPLD of the test motherboard through the I2C-IO expansion chip via the I2C interface, and after receiving the pin definition coding instruction, the complex programmable logic device CPLD of the test motherboard analyzes the pin definition coding instruction and communicates with the corresponding chip pin.
Step 103: and controlling the external test board to download the image file into the chip to be tested so that the chip to be tested tests the pins of the chip to be tested according to the image file, and sending a test result to the external test board until the external test board receives the test results of all the pins of the chip to be tested, thereby generating a full pin test result of the chip to be tested.
In one embodiment, the external test board is controlled to be connected with the chip to be tested through a serial port of the test mainboard, a reset pin of the chip to be tested is controlled through an IO pin to output high and low levels, the chip to be tested is controlled to start, and the chip to be tested is controlled to enter a UBOOT command line mode.
In one embodiment, the external test board is controlled to download the DTB image file in the image file corresponding to the current test serial number to the memory of the main control chip to be tested through the serial port or the network port. In the UBOOT command line mode, a command downloaded through a serial port is loadb, and a command downloaded through a network port is tftp.
In one embodiment, the external test board is controlled to save the test sequence number into the environment variable of the UBOOT command line mode through setenv and savenv commands in the UBOOT command line mode.
In an embodiment, the external test board is controlled to enter the kernel boot system through a bootm command in the UBOOT command line mode through a corresponding DTB image file in the memory of the chip to be tested.
In one embodiment, based on the DTB image file, the external test board controls the chip to be tested to execute a test case with multiplexing of each module and pin. The DTB image file is compiled from a device tree file, and all hardware configuration data of the system is stored in the DTB image file. The DTB image file contains the functions of each pin of the chip, and the settings of the up-down pulling, the driving capability, the slewrate and the like of the pin.
In one embodiment, the DTB image file is analyzed based on a kernel boot system, the configuration information of each chip pin is obtained, then a relevant chip register is configured, each chip pin is in a state defined by the DTB image file and comprises functions, pull-up and pull-down, driving capability, a skew rate and the like, and then the raspberry sends an external test board to control a chip to be tested to execute a test case in a test script.
In one embodiment, the system on the chip to be tested outputs the result of the current test case on the serial port, and the external test board obtains the test result in real time.
In this embodiment, based on different chip pins, the test cases for each module and pin multiplexing executed by the chip to be tested are different.
In an embodiment, for a serial port pin, a complex programmable logic device CPLD of a test motherboard connects RX and TX of a serial port to form a loop, and tests through a preset command under LINUX, and returns a test result of the serial port pin to a raspberry through a serial port for processing, wherein the test result of the serial port pin includes data, error information, and debugging information received from RX.
In one embodiment, for pin I2C, the CPLD of the motherboard will connect I2C to external I2C _ RAM, and test the pin I2c _ test command in LINUX, and send the test result of pin I2C back to the raspberry through the serial port for processing, where the test result of pin I2C includes data sent to the I2C bus, data received on the I2C bus, error information, and debug information.
In one embodiment, for an SPI pin, a complex programmable logic device CPLD of a test motherboard connects an SPI to an external SPI RAM, tests through spidev under LINUX, and sends back a test result of the SPI pin to a raspberry through a serial port for processing, wherein the test result of the SPI pin includes data sent to an SPI bus, data received on the SPI bus, error information, and debugging information;
in an embodiment, for a network interface pin, a ping command is used for testing, and a test result of the SPI pin is returned to the raspberry through a serial port for processing, wherein the test result of the SPI pin includes data sent to the SPI bus, data received on the SPI bus, error information, and debugging information.
In an embodiment, for the SDIO WIFI pin, the complex programmable logic device CPLD of the test motherboard can communicate with the SDIO WIFI pin on the test motherboard, start WIFI through wpa _ suppernant command under LINUX, and pass the test result of the SDIO WIFI pin back through the serial port to the raspberry group for processing, wherein the test result of the SDIO WIFI pin includes whether WIFI starts successfully, error information and debugging information.
In one embodiment, the PWM pin is externally connected with a DC-DC control power supply to output, then the power supply voltage output is sampled through the SAR-ADC, the SARADC drive is used for reading a voltage value to test, and the test result of the PWM pin is transmitted back to the raspberry through the serial port to be processed, wherein the test result of the PWM pin comprises the voltage value sampled through the SAR-ADC when the PWM pin is at a low level, the voltage value sampled through the SAR-ADC when the PWM pin is at a high level, and the voltage value sampled when the PWM pin outputs PWM with 50KHZ duty ratio of 50%, error information and debugging information.
In one embodiment, for a TF card pin, a Complex Programmable Logic Device (CPLD) of a test mainboard is communicated with the TF card pin on the test mainboard, a TF card drive is inserted under LINUX to generate a device file of/dev/mmcblk, then a read-write test is carried out under a mount-to-/mnt directory, and a test result of the TF card pin is returned to a raspberry through a serial port for processing, wherein the test result of the TF card pin comprises whether the drive normally operates, whether a/dev/mmcblk device file is generated, whether the/dev/mmcblk device file can be hung on the test directory, whether a test file can be created in the test directory and test data can be written, whether an MD5 check code is correct after the test file is written, error information and debugging information.
IN an embodiment, for GPIO pins, the CPLD of the test motherboard connects the GPIO pins of the chip two by two, and outputs a high level or a low level to one of the GPIOs through gpiolib IN LINUX, and then reads and tests at the other GPIO, and returns the test result of the GPIO pin to the raspberry through a serial port for processing, where the test result of the GPIO pin includes a value read by IN GPIO when OUT GPIO is set to a high level, and a value read by IN GPIO when OUT GPIO is set to a low level.
In one embodiment, the test result includes a destination IP address, a length of the test packet, a round trip time of each test packet, error information, and debug information. Judging the packet loss phenomenon or judging whether the output of abnormal information such as disconnection reconnection exists or not according to the round-trip time of each obtained test data packet to obtain the functional state of the current test pin; if the current test pin is in normal function, the phenomena of packet loss, that is, the round-trip time is not overtime, and the output of error information such as disconnection and reconnection are avoided. If the pin is not normal, abnormal information such as packet loss, disconnection, reconnection and the like can be output.
In one embodiment, because one DTB image file cannot cover all pins and all pin functions of a chip, multiple DTB image files are needed to cover all pins and all pin functions of a chip to be tested, and the raspberry sends an external test board to control the chip to be tested to use different DTB image files to repeat test steps, so that all pin functions of the chip are covered as much as possible. And when the external test board receives the test results of all the pins of the chip to be tested, counting and generating the test results of all the pins of the chip to be tested.
In summary, according to the automatic testing method for chip pins provided by this embodiment, the testing source codes are compiled into the image file, and the analysis is performed based on the pin definition coding instruction, so as to connect the corresponding chip pins to be tested, and after the connection, the chip pins are detected based on the image file, so as to generate the testing result covering all the pins of the chip. Compared with the prior art, the embodiment improves the defects that the traditional development board test can only cover limited chip pins and the function defects on the chip pins, realizes the automatic test on all the pins of the chip, reduces the dependence on manpower in the test process, and improves the test efficiency of the chip pins; meanwhile, the problems that the existing testing method is scattered and complex to operate are solved, the testing method provided by the embodiment can simplify the operation process, more comprehensively and objectively output accurate testing results and provide the accuracy of the testing results.
Example 2
Referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of an automatic testing apparatus for chip pins provided by the present invention, as shown in fig. 2, the apparatus includes an obtaining module 201, a server 202, an external testing board 203, a testing motherboard 204, and a chip to be tested 205, which are as follows:
the obtaining module 201 is configured to obtain a test serial number defined according to the test script.
And the server 202 is configured to sequentially obtain the source codes corresponding to the test sequence numbers, compile the source codes into an image file, and store the image file in an external test board.
And the external test board 203 is used for sending the pin definition coding instruction corresponding to the test serial number to the complex programmable logic device of the test mainboard.
And the test main board 204 is configured to receive the pin definition coding instruction, analyze the pin definition coding instruction by using the complex programmable logic device, and communicate with a corresponding chip pin to be tested.
And the external test board 203 is used for downloading the image file into a chip to be tested.
And the chip to be tested 205 is used for testing the pin of the chip to be tested according to the image file and sending a test result to the external test board.
And the external test board 203 is used for receiving the test results of all the pins of the chip to be tested and generating a full pin test result of the chip to be tested.
In an embodiment, the external test board 203 is configured to, before sending the pin definition coding instruction corresponding to the test serial number to the complex programmable logic device of the test motherboard, further include the external test board 203, configured to connect with the expansion chip through an I2C interface, and connect with the complex programmable logic device of the test motherboard based on an IO interface of the expansion chip.
In an embodiment, the external test board 203 is configured to download the image file to a chip to be tested, and specifically, the external test board 203 is configured to connect with the chip to be tested through a serial port of the test motherboard, control the chip to be tested to enter a UBOOT command line mode, and download the image file corresponding to the current test serial number to the chip to be tested based on a preset command.
It can be clearly understood by those skilled in the art that, for convenience and brevity, the specific working process of the system described above may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.
Further, an embodiment of the present application further provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, where the processor, when executing the computer program, implements the method for automatically testing chip pins according to the foregoing embodiment.
Further, an embodiment of the present application further provides a computer-readable storage medium, where the computer-readable storage medium includes a stored computer program, where when the computer program runs, the apparatus where the computer-readable storage medium is located is controlled to execute the method for automatically testing a chip pin according to the foregoing embodiment.
In summary, according to the automatic testing method, device, equipment and storage medium for chip pins, the server is controlled to sequentially obtain the source codes corresponding to the test serial numbers by obtaining and traversing all the test serial numbers defined by the test script, and the source codes are compiled into the image file and then stored in the external test board; controlling the external test board to send the pin definition coding instruction corresponding to the test serial number to a complex programmable logic device of a test mainboard so that the complex programmable logic device analyzes the pin definition coding instruction and communicates with a corresponding chip pin to be tested; and controlling the external test board to download the image file to the chip to be tested so that the chip to be tested tests the pins of the chip to be tested according to the image file, and sending a test result to the external test board until the external test board receives the test results of all the pins of the chip to be tested, thereby generating a full pin test result of the chip to be tested. Compared with the prior art, the technical scheme of the application overcomes the defect that the traditional development board test can only cover limited chip pins and functions on the chip pins, realizes automatic test of the chip, reduces dependence on workers in the test process, and improves the test efficiency of the chip pins.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.
Claims (8)
1. An automatic test method for chip pins is characterized by comprising the following steps:
acquiring and traversing all test serial numbers defined by the test script, controlling the server to sequentially acquire source codes corresponding to the test serial numbers, compiling the source codes into image files and storing the image files into an external test board;
controlling the external test board to send the pin definition coding instruction corresponding to the test serial number to a complex programmable logic device of a test mainboard so that the complex programmable logic device analyzes the pin definition coding instruction and communicates with a corresponding chip pin to be tested;
and controlling the external test board to download the image file into the chip to be tested so that the chip to be tested tests the pins of the chip to be tested according to the image file, and sending a test result to the external test board until the external test board receives the test results of all the pins of the chip to be tested, thereby generating a full pin test result of the chip to be tested.
2. The method according to claim 1, wherein before controlling the external test board to send the pin definition coding command corresponding to the test serial number to the complex programmable logic device of the test motherboard, the method further comprises:
and controlling the external test board to be connected with an expansion chip through an I2C interface, and connecting the external test board with the complex programmable logic device of the test mainboard based on an IO interface of the expansion chip.
3. The method for automatically testing chip pins according to claim 1, wherein the external test board is controlled to download the image file to the chip to be tested, specifically:
and controlling the external test board to be connected with the chip to be tested through the serial port of the test mainboard so that the external test board controls the chip to be tested to enter a UBOOT command line mode, and downloading the image file corresponding to the current test serial number to the chip to be tested based on a preset command.
4. An automated testing apparatus for a chip pin, comprising: the method comprises the steps of obtaining a module, a server, an external test board, a test mainboard and a chip to be tested;
the acquisition module is used for acquiring a test serial number defined according to the test script;
the server is used for sequentially acquiring source codes corresponding to the test serial numbers, compiling the source codes into image files and storing the image files into an external test board;
the external test board is used for sending the pin definition coding instruction corresponding to the test serial number to a complex programmable logic device of a test mainboard;
the test mainboard is used for receiving the pin definition coding instruction, enabling the complex programmable logic device to analyze the pin definition coding instruction and communicating with the corresponding chip pin to be tested;
the external test board is used for downloading the mirror image file to a chip to be tested;
the chip to be tested is used for testing the pins of the chip to be tested according to the mirror image file and sending a test result to the external test board;
the external test board is used for receiving test results of all chip pins to be tested and generating a full pin test result of the chip to be tested.
5. The apparatus for automatically testing chip pins according to claim 4, wherein the external test board, before sending the pin definition coding command corresponding to the test serial number to the complex programmable logic device of the test motherboard, further comprises:
the external test board is used for being connected with an expansion chip through an I2C interface and being connected with the complex programmable logic device of the test mainboard based on an IO interface of the expansion chip.
6. The apparatus for automatically testing chip pins according to claim 4, wherein the external test board is used for downloading the image file to the chip to be tested, and specifically comprises:
the external test board is used for connecting the chip to be tested through the serial port of the test mainboard, controlling the chip to be tested to enter a UBOOT command line mode, and downloading the image file corresponding to the current test serial number to the chip to be tested based on a preset command.
7. A terminal device comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, the processor implementing the method of automated testing of chip pins according to any one of claims 1 to 3 when executing the computer program.
8. A computer-readable storage medium, comprising a stored computer program, wherein the computer program, when running, controls an apparatus in which the computer-readable storage medium is located to execute the method for automated testing of chip pins according to any one of claims 1 to 3.
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| CN202210424839.2A CN114910774A (en) | 2022-04-20 | 2022-04-20 | Automatic testing method, device, equipment and storage medium for chip pins |
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| CN202210424839.2A CN114910774A (en) | 2022-04-20 | 2022-04-20 | Automatic testing method, device, equipment and storage medium for chip pins |
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