CN114900883A

CN114900883A - Method and device for processing candidate synchronous signal block

Info

Publication number: CN114900883A
Application number: CN202210590820.5A
Authority: CN
Inventors: 周化雨; 潘振岗
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2019-12-12
Filing date: 2019-12-12
Publication date: 2022-08-12
Also published as: CN111130716A; CN111130716B; WO2021114732A1

Abstract

The embodiment of the invention discloses a method and a device for processing a candidate synchronous signal block, wherein the method comprises the following steps: candidate sync signal block indices are determined, the candidate sync signal block indices being from 0 to N-1, with N being 4, 8, 10, 16, 20, 32, or 40. By implementing the embodiment of the invention, the coverage performance of the candidate synchronous signal block is favorably improved.

Description

Method and device for processing candidate synchronous signal block

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for processing a candidate synchronization signal block.

Background

In a wireless communication system, a User Equipment (UE) may implement time-frequency synchronization with a Base Station (BS) through a candidate synchronization signal block. The Synchronization Signal Block (SS/PBCH Block) or Candidate Synchronization Signal Block (Candidate SS/PBCH Block) may include a Primary Synchronization Signal (PSS), a Secondary Synchronization Signal (SSs), and a Physical Broadcast Channel (PBCH).

In scenarios supporting low complexity terminal access, such as NR-Light (NR Light access), the terminal may have only one receive antenna. In this case, the receiving performance of the terminal may be degraded, resulting in low coverage performance of the candidate synchronization signal block.

Disclosure of Invention

The embodiment of the invention discloses a method and a device for processing candidate synchronizing signal blocks, which are beneficial to improving the coverage performance of the candidate synchronizing signal blocks.

In a first aspect, an embodiment of the present invention discloses a method for processing a candidate synchronization signal block, where the method may include: candidate synchronization signal block indices are determined, the candidate synchronization signal block indices ranging from 0 to N-1, with N being 4, 8, 10, 16, 20, 32, or 40.

In one implementation, the specific implementation manner of determining the candidate synchronization signal block index may be: and determining the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the load of the PBCH.

In one implementation, where the subcarrier spacing of the candidate synchronization signal block is 15kHz, the aforementioned N may be 4, 8, 10, 16, or 20.

In one implementation, the specific implementation manner of determining the candidate synchronization signal block index may be: 2 or 3 LSB bits of the candidate synchronization signal block index are determined according to the PBCH-DMRS sequence.

In one implementation, the specific implementation manner of determining the candidate synchronization signal block index may be: the 1, 2 or 3 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

In one implementation, the specific implementation of determining 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH may be: if N is 10, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 20, 2 MSB bits of the candidate sync signal block index are determined according to the load of the PBCH.

In one implementation, where the subcarrier spacing of the candidate synchronization signal block is 30kHz, N may be 4, 8, 10, 16, 20, 32, or 40.

In one implementation, the specific implementation of determining 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH may be: if N is 10 or 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 20, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH; if N is 32, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH; if N is 40, 3 MSB bits of the candidate sync signal block index are determined according to the load of the PBCH.

In one implementation, the method may further include: the number of repetitions of a candidate synchronization signal block group, which may include a plurality of candidate synchronization signal blocks, within a transmission window is determined.

In one implementation, the specific implementation manner of determining the number of repetitions of the candidate synchronization signal block group in the transmission window may be: and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window.

In one implementation manner, the specific implementation manner of determining the number of repetitions of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window may be: determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the time length of the transmission window; and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the number of the candidate synchronization signal blocks included in the candidate synchronization signal block group and the number of the candidate synchronization signal blocks transmitted in the transmission window.

In one implementation, the method may further include: first signaling sent by a network device is received, and the first signaling can be used for indicating the number of repetitions of a candidate synchronization signal block group within a transmission window.

In one implementation, the method may further include: the number of repetitions of a set of candidate synchronization signal block sets, which may include a plurality of candidate synchronization signal blocks, within a transmission window is determined.

In one implementation, the specific implementation manner of determining the number of repetitions of the set consisting of multiple candidate synchronization signal block groups in the transmission window may be: determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the time length of the transmission window; and determining the repetition times of the set in the transmission window according to the number of the candidate synchronization signal blocks included in the set consisting of a plurality of candidate synchronization signal block groups and the number of the candidate synchronization signal blocks transmitted in the transmission window.

In one implementation, an extension index of a candidate synchronization signal block is determined, and a quasi-co-site relationship or a synchronization signal block index of the candidate synchronization signal block is determined according to the extension index of the candidate synchronization signal block.

In one implementation, the specific implementation manner of determining the extension index of the candidate synchronization signal block may be: and determining the expansion index of the candidate synchronization signal block as i ═ X1 × i1+ i2 according to the time length of the expanded transmission window, the time length of the transmission window and the period of the transmission window, wherein X1 is the number of the candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the time length of the expanded transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

In one implementation, the specific implementation manner of determining the extension index of the candidate synchronization signal block may be: according to the duration of the extended transmission window and the period of the received half frame or frame of the candidate synchronization signal block, determining the extended index of the candidate synchronization signal block as i ═ X2 ═ i3+ i4, wherein X2 is the number or maximum number of the candidate synchronization signal blocks in a half frame or a frame, i3 is the index of the period of the received half frame or frame of the candidate synchronization signal block in the duration of the extended transmission window, and i4 is the index of the aforementioned candidate synchronization signal block.

In one implementation manner, the specific implementation manner of determining the quasi-co-site relationship of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block may be: a plurality of candidate synchronization signal blocks have a quasi co-site relationship if they have the same value (a mod Q), where a is the spreading index of the candidate synchronization signal block, Q is a high level parameter, and mod represents a modulo or remainder operation (modulo).

In one implementation manner, the specific implementation manner of determining the synchronization signal block index of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block may be: determining a synchronization signal block index of the candidate synchronization signal block as (A mod Q), wherein A is an extension index of the candidate synchronization signal block, Q is a high-level parameter, and mod represents a modulo or remainder operation (modulo).

In a second aspect, an embodiment of the present invention discloses a device for processing a candidate synchronization signal block, where the device includes a unit configured to perform the method according to the first aspect.

In a third aspect, an embodiment of the present invention discloses a terminal, where the terminal includes a memory and a processor, where the memory is used to store a computer program, the computer program includes program instructions, and the processor is configured to call the program instructions to execute the method according to the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium for storing computer program instructions for use by the processing apparatus for candidate synchronization signal blocks described in the third aspect, which includes a program for performing the method of the first aspect.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a flowchart illustrating a method for processing a candidate synchronization signal block according to an embodiment of the present invention;

fig. 2 is a flowchart illustrating another method for processing a candidate synchronization signal block according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a device for processing candidate sync signal blocks according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for processing a candidate synchronization signal block according to an embodiment of the present invention. The method is applied to a terminal, and specifically, as shown in fig. 1, the method for processing a candidate synchronization signal block according to the embodiment of the present invention may include, but is not limited to, the following steps:

s101, a terminal (also called User Equipment, UE) determines a candidate synchronization signal block index, wherein the candidate synchronization signal block index is from 0 to N-1, and N is 4, 8, 10, 16, 20, 32 or 40. The candidate sync signal block index may refer to an index (or number) of a candidate sync signal block within one field (half frame or half radio frame) or one frame (frame or radio frame), that is, N candidate sync signal blocks within one field or one frame. In general, a frame is also called a "radio frame" and has a duration of 10ms, and a half-frame is also called a "half-radio frame" and has a duration of 5 ms.

In an embodiment of the present invention, each candidate synchronization signal block has a predetermined or candidate time domain position, which may also be referred to as a time domain position of the candidate synchronization signal block. The terminal detects the candidate sync signal block and determines a candidate sync signal block index.

In embodiments of the present invention, a field or a frame may include N candidate synchronization signal blocks, which may be consecutively numbered in order from 0 to N-1, or the candidate synchronization signal block index may be from 0 to N-1. That is, the base station can transmit a maximum of N candidate synchronization signal blocks in one field or one frame. Where N may be 4, 8, 10, 16, 20, 32, 40 or other values.

In a scenario supporting low-complexity terminal access, such as a New Radio (NR) lightweight access (NR-Light) of a fifth Generation mobile communication technology (5th-Generation, 5G), the terminal may have only one receiving antenna. In this case, the receiving performance of the terminal may be degraded, resulting in low coverage performance of the candidate synchronization signal block. Compared with the prior art that 4 or 8 candidate synchronization signal blocks can be sent in a half frame or a frame at most, the embodiment of the invention enables more candidate synchronization signal blocks to be sent in a half frame or a frame. Therefore, the embodiment of the invention is beneficial to the terminal to receive more candidate synchronous signal blocks, thereby being beneficial to improving the coverage performance of the candidate synchronous signal blocks.

In the embodiments of the present invention, a terminal may refer to various forms of user equipment, access terminal, subscriber unit, subscriber Station, Mobile Station (MS), remote Station, remote terminal, Mobile device, user terminal, terminal device (terminal equipment), wireless communication device, user agent, or user equipment. The terminal device may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with a Wireless communication function, a computing device or other processing devices connected to a Wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a 5G Network, or a terminal device in a Public Land Mobile Network (PLMN) for future evolution, and the like, which are not limited in the embodiments of the present invention.

The network device may be an entity on the network side for transmitting or receiving signals, e.g. the network device may be an access network device (e.g. a base station). Devices providing Base Station functionality in 2G networks include Base Transceiver Stations (BTSs) and Base Station Controllers (BSCs). The device providing a base station function in a 3G Network includes a node b (nodeb) and a Radio Network Controller (RNC). Apparatuses providing a base station function in a 4G network include Evolved node bs (Evolved nodebs, abbreviated enbs). In a Wireless Local Area Network (WLAN), a device providing a base station function is an Access Point (AP). The device providing the base station function in the 5G NR includes a node b (gnb) that continues to evolve, and the base station in the embodiment of the present invention may also refer to a device providing the base station function in a new communication system in the future, or the like.

It should be noted that the technical solution provided by the embodiment of the present invention may be applicable to 3G, 4G, or 5G communication systems, and may also be applicable to various communication systems of subsequent evolution. It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in this document indicates that the former and latter related objects are in an "or" relationship. "plurality" appearing in the embodiments of the present invention means two or more.

In one implementation, the terminal may further determine a number of repetitions of a candidate synchronization signal block group within the transmission window, the candidate synchronization signal block group including a plurality of candidate synchronization signal blocks. Each candidate synchronization signal block may include the same number of candidate synchronization signal blocks. In this way, the terminal can determine the number of repetitions of the candidate synchronization signal block set, thereby performing a receiver combining algorithm to enhance the terminal reception performance. The receiver combining algorithm includes the receiver accumulating or soft combining the detected values of the signals or channels within the multiple candidate synchronization signal blocks and detecting or demodulating or decoding the combined values to improve reception performance. Generally, a candidate synchronization signal block is composed of non-Quasi-Co-Located (non-QCL) or synchronization signal blocks using different beams. For example, in some scenarios, multiple synchronization signal blocks are co-site-intended if they have the same average gain (average gain), QCL-type a, and QCL-type d properties, and are not co-site-intended otherwise. It should be noted that the above definition of the quasi-co-site is only for example and does not limit the embodiments of the present invention. In other possible implementations, the quasi-co-site may be defined in other ways.

In general, the transmission window may be a time window. The Transmission Window may be a Discovery Burst Transmission Window (Discovery Burst Transmission Window), a Discovery Signal Transmission Window (Discovery Signal Transmission Window), a candidate synchronization Signal Block Transmission Window (SS/PBCH Block Transmission Window), or other windows, which is not limited in the embodiments of the present invention. In general, the transmission window has a property of duration (or duration) indicating the length of time of the window. The duration of the transmission window may be provided by a higher layer parameter discovery burst-WindowLength-r 16. When the subcarrier spacing of the candidate synchronization signal block is 15kHz and N is 8 or 10, the duration of the transmission window may be 5 milliseconds at maximum. When the subcarrier spacing of the candidate synchronization signal block is 15kHz and N is 16 or 20, the duration of the transmission window may be 10 msec at most. When the subcarrier spacing of the candidate synchronization signal block is 30kHz and N is 8 or 10, the duration of the transmission window may be 2.5 msec at maximum. When the subcarrier spacing of the candidate synchronization signal block is 30kHz and N is 16 or 20, the duration of the transmission window may be 5 milliseconds at maximum. When the subcarrier spacing of the candidate synchronization signal block is 30kHz and N is 32 or 40, the duration of the transmission window may be 10 msec at most. In general, the duration of the transmission window determines the number or maximum number of candidate synchronization signal blocks within the transmission window given the subcarrier spacing of the candidate synchronization signal blocks. In general, the transmission window also has a property of a period, indicating that the window occurs with a certain period. The period of the transmission window may be provided by a higher layer parameter ssb-periodicityServingCell. The period of the transmission window may be the period of the received half frame or frame of the candidate synchronization signal block (provided by the higher layer parameter ssb-period serving cell), or a period configured by the higher layer independently of the period of the received half frame or frame of the candidate synchronization signal block.

The terminal may determine the number of candidate synchronization signal blocks in the transmission window according to the duration of the transmission window. That is, the duration of the transmission window corresponds to the number of candidate synchronization signal blocks transmitted within the transmission window. For example, when the subcarrier interval of the candidate synchronization signal blocks is 30kHz, if the duration of the transmission window is 5ms, the number of candidate synchronization signal blocks in the transmission window is determined to be 20; if the duration of the transmission window is 4ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 16; if the duration of the transmission window is 3ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 12; if the duration of the transmission window is 2ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 8; if the duration of the transmission window is 1ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 4; if the duration of the transmission window is 0.5ms, the number of candidate synchronization signal blocks in the transmission window is determined to be 2. For another example, when the subcarrier interval of the candidate synchronization signal blocks is 15kHz, if the duration of the transmission window is 5ms, the number of candidate synchronization signal blocks in the transmission window is determined to be 10; if the duration of the transmission window is 4ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 8; if the duration of the transmission window is 3ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 6; if the duration of the transmission window is 2ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 4; if the duration of the transmission window is 1ms, determining that the number of the candidate synchronization signal blocks in the transmission window is 2; if the duration of the transmission window is 0.5ms, the number of candidate synchronization signal blocks in the transmission window is determined to be 1.

In one implementation manner, the specific implementation manner of the terminal determining the number of repetitions of the candidate synchronization signal block group in the transmission window may be: and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window. Wherein the duration of the transmission window may be provided by a higher layer parameter. For example, the higher layer parameter may inform the terminal that the duration of the transmission window is 1ms, and the terminal may determine that the duration of the transmission window is 1 ms.

Specifically, the terminal may determine the number of candidate synchronization signal blocks transmitted in the transmission window according to the duration of the transmission window; and determining the number of times of repetition of the candidate synchronization signal block group in the transmission window according to the number of the candidate synchronization signal blocks included in the candidate synchronization signal block group and the number of the candidate synchronization signal blocks transmitted in the transmission window. In general, the number (M) of candidate synchronization signal blocks transmitted within the transmission window may refer to the number of candidate synchronization signal blocks that the terminal can receive at most within the transmission window.

In one implementation, the protocol may specify a number of candidate synchronization signal blocks (Q1) that the set of candidate synchronization signal blocks includes. In general, each candidate synchronization signal block may include the same number of candidate synchronization signal blocks. The terminal may divide the number (M) of candidate synchronization signal blocks transmitted within the transmission window by the number (Q1) of candidate synchronization signal blocks included in the candidate synchronization signal block group, and obtain the result (i.e., M/Q1) as the number of repetitions of the candidate synchronization signal block group within the transmission window. Alternatively, Q1 may be 1, 2, 4, or 8. Optionally, the terminal may obtain a third signaling sent by the network device, where the third signaling may be used to indicate Q1. The third signaling may be existing signaling in a protocol, such as signaling indicating a Quasi Co-Located (QCL) relationship of candidate synchronization signal blocks. Alternatively, the third signaling may be signaling existing in the protocol, such as signaling indicating a quasi co-sited relationship for candidate synchronization signal blocks, but the signaling may be redefined to indicate Q1. Optionally, the third signaling may also be newly defined signaling. For example, when the subcarrier spacing of the candidate synchronization signal block is 30kHz, if the duration of the transmission window is 5ms (M is 20) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 10; if the duration of the transmission window is 4ms (M is 16) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 8; if the duration of the transmission window is 3ms (M is 12) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 6; if the duration of the transmission window is 2ms (M is 8) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 4; if the duration of the transmission window is 1ms (M is 4) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 2; if the duration of the transmission window is 0.5ms (M is 2) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 1. For another example, when the subcarrier interval of the candidate synchronization signal block is 15kHz, if the duration of the transmission window is 5ms (M is 10) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 5; if the duration of the transmission window is 4ms (M is 8) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 4; if the duration of the transmission window is 3ms (M is 6) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 3; if the duration of the transmission window is 2ms (M is 4) and Q1 is 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 2; if the duration of the transmission window is 1ms (M equals 2) and Q1 equals 2, the terminal may determine that the number of repetitions of the candidate synchronization signal block group in the transmission window is 1. Alternatively, the terminal may divide the number (M) of candidate synchronization signal blocks transmitted in the transmission window by the number (Q1) of candidate synchronization signal blocks included in the candidate synchronization signal block group, and then round up (i.e., ceil (M/Q1)) or down (i.e., floor (M/Q1)) or round down (i.e., round (M/Q1)) the result as the number of repetitions of the candidate synchronization signal block group in the transmission window.

In one implementation, the terminal is configured to receive first signaling sent by the network device, where the first signaling may be used to indicate a number of repetitions of the candidate synchronization signal block group within the transmission window. I.e. the terminal may determine the number of repetitions of the candidate synchronization signal block group within the transmission window according to the indication of the first signaling. In this way, the terminal can quickly determine the number of repetitions of the candidate synchronization signal block group within the transmission window according to the indication content of the first signaling. Wherein the first signaling may be a signaling newly defined by a protocol.

In one implementation, the terminal may further determine a number of repetitions of a set of a plurality of candidate synchronization signal block groups within the transmission window, the candidate synchronization signal block groups including a plurality of candidate synchronization signal blocks. In general, the number of candidate synchronization signal block groups included in each set may be the same. Therefore, the terminal determines the number of repetitions of the set within the transmission window, and further determines the number of repetitions of the candidate synchronization signal block group within the transmission window. In this way, the number of repetitions of the terminal candidate synchronization signal block group in the transmission window can be avoided from being indicated by additional signaling, i.e., the signaling is saved.

In one implementation manner, the specific implementation manner of the terminal determining the number of repetitions of the set consisting of multiple candidate synchronization signal block groups within the transmission window may be: determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the time length of the transmission window; and determining the number of times of repetition of the set in the transmission window according to the number of candidate synchronization signal blocks included in the set consisting of the plurality of candidate synchronization signal block groups and the number of candidate synchronization signal blocks transmitted in the transmission window. In general, the number (M) of candidate synchronization signal blocks transmitted within the transmission window may refer to the number of candidate synchronization signal blocks that the terminal can receive at most within the transmission window.

In one implementation, the protocol may specify a number of candidate synchronization signal blocks comprised by a set of multiple candidate synchronization signal block sets (Q2). In general, the number of candidate synchronization signal blocks included in each set may be the same. The terminal may divide the number (M) of candidate synchronization signal blocks transmitted within the transmission window by the number (Q2) of candidate synchronization signal blocks included in the set of candidate synchronization signal block groups, and obtain the result (i.e., M/Q2) as the number of repetitions of the set of candidate synchronization signal block groups within the transmission window. Generally, Q2 is an integer multiple of Q1. For example, when the subcarrier spacing of the candidate synchronization signal block is 30kHz, if the duration of the transmission window is 5ms (M is 20), Q1 is 2, and Q2 is 4, the terminal may determine that the number of repetitions of the set of candidate synchronization signal block groups in the transmission window is 5; if the duration of the transmission window is 4ms (M ═ 16), Q1 is 2, and Q2 is 4, the terminal may determine that the number of repetitions of the set of candidate synchronization signal block groups in the transmission window is 4; if the duration of the transmission window is 3ms (M is 12), Q1 is 2, and Q2 is 4, the terminal may determine that the number of repetitions of the set of candidate synchronization signal block groups in the transmission window is 3; if the duration of the transmission window is 2ms (M is 8), Q1 is 2, and Q2 is 4, the terminal may determine that the number of repetitions of the set of candidate synchronization signal block groups in the transmission window is 2; if the duration of the transmission window is 1ms (M is 4), Q1 is 2, and Q2 is 4, the terminal may determine that the number of repetitions of the set of candidate synchronization signal block groups in the transmission window is 1. For another example, when the subcarrier interval of the candidate synchronization signal block is 15kHz, if the duration of the transmission window is 4ms (M is 8), Q1 is 2, and Q2 is 4, the terminal may determine that the number of repetitions of the candidate synchronization signal block in the transmission window is 2; if the duration of the transmission window is 2ms (M is 4), Q1 is 2, and Q2 is 4, the terminal may determine that the number of repetitions of the candidate synchronization signal block in the transmission window is 1. Alternatively, the terminal may divide the number (M) of candidate synchronization signal blocks transmitted in the transmission window by the number (Q2) of candidate synchronization signal blocks included in the set of multiple candidate synchronization signal block groups, and then take the upper round (i.e., ceil (M/Q2)) or the lower round (i.e., floor (M/Q2)) or the round (i.e., round (M/Q2)) as the number of repetitions of the set of candidate synchronization signal block groups in the transmission window.

In one implementation, the terminal may further receive second signaling from the network device, where the second signaling may be used to indicate a location within the candidate synchronization signal block group where the candidate synchronization signal block is actually transmitted. I.e. the second signalling may be used to indicate the time-frequency position where the candidate synchronization signal block is really transmitted. In this way, the terminal can perform rate configuration (e.g., Physical Downlink Shared Channel (PDSCH) resource mapping), collision processing (e.g., collision processing between a Physical Downlink Control Channel (PDCCH) and the candidate synchronization signal block), or other corresponding processing on the position where the candidate synchronization signal block is really transmitted, which is beneficial to improving the probability of successfully receiving the candidate synchronization signal block at the position where the candidate synchronization signal block is really transmitted. Wherein the second signaling may be existing signaling in the protocol that may be redefined to indicate the location where the candidate synchronization signal block is actually transmitted. Optionally, the second signaling may also be newly defined signaling.

Further, the terminal may determine an extended index of the candidate synchronization signal block and determine a quasi co-site relationship or synchronization signal block index (SS/PBCH block index) of the candidate synchronization signal block. Generally, if multiple candidate synchronization signal blocks are QCL (Quasi Co-Located), they are transmitted by the same beam (beam). In general, multiple candidate sync signal blocks are quasi co-sited, and then they have the same sync signal block index. The synchronization signal block index may be regarded as a beam index. The sync signal block index may be determined by

Given thatIn

For the PBCH-DMRS sequence index,

mod represents a modulo or remainder operation (modulo) for the number of candidate sync signal blocks in the set of candidate sync signal blocks; or the sync signal block index may be indexed by

Is given in

For the candidate synchronization signal block index(s),

mod represents a modulo or remainder operation (modulo) for the number of synchronization signal blocks in the set of candidate synchronization signal blocks. In general terms, the amount of the solvent to be used,

may be given by the high-level parameter ssbpotitionqcl-Relationship-r 16. After the terminal obtains the synchronization signal block index or the beam index, it may further obtain other channels/signals corresponding to the synchronization signal block index or the beam index, such as corresponding PDCCH monitoring time, Physical Random Access Channel (PRACH) sending time, and the like, so as to improve system coverage and flexibility; the terminal can also combine the measurement results of the same synchronous signal blocks or beams, thereby improving the measurement performance.

In one implementation, an extension index (or called number) of a candidate synchronization signal block is determined, and a quasi-co-site address relationship or a synchronization signal block index of the candidate synchronization signal block is determined according to the extension index of the candidate synchronization signal block. Generally, if multiple candidate synchronization signal blocks are co-sited, then the multiple candidate synchronization signal blocks are transmitted from the same beam (beam).

In one implementation, the specific implementation manner of determining the extension index of the candidate synchronization signal block may be: according to the duration (or called duration) of the extended transmission window, the duration of the transmission window and the period of the transmission window, determining that the extended index of the candidate synchronization signal block is i-X1 i1+ i2, where X1 is the number of the candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the extended transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the aforementioned candidate synchronization signal block index. The duration of the extended transmission window may be a higher layer configured duration or period or duration. In general, the duration of the extended transmission window may be a positive integer multiple of the period of the transmission window, or a positive integer multiple of the period of the half-frames (periodicity of the half frames for reception of the SS/PBCH blocks) received by the candidate synchronization signal block. Since the duration of the extended transmission window may be a positive integer multiple of the period of the transmission window, there may be multiple transmission windows within the extended transmission window, and the index of the transmission window within the duration of the extended transmission window (i.e., i1) may be derived from both the duration of the extended transmission window and the period of the transmission window.

In one implementation, the specific implementation manner of determining the extension index of the candidate synchronization signal block may be: according to the duration of the extended transmission window and the period of the received half frame or frame of the candidate synchronization signal block, determining the extended index of the candidate synchronization signal block as i ═ X2 × i3+ i4, wherein X2 is the number or maximum number of candidate synchronization signal blocks in a half frame or a frame, i3 is the index of the period of the received half frame or frame of the candidate synchronization signal block in the duration of the extended transmission window, and i4 is the index of the aforementioned candidate synchronization signal block. The duration of the extended transmission window may be a higher layer configured duration or period or duration. In general, the duration of the extended transmission window may be a positive integer multiple of the period of the transmission window, or a positive integer multiple of the period of the half-frames (periodicity of the half frames for reception of the SS/PBCH blocks) received by the candidate synchronization signal block.

In one implementation, the quasi co-sited of a candidate synchronization signal block is determined according to an extended index of the candidate synchronization signal blockThe specific implementation of the address relationship may be: a plurality of candidate synchronization signal blocks have a quasi co-site relationship if they have the same value (a mod Q), where a is the spreading index of the candidate synchronization signal block, Q is a high level parameter, and mod represents a modulo or remainder operation (modulo). In general, Q may be the number of candidate synchronization signal blocks within the set of candidate synchronization signal blocks. Q may be given by a high level parameter ssbPositionQCL-Relationship-r16, i.e., Q is

In one implementation manner, the specific implementation manner of determining the synchronization signal block index of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block may be: determining a synchronization signal block index of the candidate synchronization signal block as (A mod Q), wherein A is an extension index of the candidate synchronization signal block, Q is a high-level parameter, and mod represents a modulo or remainder operation (modulo). In general, Q may be the number of candidate synchronization signal blocks within the set of candidate synchronization signal blocks. Q may be given by a high level parameter ssbPositionQCL-Relationship-r16, i.e., Q is

By extending the transmission window, the candidate synchronization signal block index may be extended, i.e. an extended index of the candidate synchronization signal block may be obtained. That is, by expanding the transmission window, the candidate synchronization signal block index may be expanded in the time domain, corresponding to the time required for a round of multi-beam transmission of the candidate synchronization signal block being expanded, such as from 5 milliseconds to 20 milliseconds. Therefore, the downlink transmission can be dispersed in a longer time period, and the uplink and downlink proportion of the system can be optimized. For example, when the subcarrier spacing of a candidate synchronization signal block is 30kHz, if the duration of a transmission window is 5ms, the period of the transmission window is 10ms, and the duration of an extended transmission window is 20ms, it is determined that the extended index of the candidate synchronization signal block is i-20 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 19; if the duration of the transmission window is 4ms, the period of the transmission window is 10ms, and the duration of the extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i 16 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 15; if the duration of a transmission window is 3ms, the period of the transmission window is 10ms, and the duration of an extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i 12 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 11; if the duration of a transmission window is 2ms, the period of the transmission window is 10ms, and the duration of an extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i 8 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 7; if the duration of a transmission window is 1ms, the period of the transmission window is 10ms, and the duration of an extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i4 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 3; if the duration of the transmission window is 0.5ms, the period of the transmission window is 10ms, and the duration of the extended transmission window is 20ms, it is determined that the extended index of the candidate synchronization signal block is i-2 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 1.

For another example, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, if the duration of the transmission window is 5ms, the period of the transmission window is 10ms, and the duration of the extended transmission window is 20ms, it is determined that the extended index of the candidate synchronization signal block is i 10 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 9; if the duration of the transmission window is 4ms, the period of the transmission window is 10ms, and the duration of the extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i 8 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 7; if the duration of a transmission window is 3ms, the period of the transmission window is 10ms, and the duration of an extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i 6 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 5; if the duration of a transmission window is 2ms, the period of the transmission window is 10ms, and the duration of an extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i4 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 3; if the duration of a transmission window is 1ms, the period of the transmission window is 10ms, and the duration of an extended transmission window is 20ms, determining that the extended index of the candidate synchronization signal block is i2 × i1+ i2, where i1 may be 0 or 1, and i2 may be an integer from 0 to 1; if the duration of the transmission window is 0.5ms, the period of the transmission window is 10ms, and the duration of the extended transmission window is 20ms, it is determined that the extended index of the candidate synchronization signal block is i1+ i2, where i1 may be 0 or 1, and i2 is 0.

By implementing the embodiment of the invention, the terminal can receive more candidate synchronous signal blocks, thereby being beneficial to improving the coverage performance of the candidate synchronous signal blocks.

Referring to fig. 2, fig. 2 is a flowchart illustrating another method for processing a candidate synchronization signal block according to an embodiment of the present invention. The method is applied to a terminal, and specifically, as shown in fig. 2, the method for processing a candidate synchronization signal block according to the embodiment of the present invention may include, but is not limited to, the following steps:

s201, the terminal determines a candidate synchronization signal block index (or called number) according to the load of the PBCH-DMRS sequence and/or the PBCH, wherein the candidate synchronization signal block index is from 0 to N-1, and N is 4, 8, 10, 16, 20, 32 or 40. The candidate sync signal block index may refer to an index of the candidate sync signal block within one field or one frame.

Specifically, when the terminal initially accesses, the terminal may determine one or more candidate synchronization Signal block indexes of N candidate synchronization Signal blocks in one field or one frame according to a Physical Broadcast Channel (PBCH) -Demodulation Reference Signal (DMRS) sequence and a load of the PBCH.

In one implementation, the candidate sync signal block index may have 2 (when N is equal to 4) or 3 (when N is greater than 4) Least Significant Bit (LSB) bits and/or 1, 2, or 3 Most Significant Bit (MSB) bits.

In one implementation, a specific embodiment in which a terminal determines a candidate synchronization signal block index according to a load of a PBCH-DMRS sequence and/or a PBCH includes: from the PBCH-DMRS sequence, 2 (when N equals 4) or 3 (when N is greater than 4) LSB bits of the candidate synchronization signal block index are determined.

In one implementation, a specific embodiment in which a terminal determines a candidate synchronization signal block index according to a load of a PBCH-DMRS sequence and/or a PBCH includes: the 1, 2 or 3 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

In one implementation, the value of N may be related to the subcarrier spacing of the candidate synchronization signal block. The subcarrier spacing of the candidate synchronization signal block may be 15kHz, 30kHz, or other values, which is not limited in this embodiment of the present invention. Specifically, in the case where the subcarrier spacing of the candidate synchronization signal block is 15kHz, N may be 4, 8, 10, 16, or 20. In the case where the subcarrier spacing of the candidate synchronization signal block is 30kHz, N may be 4, 8, 10, 16, 20, 32, or 40.

It should be noted that N may refer to the maximum number of candidate synchronization signal blocks that can be transmitted in a radio frame, or N may refer to the maximum number of candidate synchronization signal blocks that can be transmitted in a half radio frame. Specifically, in the case that the subcarrier spacing of the candidate synchronization signal block is 15kHz, a maximum of 4 or 8 or 10 candidate synchronization signal blocks can be transmitted in a half radio frame, and a maximum of 16 or 20 candidate synchronization signal blocks can be transmitted in 1 radio frame. In the case of a candidate sync signal block with a subcarrier spacing of 30kHz, a maximum of 4, 8, 10, 16, or 20 candidate sync signal blocks may be transmitted in half a radio frame and a maximum of 32 or 40 candidate sync signal blocks may be transmitted in 1 radio frame.

In one implementation, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, if N is 4, that is, a value of 2 bits can indicate the candidate synchronization signal block index in a half radio frame, so 2 LSB bits are determined according to the PBCH-DMRS sequence.

In one implementation, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, if N is 8, that is, a value of 3 bits can indicate the candidate synchronization signal block index in a half radio frame, and therefore, 3 LSB bits are determined according to the PBCH-DMRS sequence.

In one implementation, when the subcarrier spacing of the candidate synchronization signal block is 15kHz, if N is 10, that is, the candidate synchronization signal block index in a half radio frame can be represented by a 4-bit value, so that 3 LSB bits are determined according to the PBCH-DMRS sequence, and 1 MSB bit is determined according to the load of PBCH. In this case, the terminal may load PBCH with bits

1 MSB bit as the candidate sync block index in half a radio frame.

When the subcarrier interval of the candidate synchronization signal block is 15kHz, if N is 16, that is, if the candidate synchronization signal block index in 1 radio frame can be represented by a 4-bit value, 3 LSB bits are determined from the PBCH-DMRS sequence, and 1 MSB bit is determined from the load of the PBCH. In this case, the terminal may load PBCH with bits

1 MSB bit, which is a candidate sync signal block index in 1 radio frame.

When the subcarrier interval of the candidate synchronization signal block is 15kHz, if N is 20, that is, if the candidate synchronization signal block index in 1 radio frame can be represented by a value of 5 bits, 3 LSB bits are determined from the PBCH-DMRS sequence, and 2 MSB bits are determined from the load of PBCH. In this case, the terminal may load PBCH with bits

2 MSB bits, which are candidate sync signal block indices in 1 radio frame.

In the above manner, the MSB bits of the candidate synchronization signal block index may be carried by 1 or 2 bits in the PBCH payload.

When the subcarrier interval of the candidate synchronization signal block is 30kHz, if N is 4, that is, the candidate synchronization signal block index in the half radio frame can be represented by a value of 2 bits, and thus 2 LSB bits are determined from the PBCH-DMRS sequence.

When the subcarrier interval of the candidate synchronization signal block is 30kHz, if N is 8, that is, the candidate synchronization signal block index in the half radio frame can be represented by a value of 3 bits, and therefore, 3 LSB bits are determined from the PBCH-DMRS sequence.

When the subcarrier interval of the candidate synchronization signal block is 30kHz, if N is 10, that is, if the candidate synchronization signal block index in a half radio frame can be represented by a 4-bit value, 3 LSB bits are determined from the PBCH-DMRS sequence, and 1 MSB bit is determined from the load of the PBCH. In this case, the terminal may load PBCH with bits

1 MSB bit, which is the candidate sync block index in half of the radio frame.

When the subcarrier interval of the candidate synchronization signal block is 30kHz, if N is 16, that is, the candidate synchronization signal block index in a half radio frame can be represented by a 4-bit value, 3 LSB bits are determined from the PBCH-DMRS sequence, and 1 MSB bit is determined from the load of the PBCH. In this case, the terminal may load PBCH with bits

1 MSB bit as the candidate sync block index in half a radio frame.

When the subcarrier interval of the candidate synchronization signal block is 30kHz, if N is 20, that is, the candidate synchronization signal block index in a half radio frame can be represented by a value of 5 bits, and thus 3 LSB bits are determined from the PBCH-DMRS sequence and 2 LSB bits are determined from the load of PBCHThe MSB bit. In this case, the terminal may load PBCH with bits

2 MSB bits, which are candidate sync signal block indices in half a radio frame.

When the subcarrier interval of the candidate synchronization signal block is 30kHz, if N is 32, that is, the candidate synchronization signal block index in 1 radio frame can be represented by a value of 5 bits, and therefore, 3 LSB bits are determined from the PBCH-DMRS sequence, and 2 MSB bits are determined from the load of PBCH. In this case, the terminal may load PBCH with bits

2 MSB bits, which are candidate sync signal block indices in 1 radio frame.

When the subcarrier interval of the candidate synchronization signal block is 30kHz, if N is 40, that is, the candidate synchronization signal block index in 1 radio frame can be represented by a value of 6 bits, and therefore, 3 LSB bits are determined from the PBCH-DMRS sequence, and 3 MSB bits are determined from the load of PBCH. In this case, the terminal may load PBCH with bits

3 MSB bits as candidate synchronization signal block index in 1 radio frame, or PBCH payload bit may be used by the terminal

3 MSB bits as candidate Sync Signal Block index in 1 radio frame, where

Bits indicated for a field.

In the above manner, the MSB bits of the candidate synchronization signal block index may be carried by 1, 2, or 3 bits in the PBCH payload.

By implementing the embodiment of the invention, the candidate synchronization signal block indexes can be determined through the load of the PBCH-DMRS sequence and/or the PBCH, namely, the network equipment does not need to indicate the terminal candidate synchronization signal block indexes through additional messages or signaling, thereby being beneficial to reducing the data volume transmitted in the network.

Further, the terminal may determine an extended index of a candidate synchronization signal block and determine a quasi co-site relationship or a synchronization signal block index (SS/PBCH block index) of the candidate synchronization signal block. Generally, if multiple candidate synchronization signal blocks are co-sited, then the multiple candidate synchronization signal blocks are emitted by the same beam (beam). In general, multiple candidate synchronization signal blocks are quasi co-sited, then they have the same synchronization signal block index. The synchronization signal block index may be regarded as a beam index.

In one implementation, the terminal may determine an extension index (or called number) of a candidate synchronization signal block, and determine a quasi-co-site relationship or a synchronization signal block index of the candidate synchronization signal block according to the extension index of the candidate synchronization signal block. Generally, if multiple candidate synchronization signal blocks are co-sited, they are transmitted by the same beam (beam).

In one implementation manner, the specific implementation manner of determining the quasi-co-site relationship of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block may be: the candidate synchronization signal blocks have a quasi co-site relationship if they have the same (A mod Q) value, where A is the extension index of the candidate synchronization signal block and Q is a high level parameter. In general, Q may be the number of candidate synchronization signal blocks within the set of candidate synchronization signal blocks. Q may be given by a high level parameter ssbPositionQCL-Relationship-r16, i.e., Q is

In one implementation manner, the specific implementation manner of determining the synchronization signal block index of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block may be: the synchronization signal block index of the candidate synchronization signal block is (a mod Q), where a is the spreading index of the candidate synchronization signal block, Q is a high level parameter, and mod represents a modulo or remainder operation (modulo). In general, Q may be the number of candidate synchronization signal blocks within the set of candidate synchronization signal blocks. Q may be given by a high level parameter ssbPositionQCL-Relationship-r16, i.e., Q is

Referring to fig. 3, fig. 3 is a schematic structural diagram of a processing apparatus of a candidate sync signal block according to an embodiment of the present invention, where the processing apparatus of the candidate sync signal block may be a terminal or an apparatus (e.g., a chip) having a terminal function. Specifically, as shown in fig. 3, the processing device 30 for candidate synchronization signal blocks may include:

a processing module 301, configured to determine candidate sync signal block indexes from 0 to N-1, where N is 4, 8, 10, 16, 20, 32, or 40.

In one implementation, when the processing module 301 is configured to determine the candidate synchronization signal block index, it may specifically be configured to: and determining the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the load of the PBCH.

In one implementation, where the subcarrier spacing of the candidate synchronization signal block is 15kHz, the N may be 4, 8, 10, 16, or 20.

In one implementation, when the processing module 301 is configured to determine the candidate synchronization signal block index, it may specifically be configured to: 2 or 3 LSB bits of the candidate synchronization signal block index are determined according to the PBCH-DMRS sequence.

In one implementation, when the processing module 301 is configured to determine the candidate synchronization signal block index, it may specifically be configured to: the 1, 2 or 3 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

In one implementation, when the processing module 301 is configured to determine 1, 2, or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH, the processing module may specifically be configured to: if N is 10, determining 1 MSB bit of the candidate synchronization signal block index according to the load of the PBCH; if N is 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 20, 2 MSB bits of the candidate sync signal block index are determined according to the load of the PBCH.

In one implementation, when the processing module 301 is configured to determine the candidate synchronization signal block index, it may specifically be configured to: from the PBCH-DMRS sequence, 2 (when N equals 4) or 3 (when N is greater than 4) LSB bits of the candidate synchronization signal block index are determined.

In one implementation, when the processing module 301 is configured to determine 1, 2, or 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH, the processing module may specifically be configured to: if N is 10 or 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 20, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH; if N is 32, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH; if N is 40, 3 MSB bits of the candidate sync signal block index are determined according to the load of the PBCH.

In one implementation, the processing module 301 may be further configured to determine a number of repetitions of a candidate synchronization signal block group within a transmission window, where the candidate synchronization signal block group may include a plurality of candidate synchronization signal blocks.

In an implementation manner, when the processing module 301 is configured to determine the number of repetitions of the candidate synchronization signal block group in the transmission window, specifically, the processing module may be configured to: and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window.

In one implementation, when the processing module 301 is configured to determine, according to the duration of the transmission window, the number of repetitions of the candidate synchronization signal block group in the transmission window, specifically, the processing module may be configured to: determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the time length of the transmission window; and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the number of the candidate synchronization signal blocks included in the candidate synchronization signal block group and the number of the candidate synchronization signal blocks transmitted in the transmission window.

In one implementation, the processing device 30 of the candidate synchronization signal block may further include a communication module 302. The communication module 302 may be configured to receive a first signaling sent by a network device, where the first signaling may be used to indicate a number of repetitions of a candidate synchronization signal block group within a transmission window.

In one implementation, the processing module 301 may be further configured to determine a number of repetitions of a set of multiple candidate synchronization signal block groups within a transmission window, where the candidate synchronization signal block groups may include multiple candidate synchronization signal blocks.

In one implementation, when the processing module 301 is configured to determine the number of repetitions of a set composed of multiple candidate synchronization signal block groups in a transmission window, it may specifically be configured to: determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the time length of the transmission window; and determining the repetition times of the set in the transmission window according to the number of the candidate synchronization signal blocks included in the set consisting of a plurality of candidate synchronization signal block groups and the number of the candidate synchronization signal blocks transmitted in the transmission window.

In one implementation, the processing module 301 may be further configured to determine an extension index of a candidate synchronization signal block, and determine a quasi-co-site relationship or a synchronization signal block index of the candidate synchronization signal block according to the extension index of the candidate synchronization signal block.

In an implementation manner, when the processing module 301 is configured to determine an extension index of a candidate synchronization signal block, it may specifically be configured to: according to the duration of the extended transmission window, the duration of the transmission window and the period of the transmission window, determining the extended index of the candidate synchronization signal block as i ═ X1 × i1+ i2, wherein X1 is the number of the candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the extended transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

In an implementation manner, when the processing module 301 is configured to determine an extension index of a candidate synchronization signal block, it may specifically be configured to: according to the duration of the extended transmission window and the period of the received half frame or frame of the candidate synchronization signal block, determining the extended index of the candidate synchronization signal block as i ═ X2 × i3+ i4, wherein X2 is the number or maximum number of candidate synchronization signal blocks in a half frame or a frame, i3 is the index of the period of the received half frame or frame of the candidate synchronization signal block in the duration of the extended transmission window, and i4 is the index of the aforementioned candidate synchronization signal block.

In one implementation, when the processing module 301 is configured to determine the quasi co-site relationship of the candidate synchronization signal block according to the extension index of the candidate synchronization signal block, specifically, the processing module may be configured to: a plurality of candidate synchronization signal blocks have a quasi co-site relationship if they have the same value (a mod Q), where a is the spreading index of the candidate synchronization signal block, Q is a high level parameter, and mod represents a modulo or remainder operation (modulo).

In one implementation, when the processing module 301 is configured to determine the synchronization signal block index of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block, specifically, the processing module may be configured to: determining a synchronization signal block index of the candidate synchronization signal block as (A mod Q), wherein A is an extension index of the candidate synchronization signal block, Q is a high-level parameter, and mod represents a modulo or remainder operation (modulo).

The embodiments of the present invention and the embodiments of the method shown in fig. 1-2 are based on the same concept, and the technical effects thereof are also the same, and for the specific principle, reference is made to the description of the embodiments shown in fig. 1-2, which is not repeated herein.

Referring to fig. 4, fig. 4 is a schematic structural diagram of a terminal according to an embodiment of the present invention. The terminal 40 may include a memory 401, a processor 402, and a communication interface 403, the memory 401, the processor 402, and the communication interface 403 being connected by one or more communication buses. Wherein the communication interface 403 is controlled by the processor 402 for transceiving information.

Memory 401 may include both read-only memory and random-access memory, and provides instructions and data to processor 402. A portion of the memory 401 may also include non-volatile random access memory.

The Processor 402 may be a Central Processing Unit (CPU), and the Processor 402 may also be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor, and optionally, the processor 402 may be any conventional processor or the like. Wherein:

a memory 401 for storing program instructions.

A processor 402 for calling program instructions stored in the memory 401 to cause the terminal 40 to perform the following operations:

candidate sync signal block indices are determined, the candidate sync signal block indices being from 0 to N-1, with N being 4, 8, 10, 16, 20, 32, or 40.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to perform the following operations when determining the candidate synchronization signal block index: and determining the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the load of the PBCH.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to perform the following operations when determining the candidate synchronization signal block index: from the PBCH-DMRS sequence, 2 (when N equals 4) or 3 (when N is greater than 4) LSB bits of the candidate synchronization signal block index are determined.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to perform the following operations when determining the candidate synchronization signal block index: the 1, 2 or 3 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

In one implementation, processor 402 is configured to call program instructions stored in memory 401 to cause the terminal 40 to determine 1, 2, or 3 MSB bits of a candidate synchronization signal block index according to a load of a PBCH, and specifically cause the terminal 40 to: if N is 10, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 20, 2 MSB bits of the candidate sync signal block index are determined according to the load of the PBCH.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to perform the following operations when determining the candidate synchronization signal block index: 2 or 3 LSB bits of the candidate synchronization signal block index are determined according to the PBCH-DMRS sequence.

In one implementation, processor 402 is configured to call program instructions stored in memory 401 to cause the terminal 40 to determine 1, 2, or 3 MSB bits of a candidate synchronization signal block index according to a load of a PBCH, and specifically cause the terminal 40 to: if N is 10 or 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH; if N is 20, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH; if N is 32, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH; if N is 40, 3 MSB bits of the candidate sync signal block index are determined according to the load of the PBCH.

In one implementation, the processor 402 may be further configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to perform the following operations: the number of repetitions of a candidate synchronization signal block group, which may include a plurality of candidate synchronization signal blocks, within a transmission window is determined.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to execute the following operation when determining the number of repetitions of a candidate synchronization signal block group in a transmission window: and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to determine the number of repetitions of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window, and specifically enable the terminal 40 to: determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the time length of the transmission window; and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the number of the candidate synchronization signal blocks included in the candidate synchronization signal block group and the number of the candidate synchronization signal blocks transmitted in the transmission window.

In one implementation, the processor 402 may be further configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to perform the following operations: first signaling sent by a network device is received, and the first signaling can be used for indicating the number of repetitions of a candidate synchronization signal block group within a transmission window.

In one implementation, the processor 402 may be further configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to perform the following operations: the number of repetitions of a set of candidate synchronization signal block sets, which may include a plurality of candidate synchronization signal blocks, within a transmission window is determined.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to perform the following operations when determining the number of repetitions of the set of multiple candidate synchronization signal block groups in the transmission window: determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the time length of the transmission window; and determining the repetition times of the set in the transmission window according to the number of the candidate synchronization signal blocks included in the set consisting of a plurality of candidate synchronization signal block groups and the number of the candidate synchronization signal blocks transmitted in the transmission window.

In one implementation, the processor 402 may be further configured to invoke program instructions stored in the memory 401 to cause the terminal 40 to perform the following operations: and determining the extension index of the candidate synchronous signal block, and determining the quasi co-site relation or synchronous signal block index of the candidate synchronous signal block according to the extension index of the candidate synchronous signal block.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to execute the following operations when determining the extension index of the candidate synchronization signal block: and determining the expansion index of the candidate synchronization signal block as i ═ X1 × i1+ i2 according to the time length of the expanded transmission window, the time length of the transmission window and the period of the transmission window, wherein X1 is the number of the candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the time length of the expanded transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to execute the following operations when determining the extension index of the candidate synchronization signal block: according to the duration of the extended transmission window and the period of the received half frame or frame of the candidate synchronization signal block, determining the extended index of the candidate synchronization signal block as i ═ X2 × i3+ i4, wherein X2 is the number or maximum number of candidate synchronization signal blocks in a half frame or a frame, i3 is the index of the period of the received half frame or frame of the candidate synchronization signal block in the duration of the extended transmission window, and i4 is the index of the aforementioned candidate synchronization signal block.

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to determine the quasi co-site relationship of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block, and specifically enable the terminal 40 to: a plurality of candidate synchronization signal blocks have a quasi co-site relationship if they have the same value (a mod Q), where a is the spreading index of the candidate synchronization signal block, Q is a high level parameter, and mod represents a modulo or remainder operation (modulo).

In one implementation, the processor 402 is configured to call the program instructions stored in the memory 401 to enable the terminal 40 to determine the synchronization signal block index of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block, and specifically, the terminal 40 may be configured to: determining a synchronization signal block index of the candidate synchronization signal block as (A mod Q), wherein A is an extension index of the candidate synchronization signal block, Q is a high-level parameter, and mod represents a modulo or remainder operation (modulo).

It should be noted that details that are not mentioned in the embodiment corresponding to fig. 4 and specific implementation manners of each step may refer to the embodiments shown in fig. 1 to fig. 2 and the foregoing details, and are not repeated here.

Embodiments of the present invention also provide a computer-readable storage medium, in which a computer program is stored, where the computer program includes program instructions, and the program instructions, when executed by a processor, cause the processor to execute the steps executed in the method embodiments shown in fig. 1-2.

While the invention has been described with reference to a number of embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A method for processing a candidate synchronization signal block, the method comprising:

determining a candidate synchronization signal block index, the candidate synchronization signal block index being from 0 to N-1, the N being 4, 8, 10, 16, 20, 32 or 40;

wherein, in the case that the subcarrier spacing of the candidate synchronization signal block is 15kHz, the N is 4, 8, 10, 16 or 20; and/or, in case the subcarrier spacing of the candidate synchronization signal block is 30kHz, said N is 4, 8, 10, 16, 20, 32 or 40.

2. The method of claim 1, wherein determining the candidate synchronization signal block index comprises:

and determining the candidate synchronization signal block index according to the PBCH-DMRS sequence and/or the load of the PBCH.

3. The method of claim 1, wherein determining the candidate synchronization signal block index comprises:

2 or 3 LSB bits of the candidate synchronization signal block index are determined according to the PBCH-DMRS sequence.

4. The method of claim 1, wherein determining the candidate synchronization signal block index comprises:

the 1, 2 or 3 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

5. The method of claim 4, wherein the subcarrier spacing of the candidate synchronization signal block is 15 kHz; determining 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of PBCH includes:

if the N is 10, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH;

if the N is 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH;

if the N is 20, 2 MSB bits of the candidate synchronization signal block index are determined according to the load of the PBCH.

6. The method of claim 4, wherein the subcarrier spacing of the candidate synchronization signal block is 30 kHz; determining 1, 2 or 3 MSB bits of the candidate synchronization signal block index according to the load of PBCH includes:

if the N is 10 or 16, determining 1 MSB bit of the candidate synchronization signal block index according to the load of PBCH;

if the N is 20, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH;

if the N is 32, determining 2 MSB bits of the candidate synchronization signal block index according to the load of PBCH;

if the N is 40, determining 3 MSB bits of the candidate synchronization signal block index according to the load of the PBCH.

7. The method of claim 1, further comprising:

determining a number of repetitions of a candidate synchronization signal block group within a transmission window, the candidate synchronization signal block group comprising a plurality of candidate synchronization signal blocks.

8. The method of claim 7, wherein determining the number of repetitions of the candidate synchronization signal block group within the transmission window comprises:

and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the duration of the transmission window.

9. The method of claim 8, wherein determining the number of repetitions of the candidate synchronization signal block within the transmission window according to the duration of the transmission window comprises:

determining the number of candidate synchronous signal blocks transmitted in a transmission window according to the duration of the transmission window;

and determining the repetition times of the candidate synchronization signal block group in the transmission window according to the number of the candidate synchronization signal blocks included in the candidate synchronization signal block group and the number of the candidate synchronization signal blocks transmitted in the transmission window.

10. The method of claim 7, further comprising:

receiving a first signaling sent by a network device, where the first signaling is used to indicate the number of repetitions of the candidate synchronization signal block group within the transmission window.

11. The method of claim 1, further comprising:

determining a number of repetitions of a set of candidate synchronization signal block groups within a transmission window, the candidate synchronization signal block groups including a plurality of candidate synchronization signal blocks.

12. The method of claim 11, wherein determining the number of repetitions of the set of candidate synchronization signal block groups within the transmission window comprises:

and determining the repetition times of the set in the transmission window according to the number of the candidate synchronization signal blocks included in the set consisting of a plurality of candidate synchronization signal block groups and the number of the candidate synchronization signal blocks transmitted in the transmission window.

13. The method of claim 1, further comprising:

and determining the extension index of the candidate synchronous signal block, and determining the quasi co-site relation or synchronous signal block index of the candidate synchronous signal block according to the extension index of the candidate synchronous signal block.

14. The method of claim 13, wherein determining the extended index of the candidate synchronization signal block comprises:

determining an extension index of a candidate synchronization signal block as i ═ X1 × i1+ i2 according to the duration of an extended transmission window, the duration of the transmission window and the period of the transmission window, wherein X1 is the number of candidate synchronization signal blocks in the transmission window, i1 is the index of the transmission window in the duration of the extended transmission window, and i2 is the index of the candidate synchronization signal block in the transmission window or the index of the candidate synchronization signal block.

15. The method of claim 13, wherein determining the extension index of the candidate synchronization signal block comprises:

according to the duration of the extended transmission window and the period of the received half frame or frame of the candidate synchronization signal block, determining the extended index of the candidate synchronization signal block as i ═ X2 × i3+ i4, wherein X2 is the number or maximum number of candidate synchronization signal blocks in a half frame or a frame, i3 is the index of the period of the received half frame or frame of the candidate synchronization signal block within the duration of the extended transmission window, and i4 is the candidate synchronization signal block index.

16. The method of claim 13, wherein the determining the quasi-co-site relationship of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block comprises:

a plurality of candidate synchronization signal blocks have a quasi co-site relationship if they have the same value (a mod Q), where a is the spreading index of the candidate synchronization signal block, Q is a high level parameter, and mod represents a modulo or remainder operation (modulo).

17. The method of claim 13, wherein determining the synchronization signal block index of the candidate synchronization signal block according to the extended index of the candidate synchronization signal block comprises:

determining a synchronization signal block index of the candidate synchronization signal block as (A mod Q), wherein A is an extension index of the candidate synchronization signal block, Q is a high-level parameter, and mod represents a modulo or remainder operation (modulo).

18. An apparatus for processing a candidate synchronization signal block, the apparatus comprising means for performing the method of any of claims 1-17.

19. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program comprising program instructions that, when executed by a processor, cause the processor to carry out the method according to any one of claims 1 to 17.

20. A terminal, comprising a memory for storing a computer program comprising program instructions and a processor configured to invoke the program instructions to perform the method of any of claims 1 to 17.