CN113630876B - Data processing method and device - Google Patents

Data processing method and device Download PDF

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CN113630876B
CN113630876B CN202010383949.XA CN202010383949A CN113630876B CN 113630876 B CN113630876 B CN 113630876B CN 202010383949 A CN202010383949 A CN 202010383949A CN 113630876 B CN113630876 B CN 113630876B
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synchronization signal
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CN113630876A (en
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周化雨
潘振岗
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Spreadtrum Communications Shanghai Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/20—Control channels or signalling for resource management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/003—Arrangements for allocating sub-channels of the transmission path
    • H04L5/0048—Allocation of pilot signals, i.e. of signals known to the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/0091—Signaling for the administration of the divided path
    • H04L5/0094—Indication of how sub-channels of the path are allocated
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation
    • H04W72/044—Wireless resource allocation based on the type of the allocated resource
    • H04W72/046—Wireless resource allocation based on the type of the allocated resource the resource being in the space domain, e.g. beams

Abstract

The embodiment of the application provides a data processing method and a device, wherein the method is applied to terminal equipment and comprises the following steps: and determining the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap, wherein X is a positive integer greater than or equal to 1. According to the scheme provided by the embodiment of the application, the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap is determined, so that the actually transmitted synchronization signal block indexes or the actually transmitted beam indexes corresponding to all bits in the synchronization signal block bitmap can be further determined.

Description

Data processing method and device
Technical Field
The embodiment of the application relates to the technical field of communication, in particular to a data processing method and device.
Background
In an R16 unlicensed spectrum (Release 16 NR-U), a terminal device may obtain a Quasi Co-site (QCL) relationship parameter Q of a synchronization signal block through a signaling sent by a base station, so as to obtain beam repetition information of the synchronization signal block.
In Release 16NR-U, the Q value limits the number of bits available for the "true transmitted synchronization Signal Block bitmap". In Release 16NR-U, the really transmitted sync block bitmap has 8 bits, but only the first Q bits are valid, indicating the really transmitted sync block index or the really transmitted beam index within a sync block burst or within a Discovery burst transmission window (Discovery burst transmission window). The UE determines the index of the synchronization signal block according to the synchronization signal block bitmap which is really transmitted, and further determines the position of a candidate synchronization signal block which needs to be really transmitted, so that the resource mapping (rate matching) of the PDSCH is carried out aiming at the position of the candidate synchronization signal block, or whether the candidate synchronization signal block is collided with the PDCCH or not is determined.
In the unlicensed spectrum, how to determine the actually transmitted synchronization signal block index or the actually transmitted beam index according to the actually transmitted synchronization signal block bitmap is an urgent problem to be solved.
Disclosure of Invention
Embodiments of the present application provide a data processing method and apparatus, so as to solve a problem how to determine a synchronization signal block index that is actually transmitted or a beam index that is actually transmitted according to a synchronization signal block bitmap that is actually transmitted.
In a first aspect, an embodiment of the present application provides a data processing method, which is applied to a terminal device, and includes:
and determining the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap, wherein X is a positive integer greater than or equal to 1.
In one possible embodiment, the method further comprises:
and determining a Q value of a quasi-common-site parameter according to the X.
In a possible implementation manner, determining a value of a quasi co-site parameter Q according to the X includes:
determining the Q value from the X, in a set of Q values.
In one possible implementation, the synchronization signal block bitmap includes 16 bits.
In one possible implementation, each bit in the synchronization signal block bitmap corresponds to an index or beam index of X synchronization signal blocks.
In one possible implementation, the Q value belongs to a set of Q values.
In one possible implementation, the elements in the set of Q values are candidates for the Q value.
In one possible embodiment, X =1.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,12.
In one possible embodiment of the method according to the invention,
elements of the set of Q values comprise 2,4,8,16; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 3,4,6,12.
In one possible embodiment, X =2.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16,32; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,24; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,5,6,10,15,30.
In one possible embodiment of the method according to the invention,
elements of the set of Q values comprise 4,8,16,32; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 3,6,9,18; alternatively, the first and second liquid crystal display panels may be,
elements of the set of Q values comprise 4,5,10,20; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 6,8,12,24; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 5,10,15,30.
In one possible embodiment, X =4.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16,32,64; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,9,12,18,36; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20,40; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,16,24,48; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18,27,54; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60.
In one possible embodiment of the method according to the invention,
elements of the set of Q values comprise 8,16,32,64; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 9,12,18,36; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 5,10,20,40; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 8,12,24,48; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 9,18,27,54; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 15,20,30,60.
In a second aspect, an embodiment of the present application provides a data processing apparatus, including:
and the processing module is used for determining the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap, wherein X is a positive integer greater than or equal to 1.
In a possible implementation, the processing module is further configured to:
and determining a Q value of a quasi-common-site parameter according to the X.
In a possible implementation, the processing module is specifically further configured to:
determining the Q value from the X, in a set of Q values.
In one possible implementation, the synchronization signal block bitmap includes 16 bits.
In one possible implementation, each bit in the synchronization signal block bitmap corresponds to an index or beam index of X synchronization signal blocks.
In one possible implementation, the Q value belongs to a set of Q values.
In one possible implementation, the elements in the set of Q values are candidates for the Q value.
In one possible embodiment, X =1.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16; alternatively, the first and second liquid crystal display panels may be,
the elements of the set of Q values are taken from 1,2,3,4,6,12.
In one of the possible embodiments thereof,
elements of the set of Q values comprise 2,4,8,16; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 3,4,6,12.
In one possible embodiment, X =2.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16,32; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18; alternatively, the first and second liquid crystal display panels may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,24; alternatively, the elements of the set of Q values are taken from 1,2,3,5,6,10,15;30.
in one possible embodiment of the method according to the invention,
elements of the set of Q values comprise 4,8,16,32; alternatively, the first and second liquid crystal display panels may be,
elements of the set of Q values comprise 3,6,9,18; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 4,5,10,20; alternatively, the first and second liquid crystal display panels may be,
elements of the set of Q values comprise 6,8,12,24; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 5,10,15,30.
In one possible embodiment, X =4.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16,32,64; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,9,12,18,36; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20,40; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,16,24,48; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18,27,54; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60.
In one possible embodiment of the method according to the invention,
elements of the set of Q values comprise 8,16,32,64; alternatively, the first and second liquid crystal display panels may be,
elements of the set of Q values comprise 9,12,18,36; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 5,10,20,40; alternatively, the first and second liquid crystal display panels may be,
elements of the set of Q values comprise 8,12,24,48; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 9,18,27,54; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 15,20,30,60.
In a third aspect, an embodiment of the present application provides a terminal device, including: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing the computer-executable instructions stored by the memory causes the at least one processor to perform the data processing method of any one of the first aspects.
In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the data processing method according to any one of the first aspect is implemented.
The data processing method provided in the embodiment of the present application can further determine the actually transmitted synchronization signal block index or the actually transmitted beam index corresponding to all bits in the synchronization signal block bitmap by determining the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of an application scenario provided in an embodiment of the present application;
fig. 2 is a schematic flowchart of a data processing method according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application;
fig. 4 is a schematic diagram of a hardware structure of a terminal device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For ease of understanding, the concepts related to the present application will first be explained.
The terminal equipment: the device can be a device which comprises a wireless transceiving function and can be matched with network equipment to provide communication services for users. In particular, a terminal device may refer to a User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a User terminal, a wireless communication device, a User agent, or a User Equipment. For example, the terminal device may be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with Wireless communication capability, a computing device or other processing device connected to a Wireless modem, an in-vehicle device, a wearable device, a terminal device in a future 5G network or a network after 5G, and so on.
A network device: the Network device may be a device for communicating with the terminal device, for example, the Network device may be a Base Station (BTS) in a Global System for Mobile Communication (GSM) or Code Division Multiple Access (CDMA) Communication System, a Base Station (NodeB, NB) in a Wideband Code Division Multiple Access (WCDMA) System, an evolved Node B (eNB, or eNodeB) in an LTE System, or the Network device may be a relay Station, an Access point, a vehicle-mounted device, a wearable device, a Network-side device in a future 5G Network or a Network after 5G Network, or a Network device in a future evolved Public Land Mobile Network (PLMN) Network, and the like.
The Network device related in the embodiment of the present application may also be referred to as a Radio Access Network (RAN) device. The RAN equipment is connected with the terminal equipment and used for receiving data of the terminal equipment and sending the data to the core network equipment. RAN devices correspond to different devices in different communication systems, for example, a base station and a base station Controller in a 2G system, a base station and a Radio Network Controller (RNC) in a 3G system, an evolved Node B (eNB) in a 4G system, and an access Network device (e.g., a gNB, a central unit CU, a distributed unit DU) in a 5G system, such as an NR.
Next, a description will be given of a scenario to which the method of the present application is applied, with reference to fig. 1.
Fig. 1 is a schematic diagram of an application scenario provided in an embodiment of the present application. Referring to fig. 1, the network device 101 and the terminal device 102 are included, and wireless communication can be performed between the network device 101 and the terminal device 102.
The Network including the Network device 101 and the terminal device 102 may also be referred to as a Non-Terrestrial communication Network (NTN), where NTN refers to a communication Network between the terminal device and a satellite (which may also be referred to as a Network device).
It is understood that the technical solution of the embodiment of the present application can be applied to NR communication technology, where NR refers to a new Generation radio access network technology, and can be applied to a future evolution network, such as the fifth Generation Mobile communication (5 g) system in the future. The scheme in the embodiment of the application can also be applied to other Wireless communication networks such as Wireless Fidelity (WIFI) and Long Term Evolution (LTE), and the corresponding names can also be replaced by the names of the corresponding functions in other Wireless communication networks.
The network architecture and the service scenario described in the embodiment of the present application are for more clearly illustrating the technical solution of the embodiment of the present application, and do not form a limitation on the technical solution provided in the embodiment of the present application, and as a person of ordinary skill in the art knows that along with the evolution of the network architecture and the appearance of a new service scenario, the technical solution provided in the embodiment of the present application is also applicable to similar technical problems.
In Rel-15 NR, a synchronization signal and a broadcast channel form a synchronization signal block, so that a beam sweeping function is introduced.
Through a Primary Synchronization Signal (PSS) and a Secondary Synchronization Signal (SSS), a UE obtains time-frequency Synchronization of a cell and obtains a physical layer cell ID of the cell, which is generally referred to as cell search.
The PSS, SSS and Physical Broadcast Channel (PBCH) constitute one SS/PBCH block (synchronization signal block).
Each synchronization signal block has a predetermined time domain position. This time domain location may also be referred to as a candidate synchronization signal block. A plurality of sync signal blocks constitute one SS-burst. A plurality of synchronization signal blocks constitute a synchronization signal burst. The plurality of synchronization signal bursts constitute an SS-burst-set (set of synchronization signal bursts). The time domain positions of the Lmax sync signal blocks are fixed within a 5ms window. The time domain position indices of the Lmax sync signal blocks are arranged consecutively, from 0 to Lmax-1. The transmission time instant of a synchronization signal block within this 5ms window is fixed and the index is also fixed.
Generally, a beam sweeping (beam sweeping) manner is adopted when the base station transmits the synchronization signal block, that is, the base station transmits the synchronization signal block at different time domain positions through different beams, and accordingly, the UE can measure the different beams and sense on which beam the received signal is strongest.
In NR licensed spectrum (also known as non-shared spectrum access), the UE obtains 5ms intra-timing information by obtaining candidate synchronization signal block indices. In the licensed spectrum, the candidate synchronization signal block indices are related to Lmax candidate positions of the synchronization signal block. When Lmax =4, the lower two bits (2 LSBs) of the candidate synchronization signal block index are carried in PBCH-DMRS (PBCH demodulation reference signal); when Lmax is greater than 4, the lower three bits (3 LSBs) of the candidate synchronization signal block index are carried in PBCH-DMRS; when Lmax =64, the upper three bits (3 MSBs) of the candidate synchronization signal block index are carried in PBCH payload (payload) or MIB. At this time, the number of candidate sync signal block indexes is equal to the number of sync signal block indexes.
In NR unlicensed spectrum (NR-U), also called shared spectrum access, the UE obtains 5ms inner timing information by acquiring candidate synchronization signal block index. In the unlicensed spectrum, candidate sync signal blocks within a half-frame are numbered in order from 0 to Lmax-1. Lmax =10 when the subcarrier spacing of the synchronization signal block is 15 kHz; when the subcarrier spacing of the synchronization signal block is 30kHz, lmax =20. The UE determines the 3LSB bits of a candidate synchronization signal block index within a half-frame, by the index of the PBCH DMRS sequence (one-to-one mapping). For Lmax =10, the UE determines 1 MSB bit of a candidate synchronization signal block index within a half frame by PBCH payload bits
Figure BDA0002483218750000083
For Lmax =20, the ue determines 2 MSB bits of a candidate synchronization signal block index within a half frame by PBCH load bit ≥>
Figure BDA0002483218750000082
In the unlicensed spectrum of NR, the candidate sync signal block index and the sync signal block index are different, the candidate sync signal block index representing an index of the sync signal block at a candidate position, and the sync signal block index representing a beam index of the sync signal block. At this time, the number of candidate sync signal block indexes may be greater than the number of sync signal block indexes. The synchronization signal block may be a synchronization signal block in a window (e.g., a discovery burst transmission window), so that the number of candidate synchronization signal block indexes is reduced, and the UE complexity is reduced.
In the unlicensed spectrum, a base station performs Listen Before Transmit (LBT) or Channel Access Assessment (CAA) Before transmitting a synchronization signal block, and the base station can transmit the synchronization signal block only when monitoring that a Channel is idle. It is for LBT reason that a window is predefined, and there are more candidate synchronization signal block positions (or indexes) in the window than the actual synchronization signal blocks to be transmitted, and when the base station detects that the channel is busy, the base station can continue to monitor until the channel is idle, and then transmit the synchronization signal blocks at the subsequent candidate synchronization signal block positions.
On the other hand, in the unlicensed Spectrum, since the Power Spectral Density (PSD) is limited, it is difficult to use more narrower beams to achieve the coverage requirement, and therefore, the base station often needs to perform beam repetition (beam repetition) to improve the coverage of the synchronization signal block. Generally, the base station may notify the UE of the beam repetition information of the synchronization signal block, so that the UE knows which measurement values of the synchronization signal block can be averaged during measurement (the measurement values of the synchronization signal block transmitted by using the same beam can be averaged), and the base station may also have more transmission occasions of the PDCCH associated with the synchronization signal block, because the UE needs to monitor multiple PDCCHs associated with multiple synchronization signal blocks transmitted by using the same beam.
In R16 NR-U, the beam repetition information of the synchronization signal block is notified to the UE through a synchronization signal block QCL (Quasi Co-Location) relation parameter, for example, the synchronization signal block QCL relation parameter is Q, the UE obtains the Q value through base station signaling, and if the values of the candidate synchronization signal block indexes modulo Q (the remainder is divided by Q) of two synchronization signal blocks are the same, the two synchronization signal blocks are QCL, or beam repetition, or the synchronization signal block indexes (also called beam indexes) are the same.
In general, the value of the candidate synchronization signal block index modulo Q is referred to as the synchronization signal block index (also called the beam index). The largest sync signal block index is equal to the largest Q value. The selectable Q values are integer factors of the maximum Q value, for example, in the NR unlicensed spectrum of Release 16, the maximum Q value is 8, and the selectable Q values are 8, 4, 2, and 1. In the Release 16NR-U, a Master Information Block (MIB) indicates an optional Q value using only 2 bits.
In Release 16NR-U, the Q value limits the number of bits available for the "true transmitted synchronization Signal Block bitmap". In Release 16NR-U, the really transmitted sync block bitmap has 8 bits, but only the first Q bits are valid, indicating the really transmitted sync block index or the really transmitted beam index within a sync block burst or within a Discovery burst transmission window (Discovery burst transmission window). The UE determines the index of the synchronization signal block according to the synchronization signal block bitmap which is really transmitted, and further determines the position of a candidate synchronization signal block which needs to be really transmitted, so that the resource mapping (rate matching) of the PDSCH is carried out aiming at the position of the candidate synchronization signal block, or whether the candidate synchronization signal block is collided with the PDCCH or not is determined.
In the Frequency Range 2 (Frequency Range 2, fr2) of the licensed spectrum of Release 16NR, i.e., >6GHz and < =52.6GHz band, the actually transmitted synchronization signal Block bitmap is 16 bits (using IE ssb-positioninburst) in the System Information Block 1 (System Information Block 1, sib1), where the first 8 bits are a bitmap of whether the synchronization signal Block in a group is transmitted or not, i.e., inogroup, and the last 8 bits are a bitmap of whether the group is transmitted or not, i.e., groupPresence. However, in the unlicensed spectrum, the actually transmitted synchronization signal block bitmap indicates the actually transmitted synchronization signal block index or the actually transmitted beam index, and therefore, the bitmap indicates whether the synchronization signal block in a group is transmitted or not, wherein one group is Q candidate synchronization signal block positions. In the unlicensed spectrum, how to determine the actually transmitted synchronization signal block index or the actually transmitted beam index according to the actually transmitted synchronization signal block bitmap is an urgent problem to be solved.
In order to solve the above problem, the present application provides a data processing scheme, which determines a synchronization signal block index actually transmitted or a beam index actually transmitted according to the number of synchronization signal blocks corresponding to bits in a synchronization signal block bitmap. The solution of the present application will be explained below with reference to fig. 2.
Fig. 2 is a schematic flowchart of a data processing method provided in an embodiment of the present application, where the method is applied to a terminal device, and as shown in fig. 2, the method may include:
s21, determining the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap, wherein X is a positive integer greater than or equal to 1.
In the authorized spectrum of R16, the actually transmitted synchronization signal block bitmap is 16 bits in SIB1, where the first 8 bits are a bitmap indicating whether a synchronization signal block in a group is transmitted, and the last 8 bits are a bitmap indicating whether a group is transmitted. In the unlicensed spectrum of R16, the actually transmitted synchronization signal block bitmap indicates the actually transmitted synchronization signal block index or the actually transmitted beam index.
In the unlicensed spectrum of R16, the synchronization signal block bitmap includes a plurality of bits, and the plurality of bits can represent a synchronization signal block index that is actually transmitted or a beam index that is actually transmitted. In the embodiment of the present application, by determining the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap, it is possible to determine the actually transmitted synchronization signal blocks or the actually transmitted beam indexes corresponding to all bits in the synchronization signal block bitmap.
The data processing method provided by the embodiment of the application determines the number X of the synchronous signal blocks corresponding to each bit in the synchronous signal block bitmap, the actually transmitted synchronization signal block index or the actually transmitted beam index corresponding to all bits in the synchronization signal block bitmap can be further determined. Since X can be larger than 1, when the synchronization signal block bitmap has N bits, then the number of actually transmitted synchronization signal block indexes or actually transmitted beam indexes that the synchronization signal block bitmap can indicate is X times N.
In some embodiments, the actually transmitted synchronization signal block index or the actually transmitted beam index may be represented by 16 bits, where each bit in the synchronization signal block bitmap corresponds to the index or beam index of X synchronization signal blocks.
In some embodiments, the first 8 bits (inoneegroup, i.e. a bitmap whether or not a group of sync signal blocks is transmitted) and the last 8 bits (grouppanse, i.e. a bitmap whether or not a group is transmitted) of the parameter (ssb-positioninburst) in SIB1 may be combined into 16 bits to represent the really transmitted sync signal block index or the really transmitted beam index, where each bit in the sync signal block bitmap corresponds to the index or beam index of X sync signal blocks.
After the number X of the synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap is determined, the value Q of the quasi-co-site parameter can be determined according to the number X of the synchronization signal blocks corresponding to each bit.
Optionally, the quasi-co-site parameter Q value belongs to a Q value set, and an element in the Q value set is a candidate value of the Q value. After X is determined, the Q value may be determined in the set of Q values according to the value of X.
The number X of sync signal blocks corresponding to each bit in the sync signal block bitmap is a positive integer greater than or equal to 1. According to the difference of the values of X, the maximum Q value is different, so that the elements in the Q value set are different, and further the Q value is different.
The Q value set and the Q value of X under different values will be described below.
To reduce signaling overhead, the actually transmitted synchronization signal block index or the actually transmitted beam index may be represented by 16 bits, and 1 bit in the actually transmitted synchronization signal block bitmap represents 1 synchronization signal block, i.e., X =1 at this time.
When X =1, i.e. 1 bit in the actually transmitted synchronization signal block bitmap represents 1 synchronization signal block, the maximum Q value may be 16 or 12, and the maximum element in the Q value set may be 16 or 12.
In one possible implementation, the elements of the set of Q values are taken from all factors of the maximum Q value. Here, the factor B of the integer a means that the integer a can be divided exactly by B. The reason why the elements of the Q value set are taken from all factors of the maximum Q value is that if the elements of the Q value set are all factors of the maximum Q value, the synchronization signal block indexes of the same position within each group can be kept the same after the candidate synchronization signal block positions (indexes) are grouped into groups according to the maximum Q value.
Optionally, when the maximum Q value is 16, the elements of the Q value set are taken from 1,2,4,8,16, i.e., the optional Q value is selected from 1,2,4,8,16.
Optionally, when the maximum Q value is 12, the elements of the Q value set are taken from 1,2,3,4,6,12, i.e., the optional Q value is selected from 1,2,3,4,6,12.
In some embodiments, the trade-off is to reduce the signaling overhead and the accuracy of the indication, and Q bits may also be used to represent the actually transmitted synchronization signal block index or the actually transmitted beam index. In this case, the maximum Q value is not limited, and when the Q value is small, an effect of reducing signaling overhead can be achieved.
The maximum Q value may be greater than 16 or 12 when each bit in the synchronization signal block bitmap that is actually being transmitted represents multiple synchronization signal blocks.
In some embodiments, 1 bit in the actually transmitted synchronization signal block bitmap may represent 2 synchronization signal blocks, at which time X =2, at which time the maximum Q value may be greater than 16 or 12, e.g., may be 32, 18, 20, 24, 30.
Optionally, when the maximum Q value is 32, the elements of the set of Q values are taken from 1,2,4,8,16,32.
Optionally, when the maximum Q value is 18, the elements of the set of Q values are taken from 1,2,3,6,9,18.
Optionally, when the maximum Q value is 20, the elements of the set of Q values are taken from 1,2,4,5,10,20.
Optionally, when the maximum Q value is 24, the elements of the set of Q values are taken from 1,2,3,4,6,8,12,24.
Optionally, when the maximum Q value is 30, the elements of the set of Q values are taken from 1,2,3,5,6,10,15,30.
In some embodiments, 1 bit in the really transmitted synchronization signal block bitmap may represent 4 synchronization signal blocks, at which time X =4. In this case, 16 bits can represent 64 sync block indexes, and the maximum Q value may be greater than 16 or 12, for example, 64, 36, 40, 48, 60.
Optionally, when the maximum Q value is 64, the elements of the set of Q values are taken from 1,2,4,8,16,32,64.
Optionally, when the maximum Q value is 36, the elements of the set of Q values are taken from 1,2,3,4,6,9,12,18,36.
Optionally, when the maximum Q value is 40, the elements of the set of Q values are taken from 1,2,4,5,10,20,40.
Optionally, when the maximum Q value is 48, the elements of the set of Q values are taken from 1,2,3,4,6,8,12,16,24,48.
Optionally, when the maximum Q value is 54, the elements of the set of Q values are taken from 1,2,3,6,9,18,27,54.
Optionally, when the maximum Q value is 60, the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60.
After the value range of the Q value set element is determined, the Q value set can be further determined. Therefore, the range of the selectable Q value can be reduced, and the signaling overhead is saved.
When X =1, the elements of the set of Q values are taken from 1,2,4,8,16, or the elements of the set of Q values are taken from 1,2,3,4,6,12.
Optionally, when the elements of the set of Q values are taken from 1,2,4,8,16, or the maximum Q value is 16, the elements of the set of Q values comprise 2,4,8,16.
Optionally, when the elements of the set of Q values are taken from 1,2,3,4,6,12, or the maximum Q value is 12, the elements of the set of Q values comprise 3,4,6,12.
When X =2, the elements of the set of Q values are taken from 1,2,4,8,16,32, or the elements of the set of Q values are taken from 1,2,3,6,9,18, or the elements of the set of Q values are taken from 1,2,4,5,10,20, or the elements of the set of Q values are taken from 1,2,3,4,6,8,12,24, or the elements of the set of Q values are taken from 1,2,3,5,6,10,15,30.
Optionally, when the elements of the set of Q values are taken from 1,2,4,8,16,32, or the maximum Q value is 32, the elements of the set of Q values comprise 4,8,16,32.
Optionally, when the elements of the set of Q values are taken from 1,2,3,6,9,18, or the maximum Q value is 18, the elements of the set of Q values comprise 3,6,9,18.
Optionally, when the elements of the set of Q values are taken from 1,2,4,5,10,20, or the maximum Q value is 20, the elements of the set of Q values comprise 4,5,10,20.
Optionally, when the elements of the set of Q values are taken from 1,2,3,4,6,8,12,24, or the maximum Q value is 24, the elements of the set of Q values comprise 6,8,12,24.
Optionally, when the elements of the set of Q values are taken from 1,2,3,5,6,10,15,30, or the maximum Q value is 30, the elements of the set of Q values comprise 5,10,15,30.
When X =4, the elements of the set of Q values are taken from 1,2,4,8,16,32,64, or the elements of the set of Q values are taken from 1,2,3,4,6,9,12,18,36, or the elements of the set of Q values are taken from 1,2,4,5,10,20,40, or the elements of the set of Q values are taken from 1,2,3,4,6,8,12,16,24,48, or the elements of the set of Q values are taken from 1,2,3,6,9,18,27,54, or the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60.
Optionally, when an element of the set of Q values is taken from 1,2,4,8,16,32,64, or the maximum Q value is 64, the element of the set of Q values comprises 8,16,32,64.
Optionally, when the elements of the set of Q values are taken from 1,2,3,4,6,9,12,18,36, or the maximum Q value is 36, the elements of the set of Q values comprise 9,12,18,36.
Optionally, when the elements of the set of Q values are taken from 1,2,4,5,10,20,40, or the maximum Q value is 40, the elements of the set of Q values comprise 5,10,20,40.
Optionally, when the elements of the set of Q values are taken from 1,2,3,4,6,8,12,16,24,48, or the maximum Q value is 48, the elements of the set of Q values comprise 8,12,24,48.
Optionally, when an element of the set of Q values is taken from 1,2,3,6,9,18,27,54, or the maximum Q value is 54, the element of the set of Q values comprises 9,18,27,54.
Optionally, when the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60, or the maximum Q value is 60, the elements of the set of Q values comprise 15,20,30,60.
According to the data processing method provided by the embodiment of the application, the number X of the synchronous signal blocks corresponding to each bit in the synchronous signal block bitmap is determined, and the Q value of the quasi-common-site parameter can be determined according to the value of X. When the value of X is 1, the Q value is small, and the signaling overhead can be obviously reduced. When the value of X is larger than 1, the balance between the reduction of signaling overhead and the accuracy of indication can be achieved, and the value of the maximum Q value is not limited. After the value Q is determined by the value X, the actually transmitted synchronization signal block index or the actually transmitted beam index corresponding to all bits in the synchronization signal block bitmap can be determined.
Fig. 3 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present application, and as shown in fig. 3, the data processing apparatus includes a processing module 31, where:
the processing module 31 is configured to determine a number X of synchronization signal blocks corresponding to each bit in the synchronization signal block bitmap, where X is a positive integer greater than or equal to 1.
In a possible implementation, the processing module 31 is further configured to:
and determining a Q value of a quasi-common-site parameter according to the X.
In a possible implementation, the processing module 31 is specifically further configured to:
determining the Q value from the X, in a set of Q values.
In one possible implementation, the synchronization signal block bitmap includes 16 bits.
In one possible implementation, each bit in the synchronization signal block bitmap corresponds to an index or beam index of X synchronization signal blocks.
In one possible implementation, the Q values belong to a set of Q values.
In one possible implementation, the elements in the set of Q values are candidates for the Q value.
In one possible embodiment, X =1.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,12.
In one possible embodiment of the method according to the invention,
when an element of the set of Q values is taken from 1,2,4,8,16, or when the maximum Q value is 16, the element of the set of Q values comprises 2,4,8,16;
when the elements of the set of Q values are taken from 1,2,3,4,6,12, or when the maximum Q value is 12, the elements of the set of Q values comprise 3,4,6,12.
In one possible embodiment, X =2.
In one of the possible embodiments thereof,
the elements of the set of Q values are taken from 1,2,4,8,16,32; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18; alternatively, the first and second liquid crystal display panels may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,24; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,5,6,10,15,30.
In one possible embodiment of the method according to the invention,
when an element of the set of Q values is taken from 1,2,4,8,16,32, or when the maximum Q value is 32, the element of the set of Q values comprises 4,8,16,32;
when an element of the set of Q values is taken from 1,2,3,6,9,18, or when the maximum Q value is 18, the element of the set of Q values comprises 3,6,9,18;
when elements of the set of Q values are taken from 1,2,4,5,10,20, or when the maximum Q value is 20, the elements of the set of Q values comprise 4,5,10,20;
when an element of the set of Q values is taken from 1,2,3,4,6,8,12,24, or when the maximum Q value is 24, the element of the set of Q values comprises 6,8,12,24;
when the elements of the set of Q values are taken from 1,2,3,5,6,10,15,30, or when the maximum Q value is 30, the elements of the set of Q values comprise 5,10,15,30.
In one possible embodiment, X =4.
In one possible embodiment of the method according to the invention,
the elements of the set of Q values are taken from 1,2,4,8,16,32,64; alternatively, the first and second liquid crystal display panels may be,
the elements of the set of Q values are taken from 1,2,3,4,6,9,12,18,36; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20,40; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,16,24,48; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18,27,54; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60.
In one possible embodiment of the method according to the invention,
when an element of the set of Q values is taken from 1,2,4,8,16,32,64, or when the maximum Q value is 64, the element of the set of Q values comprises 8,16,32,64;
when an element of the set of Q values is taken from 1,2,3,4,6,9,12,18,36, or when the maximum Q value is 36, the element of the set of Q values comprises 9,12,18,36;
when an element of the set of Q values is taken from 1,2,4,5,10,20,40, or when the maximum Q value is 40, the element of the set of Q values comprises 5,10,20,40;
when an element of the set of Q values is taken from 1,2,3,4,6,8,12,16,24,48, or when the maximum Q value is 48, the element of the set of Q values comprises 8,12,24,48;
when an element of the set of Q values is taken from 1,2,3,6,9,18,27,54, or when the maximum Q value is 54, the element of the set of Q values comprises 9,18,27,54;
when the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60, or when the maximum Q value is 60, the elements of the set of Q values comprise 15,20,30,60.
The apparatus provided in the embodiment of the present application may be configured to implement the technical solution of the method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.
Fig. 4 is a schematic diagram of a hardware structure of a terminal device provided in an embodiment of the present application, and as shown in fig. 4, the terminal device includes: at least one processor 41 and a memory 42. The processor 41 and the memory 42 are connected by a bus 43.
Optionally, the model determination further comprises a communication component. For example, the communication component may include a receiver and/or a transmitter.
In a specific implementation, the at least one processor 41 executes computer-executable instructions stored by the memory 42, causing the at least one processor 41 to perform the data processing method as described above.
For a specific implementation process of the processor 41, reference may be made to the above method embodiments, which implement similar principles and technical effects, and this embodiment is not described herein again.
In the embodiment shown in fig. 4, it should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose processors, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the methods disclosed in the incorporated application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.
The memory may comprise high speed RAM memory and may also include non-volatile storage NVM, such as at least one disk memory.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored, and when a processor executes the computer-executable instructions, the data processing method as described above is implemented.
The computer-readable storage medium may be implemented by any type of volatile or non-volatile storage device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk. Readable storage media can be any available media that can be accessed by a general purpose or special purpose computer.
An exemplary readable storage medium is coupled to the processor such the processor can read information from, and write information to, the readable storage medium. Of course, the readable storage medium may also be an integral part of the processor. The processor and the readable storage medium may reside in an Application Specific Integrated Circuits (ASIC). Of course, the processor and the readable storage medium may also reside as discrete components in the apparatus.
The division of the units is only a logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions may be stored in a computer-readable storage medium if they are implemented in the form of software functional units and sold or used as separate products. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (18)

1. A data processing method is applied to a terminal device and comprises the following steps:
determining the number X of beam indexes of a synchronization signal block corresponding to each bit in a synchronization signal block bitmap, wherein X is a positive integer greater than or equal to 1.
2. The method of claim 1, further comprising:
and determining a Q value of a quasi-common-site parameter according to the X.
3. The method of claim 2, wherein determining a value of a quasi co-sited parameter Q based on the X comprises:
determining the Q value from the X, in a set of Q values.
4. The method of claim 1, wherein the synchronization signal block bitmap comprises 16 bits.
5. The method of claim 2, wherein the Q value belongs to a set of Q values.
6. The method of claim 2 wherein an element in the set of Q values is a candidate for the Q value.
7. The method of claim 5 or 6, wherein X =1.
8. The method of claim 7,
the elements of the set of Q values are taken from 1,2,4,8,16; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,12.
9. The method of claim 8,
elements of the set of Q values comprise 2,4,8,16; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 3,4,6,12.
10. The method of claim 5 or 6, wherein X =2.
11. The method of claim 10,
the elements of the set of Q values are taken from 1,2,4,8,16,32; alternatively, the first and second liquid crystal display panels may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,24; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,5,6,10,15,30.
12. The method of claim 11,
elements of the set of Q values comprise 4,8,16,32; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 3,6,9,18; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 4,5,10,20; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 6,8,12,24; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 5,10,15,30.
13. The method of claim 5 or 6, wherein X =4.
14. The method of claim 13,
the elements of the set of Q values are taken from 1,2,4,8,16,32,64; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,9,12,18,36; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,4,5,10,20,40; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,6,8,12,16,24,48; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,6,9,18,27,54; alternatively, the first and second electrodes may be,
the elements of the set of Q values are taken from 1,2,3,4,5,6,10,12,15,20,30,60.
15. The method of claim 14,
elements of the set of Q values comprise 8,16,32,64; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 9,12,18,36; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 5,10,20,40; alternatively, the first and second electrodes may be,
elements of the set of Q values comprise 8,12,24,48; alternatively, the first and second liquid crystal display panels may be,
elements of the set of Q values comprise 9,18,27,54; alternatively, the first and second electrodes may be,
the elements of the set of Q values include 15,20,30,60.
16. A data processing apparatus, comprising:
a processing module, configured to determine a number X of beam indexes of a synchronization signal block corresponding to each bit in a synchronization signal block bitmap, where X is a positive integer greater than or equal to 1.
17. A terminal device, comprising: at least one processor and a memory;
the memory stores computer-executable instructions;
execution of the computer-executable instructions stored by the memory by the at least one processor causes the at least one processor to perform the data processing method of any of claims 1 to 15.
18. A computer-readable storage medium having stored thereon computer-executable instructions which, when executed by a processor, implement a data processing method as claimed in any one of claims 1 to 15.
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